Lines Matching refs:ldr
179 ldr r2, [vcpu, #VCPU_PC]
180 ldr r3, [vcpu, #VCPU_CPSR]
185 ldr r2, [vcpu, #VCPU_USR_SP]
186 ldr r3, [vcpu, #VCPU_USR_LR]
332 ldr r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
335 ldr r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)]
336 ldr r7, [vcpu, #CP15_OFFSET(c10_AMAIR1)]
347 ldr r2, [vcpu, #CP15_OFFSET(c13_CID)]
348 ldr r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
349 ldr r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
350 ldr r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
351 ldr r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
352 ldr r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
353 ldr r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
354 ldr r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
355 ldr r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
356 ldr r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
357 ldr r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
375 ldr r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
376 ldr r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
377 ldr r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
378 ldr r5, [vcpu, #CP15_OFFSET(c3_DACR)]
383 ldr r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
384 ldr r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
385 ldr r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
406 ldr r2, [vcpu, #VCPU_KVM]
407 ldr r2, [r2, #KVM_VGIC_VCTRL]
415 ldr r4, [r2, #GICH_VMCR]
416 ldr r5, [r2, #GICH_MISR]
417 ldr r6, [r2, #GICH_EISR0]
418 ldr r7, [r2, #GICH_EISR1]
419 ldr r8, [r2, #GICH_ELRSR0]
420 ldr r9, [r2, #GICH_ELRSR1]
421 ldr r10, [r2, #GICH_APR]
452 ldr r4, [r11, #VGIC_CPU_NR_LR]
453 1: ldr r6, [r2], #4
468 ldr r2, [vcpu, #VCPU_KVM]
469 ldr r2, [r2, #KVM_VGIC_VCTRL]
477 ldr r3, [r11, #VGIC_V2_CPU_HCR]
478 ldr r4, [r11, #VGIC_V2_CPU_VMCR]
479 ldr r8, [r11, #VGIC_V2_CPU_APR]
491 ldr r4, [r11, #VGIC_CPU_NR_LR]
492 1: ldr r6, [r3], #4
511 ldr r4, [vcpu, #VCPU_KVM]
512 ldr r2, [r4, #KVM_TIMER_ENABLED]
522 ldr r4, =VCPU_TIMER_CNTV_CVAL
555 ldr r4, [vcpu, #VCPU_KVM]
556 ldr r2, [r4, #KVM_TIMER_ENABLED]
560 ldr r2, [r4, #KVM_TIMER_CNTVOFF]
561 ldr r3, [r4, #(KVM_TIMER_CNTVOFF + 4)]
564 ldr r4, =VCPU_TIMER_CNTV_CVAL
570 ldr r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
583 ldr r3, =HSTR_T(15)
625 ldr r3, =(HDCR_TPM|HDCR_TPMCR)