Lines Matching refs:ldr
46 ldr r1, =CPU_MASK
48 ldr r1, =CPU_CORTEX_A9
59 ldr r1, =CPU_MASK
61 ldr r1, =CPU_CORTEX_A9
66 ldr r1, [r0]
67 ldr r1, [r0, r1]
69 ldr r2, [r0]
70 ldr r2, [r0, r2]
76 ldr r2, [r0]
80 ldr r1, [r0, #L2X0_R_PHY_BASE]
85 ldr r2, [r1, #L2X0_CTRL]
89 ldr r1, [r0, #L2X0_R_TAG_LATENCY]
90 ldr r2, [r0, #L2X0_R_DATA_LATENCY]
91 ldr r3, [r0, #L2X0_R_PREFETCH_CTRL]
97 ldr r2, [r0]
100 ldr r1, [r0, #L2X0_R_PWR_CTRL]
101 ldr r2, [r0, #L2X0_R_AUX_CTRL]