Lines Matching refs:ldr

55 	ldr 	ip, CACHE_FLUSH
65 	ldr	ip, [r0, #DDR2_SDRCR_OFFSET]
70 	ldr	ip, [r0, #DDR2_SDRCR_OFFSET]
85 	ldr	ip, [r3, #PLLDIV1]
90 	ldr	ip, [r3, #PLLCTL]
101 	ldr	ip, [r3, #PLLCTL]
106 	ldr	ip, [r4]
114 	ldr	ip, [r4]
121 	ldr	ip, [r3, #PLLCTL]
126 	ldr	ip, [r3, #PLLCTL]
135 	ldr	ip, [r3, #PLLCTL]
145 	ldr	ip, [r3, #PLLCTL]
152 	ldr	ip, [r3, #PLLDIV1]
166 	ldr	ip, [r0, #DDR2_SDRCR_OFFSET]
170 	ldr	ip, [r0, #DDR2_SDRCR_OFFSET]
190 	ldr	ip, [r1, r6]
196 	ldr	ip, [r1, #PTCMD]
202 	ldr	ip, [r1, #PTSTAT]
211 	ldr	ip, [r1, r6]