Lines Matching refs:ldr

74 	ldr	x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
75 	ldr	x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
76 	ldr	x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
84 	ldr	x21, [x3, #16]
169 	ldr	x18, [x3, #144]
332 	ldr	x21, [x4, #(15 * 8)]
333 	ldr	x20, [x4, #(14 * 8)]
334 	ldr	x19, [x4, #(13 * 8)]
335 	ldr	x18, [x4, #(12 * 8)]
336 	ldr	x17, [x4, #(11 * 8)]
337 	ldr	x16, [x4, #(10 * 8)]
338 	ldr	x15, [x4, #(9 * 8)]
339 	ldr	x14, [x4, #(8 * 8)]
340 	ldr	x13, [x4, #(7 * 8)]
341 	ldr	x12, [x4, #(6 * 8)]
342 	ldr	x11, [x4, #(5 * 8)]
343 	ldr	x10, [x4, #(4 * 8)]
344 	ldr	x9, [x4, #(3 * 8)]
345 	ldr	x8, [x4, #(2 * 8)]
346 	ldr	x7, [x4, #(1 * 8)]
347 	ldr	x6, [x4, #(0 * 8)]
384 	ldr	\tmp, [x0, #VCPU_DEBUG_FLAGS]
402 	ldr	x25, [x25, #CPU_SYSREG_OFFSET(MDSCR_EL1)]
463 	ldr	x7, [x3, #24]
469 	ldr     x2, [x0, #VCPU_HCR_EL2]
492 	ldr	x2, [x0, #VCPU_MDCR_EL2]
507 	ldr	x1, [x0, #VCPU_KVM]
509 	ldr	x2, [x1, #KVM_VTTBR]
538 	ldr	x25, [x0, #VCPU_IRQ_LINES]
551 	ldr	x2, [x0, #VCPU_KVM]
553 	ldr	w3, [x2, #KVM_TIMER_ENABLED]
587 	ldr	x2, [x0, #VCPU_KVM]
589 	ldr	w3, [x2, #KVM_TIMER_ENABLED]
592 	ldr	x3, [x2, #KVM_TIMER_CNTVOFF]
594 	ldr	x2, [x0, #VCPU_TIMER_CNTV_CVAL]
598 	ldr	w2, [x0, #VCPU_TIMER_CNTV_CTL]
666 	ldr	x21, [x2, #CPU_SYSREG_OFFSET(MDCCINT_EL1)]
691 	ldr	x2, [x0, #VCPU_HOST_CONTEXT]
699 	ldr	x4, [x2, #CPU_SYSREG_OFFSET(FPEXC32_EL2)]
724 	ldr	x2, [x0, #VCPU_HOST_CONTEXT]
749 	ldr	x3, [x0, #VCPU_DEBUG_PTR]
770 	ldr	x3, [x0, #VCPU_DEBUG_PTR]
783 	ldr	x2, [x0, #VCPU_HOST_CONTEXT]
810 	ldr	x2, [x0, #KVM_VTTBR]
846 	ldr     x2, [x0, #KVM_VTTBR]
882 	ldr	x2, [x0, #VCPU_HOST_CONTEXT]
891 	ldr	x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
911 	ldr	lr, =panic