Home
last modified time | relevance | path

Searched refs:cs (Results 1 – 200 of 796) sorted by relevance

1234

/linux-4.4.14/drivers/isdn/hisax/
Dicc.c32 ICCVersion(struct IsdnCardState *cs, char *s) in ICCVersion() argument
36 val = cs->readisac(cs, ICC_RBCH); in ICCVersion()
41 ph_command(struct IsdnCardState *cs, unsigned int command) in ph_command() argument
43 if (cs->debug & L1_DEB_ISAC) in ph_command()
44 debugl1(cs, "ph_command %x", command); in ph_command()
45 cs->writeisac(cs, ICC_CIX0, (command << 2) | 3); in ph_command()
50 icc_new_ph(struct IsdnCardState *cs) in icc_new_ph() argument
52 switch (cs->dc.icc.ph_state) { in icc_new_ph()
54 ph_command(cs, ICC_CMD_DI); in icc_new_ph()
55 l1_msg(cs, HW_RESET | INDICATION, NULL); in icc_new_ph()
[all …]
Disac.c31 void ISACVersion(struct IsdnCardState *cs, char *s) in ISACVersion() argument
35 val = cs->readisac(cs, ISAC_RBCH); in ISACVersion()
40 ph_command(struct IsdnCardState *cs, unsigned int command) in ph_command() argument
42 if (cs->debug & L1_DEB_ISAC) in ph_command()
43 debugl1(cs, "ph_command %x", command); in ph_command()
44 cs->writeisac(cs, ISAC_CIX0, (command << 2) | 3); in ph_command()
49 isac_new_ph(struct IsdnCardState *cs) in isac_new_ph() argument
51 switch (cs->dc.isac.ph_state) { in isac_new_ph()
54 ph_command(cs, ISAC_CMD_DUI); in isac_new_ph()
55 l1_msg(cs, HW_RESET | INDICATION, NULL); in isac_new_ph()
[all …]
Damd7930_fn.c64 static void Amd7930_new_ph(struct IsdnCardState *cs);
102 WriteWordAmd7930(struct IsdnCardState *cs, BYTE reg, WORD val) in WriteWordAmd7930() argument
104 wByteAMD(cs, 0x00, reg); in WriteWordAmd7930()
105 wByteAMD(cs, 0x01, LOBYTE(val)); in WriteWordAmd7930()
106 wByteAMD(cs, 0x01, HIBYTE(val)); in WriteWordAmd7930()
110 ReadWordAmd7930(struct IsdnCardState *cs, BYTE reg) in ReadWordAmd7930() argument
115 res = rByteAMD(cs, reg); in ReadWordAmd7930()
116 res += 256 * rByteAMD(cs, reg); in ReadWordAmd7930()
120 wByteAMD(cs, 0x00, reg); in ReadWordAmd7930()
121 res = rByteAMD(cs, 0x01); in ReadWordAmd7930()
[all …]
Delsa.c136 static void set_arcofi(struct IsdnCardState *cs, int bc);
176 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
178 return (readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset)); in ReadISAC()
182 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
184 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset, value); in WriteISAC()
188 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
190 readfifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0, data, size); in ReadISACfifo()
194 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
196 writefifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0, data, size); in WriteISACfifo()
200 ReadISAC_IPAC(struct IsdnCardState *cs, u_char offset) in ReadISAC_IPAC() argument
[all …]
Dhfc_sx.c62 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val) in Write_hfc() argument
64 byteout(cs->hw.hfcsx.base + 1, regnum); in Write_hfc()
65 byteout(cs->hw.hfcsx.base, val); in Write_hfc()
69 Read_hfc(struct IsdnCardState *cs, u_char regnum) in Read_hfc() argument
73 byteout(cs->hw.hfcsx.base + 1, regnum); in Read_hfc()
74 ret = bytein(cs->hw.hfcsx.base); in Read_hfc()
83 fifo_select(struct IsdnCardState *cs, u_char fifo) in fifo_select() argument
85 if (fifo == cs->hw.hfcsx.last_fifo) in fifo_select()
88 byteout(cs->hw.hfcsx.base + 1, HFCSX_FIF_SEL); in fifo_select()
89 byteout(cs->hw.hfcsx.base, fifo); in fifo_select()
[all …]
Dipacx.c35 static void ph_command(struct IsdnCardState *cs, unsigned int command);
36 static inline void cic_int(struct IsdnCardState *cs);
38 static void dbusy_timer_handler(struct IsdnCardState *cs);
39 static void dch_empty_fifo(struct IsdnCardState *cs, int count);
40 static void dch_fill_fifo(struct IsdnCardState *cs);
41 static inline void dch_int(struct IsdnCardState *cs);
42 static void dch_setstack(struct PStack *st, struct IsdnCardState *cs);
43 static void dch_init(struct IsdnCardState *cs);
47 static void bch_int(struct IsdnCardState *cs, u_char hscx);
50 static int bch_open_state(struct IsdnCardState *cs, struct BCState *bcs);
[all …]
Dhfc_2bds0.c29 dummyf(struct IsdnCardState *cs, u_char *data, int size) in dummyf() argument
35 ReadReg(struct IsdnCardState *cs, int data, u_char reg) in ReadReg() argument
40 if (cs->hw.hfcD.cip != reg) { in ReadReg()
41 cs->hw.hfcD.cip = reg; in ReadReg()
42 byteout(cs->hw.hfcD.addr | 1, reg); in ReadReg()
44 ret = bytein(cs->hw.hfcD.addr); in ReadReg()
46 if (cs->debug & L1_DEB_HSCX_FIFO && (data != 2)) in ReadReg()
47 debugl1(cs, "t3c RD %02x %02x", reg, ret); in ReadReg()
50 ret = bytein(cs->hw.hfcD.addr | 1); in ReadReg()
55 WriteReg(struct IsdnCardState *cs, int data, u_char reg, u_char value) in WriteReg() argument
[all …]
Dw6692.c51 W6692Version(struct IsdnCardState *cs, char *s) in W6692Version() argument
55 val = cs->readW6692(cs, W_D_RBCH); in W6692Version()
60 ph_command(struct IsdnCardState *cs, unsigned int command) in ph_command() argument
62 if (cs->debug & L1_DEB_ISAC) in ph_command()
63 debugl1(cs, "ph_command %x", command); in ph_command()
64 cs->writeisac(cs, W_CIX, command); in ph_command()
69 W6692_new_ph(struct IsdnCardState *cs) in W6692_new_ph() argument
71 switch (cs->dc.w6692.ph_state) { in W6692_new_ph()
73 ph_command(cs, W_L1CMD_DRC); in W6692_new_ph()
74 l1_msg(cs, HW_RESET | INDICATION, NULL); in W6692_new_ph()
[all …]
Dsedlbauer.c154 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
156 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset)); in ReadISAC()
160 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
162 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset, value); in WriteISAC()
166 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
168 readfifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0, data, size); in ReadISACfifo()
172 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
174 writefifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0, data, size); in WriteISACfifo()
178 ReadISAC_IPAC(struct IsdnCardState *cs, u_char offset) in ReadISAC_IPAC() argument
180 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset | 0x80)); in ReadISAC_IPAC()
[all …]
Denternow_pci.c97 ReadByteAmd7930(struct IsdnCardState *cs, unsigned char offset) in ReadByteAmd7930() argument
101 return (inb(cs->hw.njet.isac + 4 * offset)); in ReadByteAmd7930()
105 outb(offset, cs->hw.njet.isac + 4 * AMD_CR); in ReadByteAmd7930()
106 return (inb(cs->hw.njet.isac + 4 * AMD_DR)); in ReadByteAmd7930()
112 WriteByteAmd7930(struct IsdnCardState *cs, unsigned char offset, unsigned char value) in WriteByteAmd7930() argument
116 outb(value, cs->hw.njet.isac + 4 * offset); in WriteByteAmd7930()
120 outb(offset, cs->hw.njet.isac + 4 * AMD_CR); in WriteByteAmd7930()
121 outb(value, cs->hw.njet.isac + 4 * AMD_DR); in WriteByteAmd7930()
127 enpci_setIrqMask(struct IsdnCardState *cs, unsigned char val) { in enpci_setIrqMask() argument
129 outb(0x00, cs->hw.njet.base + NETJET_IRQMASK1); in enpci_setIrqMask()
[all …]
Dhfc_pci.c73 release_io_hfcpci(struct IsdnCardState *cs) in release_io_hfcpci() argument
76 cs->hw.hfcpci.pci_io); in release_io_hfcpci()
77 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */ in release_io_hfcpci()
78 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in release_io_hfcpci()
79 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */ in release_io_hfcpci()
81 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */ in release_io_hfcpci()
83 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in release_io_hfcpci()
84 …pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, 0); /* disable memory mapped ports + busmast… in release_io_hfcpci()
85 del_timer(&cs->hw.hfcpci.timer); in release_io_hfcpci()
86 pci_free_consistent(cs->hw.hfcpci.dev, 0x8000, in release_io_hfcpci()
[all …]
Dnj_u.c19 static u_char dummyrr(struct IsdnCardState *cs, int chan, u_char off) in dummyrr() argument
24 static void dummywr(struct IsdnCardState *cs, int chan, u_char off, u_char value) in dummywr() argument
31 struct IsdnCardState *cs = dev_id; in netjet_u_interrupt() local
35 spin_lock_irqsave(&cs->lock, flags); in netjet_u_interrupt()
36 if (!((sval = bytein(cs->hw.njet.base + NETJET_IRQSTAT1)) & in netjet_u_interrupt()
38 val = NETjet_ReadIC(cs, ICC_ISTA); in netjet_u_interrupt()
39 if (cs->debug & L1_DEB_ISAC) in netjet_u_interrupt()
40 debugl1(cs, "tiger: i1 %x %x", sval, val); in netjet_u_interrupt()
42 icc_interrupt(cs, val); in netjet_u_interrupt()
43 NETjet_WriteIC(cs, ICC_MASK, 0xFF); in netjet_u_interrupt()
[all …]
Dhfcscard.c24 struct IsdnCardState *cs = dev_id; in hfcs_interrupt() local
28 spin_lock_irqsave(&cs->lock, flags); in hfcs_interrupt()
30 (stat = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_STAT))) { in hfcs_interrupt()
31 val = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_INT_S1); in hfcs_interrupt()
32 if (cs->debug & L1_DEB_ISAC) in hfcs_interrupt()
33 debugl1(cs, "HFCS: stat(%02x) s1(%02x)", stat, val); in hfcs_interrupt()
34 hfc2bds0_interrupt(cs, val); in hfcs_interrupt()
36 if (cs->debug & L1_DEB_ISAC) in hfcs_interrupt()
37 debugl1(cs, "HFCS: irq_no_irq stat(%02x)", stat); in hfcs_interrupt()
39 spin_unlock_irqrestore(&cs->lock, flags); in hfcs_interrupt()
[all …]
Dteles3.c56 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
58 return (readreg(cs->hw.teles3.isac, offset)); in ReadISAC()
62 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
64 writereg(cs->hw.teles3.isac, offset, value); in WriteISAC()
68 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
70 read_fifo(cs->hw.teles3.isacfifo, data, size); in ReadISACfifo()
74 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
76 write_fifo(cs->hw.teles3.isacfifo, data, size); in WriteISACfifo()
80 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
82 return (readreg(cs->hw.teles3.hscx[hscx], offset)); in ReadHSCX()
[all …]
Dnj_s.c19 static u_char dummyrr(struct IsdnCardState *cs, int chan, u_char off) in dummyrr() argument
24 static void dummywr(struct IsdnCardState *cs, int chan, u_char off, u_char value) in dummywr() argument
31 struct IsdnCardState *cs = dev_id; in netjet_s_interrupt() local
35 spin_lock_irqsave(&cs->lock, flags); in netjet_s_interrupt()
36 s1val = bytein(cs->hw.njet.base + NETJET_IRQSTAT1); in netjet_s_interrupt()
38 val = NETjet_ReadIC(cs, ISAC_ISTA); in netjet_s_interrupt()
39 if (cs->debug & L1_DEB_ISAC) in netjet_s_interrupt()
40 debugl1(cs, "tiger: i1 %x %x", s1val, val); in netjet_s_interrupt()
42 isac_interrupt(cs, val); in netjet_s_interrupt()
43 NETjet_WriteIC(cs, ISAC_MASK, 0xFF); in netjet_s_interrupt()
[all …]
Darcofi.c22 add_arcofi_timer(struct IsdnCardState *cs) { in add_arcofi_timer() argument
23 if (test_and_set_bit(FLG_ARCOFI_TIMER, &cs->HW_Flags)) { in add_arcofi_timer()
24 del_timer(&cs->dc.isac.arcofitimer); in add_arcofi_timer()
26 init_timer(&cs->dc.isac.arcofitimer); in add_arcofi_timer()
27 cs->dc.isac.arcofitimer.expires = jiffies + ((ARCOFI_TIMER_VALUE * HZ) / 1000); in add_arcofi_timer()
28 add_timer(&cs->dc.isac.arcofitimer); in add_arcofi_timer()
32 send_arcofi(struct IsdnCardState *cs) { in send_arcofi() argument
33 add_arcofi_timer(cs); in send_arcofi()
34 cs->dc.isac.mon_txp = 0; in send_arcofi()
35 cs->dc.isac.mon_txc = cs->dc.isac.arcofi_list->len; in send_arcofi()
[all …]
Ddiva.c132 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
134 return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset)); in ReadISAC()
138 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
140 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset, value); in WriteISAC()
144 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
146 readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size); in ReadISACfifo()
150 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
152 writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size); in WriteISACfifo()
156 ReadISAC_IPAC(struct IsdnCardState *cs, u_char offset) in ReadISAC_IPAC() argument
158 return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset + 0x80)); in ReadISAC_IPAC()
[all …]
Dasuscom.c78 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
80 return (readreg(cs->hw.asus.adr, cs->hw.asus.isac, offset)); in ReadISAC()
84 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
86 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset, value); in WriteISAC()
90 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
92 readfifo(cs->hw.asus.adr, cs->hw.asus.isac, 0, data, size); in ReadISACfifo()
96 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
98 writefifo(cs->hw.asus.adr, cs->hw.asus.isac, 0, data, size); in WriteISACfifo()
102 ReadISAC_IPAC(struct IsdnCardState *cs, u_char offset) in ReadISAC_IPAC() argument
104 return (readreg(cs->hw.asus.adr, cs->hw.asus.isac, offset | 0x80)); in ReadISAC_IPAC()
[all …]
Dhscx.c26 HscxVersion(struct IsdnCardState *cs, char *s) in HscxVersion() argument
30 verA = cs->BC_Read_Reg(cs, 0, HSCX_VSTR) & 0xf; in HscxVersion()
31 verB = cs->BC_Read_Reg(cs, 1, HSCX_VSTR) & 0xf; in HscxVersion()
43 struct IsdnCardState *cs = bcs->cs; in modehscx() local
46 if (cs->debug & L1_DEB_HSCX) in modehscx()
47 debugl1(cs, "hscx %c mode %d ichan %d", in modehscx()
51 cs->BC_Write_Reg(cs, hscx, HSCX_XAD1, 0xFF); in modehscx()
52 cs->BC_Write_Reg(cs, hscx, HSCX_XAD2, 0xFF); in modehscx()
53 cs->BC_Write_Reg(cs, hscx, HSCX_RAH2, 0xFF); in modehscx()
54 cs->BC_Write_Reg(cs, hscx, HSCX_XBCH, 0x0); in modehscx()
[all …]
Davm_a1.c56 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
58 return (readreg(cs->hw.avm.isac, offset)); in ReadISAC()
62 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
64 writereg(cs->hw.avm.isac, offset, value); in WriteISAC()
68 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
70 read_fifo(cs->hw.avm.isacfifo, data, size); in ReadISACfifo()
74 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
76 write_fifo(cs->hw.avm.isacfifo, data, size); in WriteISACfifo()
80 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
82 return (readreg(cs->hw.avm.hscx[hscx], offset)); in ReadHSCX()
[all …]
Dsaphir.c68 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
70 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset)); in ReadISAC()
74 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
76 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset, value); in WriteISAC()
80 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
82 readfifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size); in ReadISACfifo()
86 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
88 writefifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size); in WriteISACfifo()
92 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
94 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, in ReadHSCX()
[all …]
Djade.c24 JadeVersion(struct IsdnCardState *cs, char *s) in JadeVersion() argument
28 cs->BC_Write_Reg(cs, -1, 0x50, 0x19); in JadeVersion()
31 ver = cs->BC_Read_Reg(cs, -1, 0x60); in JadeVersion()
43 ver = cs->BC_Read_Reg(cs, -1, 0x60); in JadeVersion()
50 jade_write_indirect(struct IsdnCardState *cs, u_char reg, u_char value) in jade_write_indirect() argument
56 cs->BC_Write_Reg(cs, -1, COMM_JADE + 1, value); in jade_write_indirect()
58 cs->BC_Write_Reg(cs, -1, COMM_JADE, reg); in jade_write_indirect()
63 ret = cs->BC_Read_Reg(cs, -1, COMM_JADE); in jade_write_indirect()
80 struct IsdnCardState *cs = bcs->cs; in modejade() local
83 if (cs->debug & L1_DEB_HSCX) { in modejade()
[all …]
Disurf.c37 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
39 return (readb(cs->hw.isurf.isac + offset)); in ReadISAC()
43 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
45 writeb(value, cs->hw.isurf.isac + offset); mb(); in WriteISAC()
49 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
53 data[i] = readb(cs->hw.isurf.isac); in ReadISACfifo()
57 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
61 writeb(data[i], cs->hw.isurf.isac); mb(); in WriteISACfifo()
72 ReadISAR(struct IsdnCardState *cs, int mode, u_char offset) in ReadISAR() argument
74 return (readb(cs->hw.isurf.isar + offset)); in ReadISAR()
[all …]
Dgazel.c104 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
108 switch (cs->subtyp) { in ReadISAC()
112 return (readreg(cs->hw.gazel.isac, off2)); in ReadISAC()
115 return (readreg_ipac(cs->hw.gazel.ipac, 0x80 + off2)); in ReadISAC()
121 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
125 switch (cs->subtyp) { in WriteISAC()
129 writereg(cs->hw.gazel.isac, off2, value); in WriteISAC()
133 writereg_ipac(cs->hw.gazel.ipac, 0x80 + off2, value); in WriteISAC()
139 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
141 switch (cs->subtyp) { in ReadISACfifo()
[all …]
Dteleint.c103 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
105 cs->hw.hfc.cip = offset; in ReadISAC()
106 return (readreg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset)); in ReadISAC()
110 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
112 cs->hw.hfc.cip = offset; in WriteISAC()
113 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset, value); in WriteISAC()
117 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
119 cs->hw.hfc.cip = 0; in ReadISACfifo()
120 readfifo(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, 0, data, size); in ReadISACfifo()
124 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
[all …]
Delsa_ser.c48 static inline unsigned int serial_in(struct IsdnCardState *cs, int offset) in serial_in() argument
51 u_int val = inb(cs->hw.elsa.base + 8 + offset); in serial_in()
52 debugl1(cs, "in %s %02x", ModemIn[offset], val); in serial_in()
55 return inb(cs->hw.elsa.base + 8 + offset); in serial_in()
59 static inline unsigned int serial_inp(struct IsdnCardState *cs, int offset) in serial_inp() argument
63 u_int val = inb(cs->hw.elsa.base + 8 + offset); in serial_inp()
64 debugl1(cs, "inp %s %02x", ModemIn[offset], val); in serial_inp()
66 u_int val = inb_p(cs->hw.elsa.base + 8 + offset); in serial_inp()
67 debugl1(cs, "inP %s %02x", ModemIn[offset], val); in serial_inp()
72 return inb(cs->hw.elsa.base + 8 + offset); in serial_inp()
[all …]
Dsportster.c54 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
56 return (bytein(calc_off(cs->hw.spt.isac, offset))); in ReadISAC()
60 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
62 byteout(calc_off(cs->hw.spt.isac, offset), value); in WriteISAC()
66 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
68 read_fifo(cs->hw.spt.isac, data, size); in ReadISACfifo()
72 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
74 write_fifo(cs->hw.spt.isac, data, size); in WriteISACfifo()
78 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
80 return (bytein(calc_off(cs->hw.spt.hscx[hscx], offset))); in ReadHSCX()
[all …]
Dniccy.c78 static u_char ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
80 return readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset); in ReadISAC()
83 static void WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
85 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset, value); in WriteISAC()
88 static void ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
90 readfifo(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, 0, data, size); in ReadISACfifo()
93 static void WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
95 writefifo(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, 0, data, size); in WriteISACfifo()
98 static u_char ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
100 return readreg(cs->hw.niccy.hscx_ale, in ReadHSCX()
[all …]
Dmic.c66 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
68 return (readreg(cs->hw.mic.adr, cs->hw.mic.isac, offset)); in ReadISAC()
72 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
74 writereg(cs->hw.mic.adr, cs->hw.mic.isac, offset, value); in WriteISAC()
78 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
80 readfifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size); in ReadISACfifo()
84 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
86 writefifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size); in WriteISACfifo()
90 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
92 return (readreg(cs->hw.mic.adr, in ReadHSCX()
[all …]
Dbkm_a8.c78 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
80 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80)); in ReadISAC()
84 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
86 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value); in WriteISAC()
90 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
92 readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size); in ReadISACfifo()
96 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
98 writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size); in WriteISACfifo()
103 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
105 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
[all …]
Ds0box.c96 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
98 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset)); in ReadISAC()
102 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
104 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value); in WriteISAC()
108 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
110 read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size); in ReadISACfifo()
114 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
116 write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size); in WriteISACfifo()
120 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
122 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset)); in ReadHSCX()
[all …]
Dbkm_a4t.c74 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
76 return (readreg(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, offset)); in ReadISAC()
80 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
82 writereg(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, offset, value); in WriteISAC()
86 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
88 readfifo(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, 0, data, size); in ReadISACfifo()
92 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
94 writefifo(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, 0, data, size); in WriteISACfifo()
98 ReadJADE(struct IsdnCardState *cs, int jade, u_char offset) in ReadJADE() argument
100 …return (readreg(cs->hw.ax.jade_ale, cs->hw.ax.jade_adr, offset + (jade == -1 ? 0 : (jade ? 0xC0 : … in ReadJADE()
[all …]
Dhfc_2bs0.c22 WaitForBusy(struct IsdnCardState *cs) in WaitForBusy() argument
27 while (!(cs->BC_Read_Reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) { in WaitForBusy()
28 val = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2 | in WaitForBusy()
29 (cs->hw.hfc.cip & 3)); in WaitForBusy()
41 WaitNoBusy(struct IsdnCardState *cs) in WaitNoBusy() argument
45 while ((cs->BC_Read_Reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) { in WaitNoBusy()
62 return (bcs->cs->hw.hfc.fifosize); in GetFreeFifoBytes()
65 s += bcs->cs->hw.hfc.fifosize; in GetFreeFifoBytes()
66 s = bcs->cs->hw.hfc.fifosize - s; in GetFreeFifoBytes()
75 WaitNoBusy(bcs->cs); in ReadZReg()
[all …]
Davm_a1p.c62 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
67 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_REG_OFFSET + offset); in ReadISAC()
68 ret = bytein(cs->hw.avm.cfg_reg + DATAREG_OFFSET); in ReadISAC()
73 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
76 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_REG_OFFSET + offset); in WriteISAC()
77 byteout(cs->hw.avm.cfg_reg + DATAREG_OFFSET, value); in WriteISAC()
81 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
83 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_FIFO_OFFSET); in ReadISACfifo()
84 insb(cs->hw.avm.cfg_reg + DATAREG_OFFSET, data, size); in ReadISACfifo()
88 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
[all …]
Dteles0.c98 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
100 return (readisac(cs->hw.teles0.membase, offset)); in ReadISAC()
104 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
106 writeisac(cs->hw.teles0.membase, offset, value); in WriteISAC()
110 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
112 read_fifo_isac(cs->hw.teles0.membase, data, size); in ReadISACfifo()
116 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
118 write_fifo_isac(cs->hw.teles0.membase, data, size); in WriteISACfifo()
122 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
124 return (readhscx(cs->hw.teles0.membase, hscx, offset)); in ReadHSCX()
[all …]
Dix1_micro.c76 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
78 return (readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset)); in ReadISAC()
82 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
84 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset, value); in WriteISAC()
88 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
90 readfifo(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, 0, data, size); in ReadISACfifo()
94 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
96 writefifo(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, 0, data, size); in WriteISACfifo()
100 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
102 return (readreg(cs->hw.ix1.hscx_ale, in ReadHSCX()
[all …]
Davm_pci.c78 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
83 outb(idx, cs->hw.avm.cfg_reg + 4); in ReadISAC()
84 val = inb(cs->hw.avm.isac + (offset & 0xf)); in ReadISAC()
89 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
93 outb(idx, cs->hw.avm.cfg_reg + 4); in WriteISAC()
94 outb(value, cs->hw.avm.isac + (offset & 0xf)); in WriteISAC()
98 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
100 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4); in ReadISACfifo()
101 insb(cs->hw.avm.isac, data, size); in ReadISACfifo()
105 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
[all …]
Disar.c31 static void isar_setup(struct IsdnCardState *cs);
36 waitforHIA(struct IsdnCardState *cs, int timeout) in waitforHIA() argument
39 while ((cs->BC_Read_Reg(cs, 0, ISAR_HIA) & 1) && timeout) { in waitforHIA()
50 sendmsg(struct IsdnCardState *cs, u_char his, u_char creg, u_char len, in sendmsg() argument
55 if (!waitforHIA(cs, 4000)) in sendmsg()
58 if (cs->debug & L1_DEB_HSCX) in sendmsg()
59 debugl1(cs, "sendmsg(%02x,%02x,%d)", his, creg, len); in sendmsg()
61 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_H, creg); in sendmsg()
62 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_L, len); in sendmsg()
63 cs->BC_Write_Reg(cs, 0, ISAR_WADR, 0); in sendmsg()
[all …]
Dhscx_irq.c17 waitforCEC(struct IsdnCardState *cs, int hscx) in waitforCEC() argument
21 while ((READHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) { in waitforCEC()
31 waitforXFW(struct IsdnCardState *cs, int hscx) in waitforXFW() argument
35 while (((READHSCX(cs, hscx, HSCX_STAR) & 0x44) != 0x40) && to) { in waitforXFW()
44 WriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data) in WriteHSCXCMDR() argument
46 waitforCEC(cs, hscx); in WriteHSCXCMDR()
47 WRITEHSCX(cs, hscx, HSCX_CMDR, data); in WriteHSCXCMDR()
56 struct IsdnCardState *cs = bcs->cs; in hscx_empty_fifo() local
58 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) in hscx_empty_fifo()
59 debugl1(cs, "hscx_empty_fifo"); in hscx_empty_fifo()
[all …]
Dtelespci.c181 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
183 return (readisac(cs->hw.teles0.membase, offset)); in ReadISAC()
187 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
189 writeisac(cs->hw.teles0.membase, offset, value); in WriteISAC()
193 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
195 read_fifo_isac(cs->hw.teles0.membase, data, size); in ReadISACfifo()
199 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
201 write_fifo_isac(cs->hw.teles0.membase, data, size); in WriteISACfifo()
205 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
207 return (readhscx(cs->hw.teles0.membase, hscx, offset)); in ReadHSCX()
[all …]
Dnetjet.c31 NETjet_ReadIC(struct IsdnCardState *cs, u_char offset) in NETjet_ReadIC() argument
35 cs->hw.njet.auxd &= 0xfc; in NETjet_ReadIC()
36 cs->hw.njet.auxd |= (offset >> 4) & 3; in NETjet_ReadIC()
37 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); in NETjet_ReadIC()
38 ret = bytein(cs->hw.njet.isac + ((offset & 0xf) << 2)); in NETjet_ReadIC()
43 NETjet_WriteIC(struct IsdnCardState *cs, u_char offset, u_char value) in NETjet_WriteIC() argument
45 cs->hw.njet.auxd &= 0xfc; in NETjet_WriteIC()
46 cs->hw.njet.auxd |= (offset >> 4) & 3; in NETjet_WriteIC()
47 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); in NETjet_WriteIC()
48 byteout(cs->hw.njet.isac + ((offset & 0xf) << 2), value); in NETjet_WriteIC()
[all …]
Dconfig.c579 if (cards[i].cs) in hisax_findcard()
580 if (cards[i].cs->myid == driverid) in hisax_findcard()
581 return cards[i].cs; in hisax_findcard()
592 if (cards[cardnr - 1].cs)
593 return cards[cardnr - 1].cs;
602 struct IsdnCardState *cs = hisax_findcard(id); in HiSax_readstatus() local
604 if (cs) { in HiSax_readstatus()
610 count = cs->status_end - cs->status_read + 1; in HiSax_readstatus()
613 if (copy_to_user(p, cs->status_read, count)) in HiSax_readstatus()
615 cs->status_read += count; in HiSax_readstatus()
[all …]
Djade_irq.c14 waitforCEC(struct IsdnCardState *cs, int jade, int reg) in waitforCEC() argument
18 while ((READJADE(cs, jade, jade_HDLC_STAR) & mask) && to) { in waitforCEC()
28 waitforXFW(struct IsdnCardState *cs, int jade) in waitforXFW() argument
34 WriteJADECMDR(struct IsdnCardState *cs, int jade, int reg, u_char data) in WriteJADECMDR() argument
36 waitforCEC(cs, jade, reg); in WriteJADECMDR()
37 WRITEJADE(cs, jade, reg, data); in WriteJADECMDR()
46 struct IsdnCardState *cs = bcs->cs; in jade_empty_fifo() local
48 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) in jade_empty_fifo()
49 debugl1(cs, "jade_empty_fifo"); in jade_empty_fifo()
52 if (cs->debug & L1_DEB_WARN) in jade_empty_fifo()
[all …]
Damd7930_fn.h19 #define rByteAMD(cs, reg) cs->readisac(cs, reg) argument
20 #define wByteAMD(cs, reg, val) cs->writeisac(cs, reg, val) argument
21 #define rWordAMD(cs, reg) ReadWordAmd7930(cs, reg) argument
22 #define wWordAMD(cs, reg, val) WriteWordAmd7930(cs, reg, val) argument
26 #define AmdIrqOff(cs) cs->dc.amd7930.setIrqMask(cs, 0) argument
27 #define AmdIrqOn(cs) cs->dc.amd7930.setIrqMask(cs, 1) argument
Disdnl1.c130 debugl1(struct IsdnCardState *cs, char *fmt, ...) in debugl1() argument
136 sprintf(tmp, "Card%d ", cs->cardnr + 1); in debugl1()
137 VHiSax_putstatus(cs, tmp, fmt, args); in debugl1()
146 struct IsdnCardState *cs = st->l1.hardware; in l1m_debug() local
150 sprintf(tmp, "Card%d ", cs->cardnr + 1); in l1m_debug()
151 VHiSax_putstatus(cs, tmp, fmt, args); in l1m_debug()
156 L1activated(struct IsdnCardState *cs) in L1activated() argument
160 st = cs->stlist; in L1activated()
171 L1deactivated(struct IsdnCardState *cs) in L1deactivated() argument
175 st = cs->stlist; in L1deactivated()
[all …]
Dnetjet.h58 u_char NETjet_ReadIC(struct IsdnCardState *cs, u_char offset);
59 void NETjet_WriteIC(struct IsdnCardState *cs, u_char offset, u_char value);
60 void NETjet_ReadICfifo(struct IsdnCardState *cs, u_char *data, int size);
61 void NETjet_WriteICfifo(struct IsdnCardState *cs, u_char *data, int size);
63 void read_tiger(struct IsdnCardState *cs);
64 void write_tiger(struct IsdnCardState *cs);
68 void inittiger(struct IsdnCardState *cs);
69 void release_io_netjet(struct IsdnCardState *cs);
Dcallc.c62 if (cards[i].cs) in hisax_findcard()
63 if (cards[i].cs->myid == driverid) in hisax_findcard()
64 return (cards[i].cs); in hisax_findcard()
77 VHiSax_putstatus(chanp->cs, tmp, fmt, args); in link_debug()
178 ic.driver = chanp->cs->myid; in HL_LL()
181 chanp->cs->iif.statcallb(&ic); in HL_LL()
193 ic.driver = chanp->cs->myid; in lli_deliver_cause()
196 if (chanp->cs->protocol == ISDN_PTYPE_EURO) in lli_deliver_cause()
202 chanp->cs->iif.statcallb(&ic); in lli_deliver_cause()
212 chanp->cs->cardmsg(chanp->cs, MDL_INFO_REL, (void *) (long)chanp->chan); in lli_close()
[all …]
Disdnl1.h25 void debugl1(struct IsdnCardState *cs, char *fmt, ...);
26 void DChannel_proc_xmt(struct IsdnCardState *cs);
27 void DChannel_proc_rcv(struct IsdnCardState *cs);
28 void l1_msg(struct IsdnCardState *cs, int pr, void *arg);
30 void Logl2Frame(struct IsdnCardState *cs, struct sk_buff *skb, char *buf,
Dtei.c152 struct IsdnCardState *cs; in tei_id_assign() local
170 cs = (struct IsdnCardState *) st->l1.hardware; in tei_id_assign()
171 cs->cardmsg(cs, MDL_ASSIGN | REQUEST, NULL); in tei_id_assign()
233 struct IsdnCardState *cs; in tei_id_remove() local
244 cs = (struct IsdnCardState *) st->l1.hardware; in tei_id_remove()
245 cs->cardmsg(cs, MDL_REMOVE | REQUEST, NULL); in tei_id_remove()
267 struct IsdnCardState *cs; in tei_id_req_tout() local
280 cs = (struct IsdnCardState *) st->l1.hardware; in tei_id_req_tout()
281 cs->cardmsg(cs, MDL_REMOVE | REQUEST, NULL); in tei_id_req_tout()
290 struct IsdnCardState *cs; in tei_id_ver_tout() local
[all …]
Dhscx.h37 extern int HscxVersion(struct IsdnCardState *cs, char *s);
39 extern void clear_pending_hscx_ints(struct IsdnCardState *cs);
40 extern void inithscx(struct IsdnCardState *cs);
41 extern void inithscxisac(struct IsdnCardState *cs, int part);
Dicc.h68 extern void ICCVersion(struct IsdnCardState *cs, char *s);
69 extern void initicc(struct IsdnCardState *cs);
70 extern void icc_interrupt(struct IsdnCardState *cs, u_char val);
71 extern void clear_pending_icc_ints(struct IsdnCardState *cs);
Darcofi.h25 extern int arcofi_fsm(struct IsdnCardState *cs, int event, void *data);
26 extern void init_arcofi(struct IsdnCardState *cs);
27 extern void clear_arcofi(struct IsdnCardState *cs);
Dhfc_2bds0.h125 extern void init2bds0(struct IsdnCardState *cs);
126 extern void release2bds0(struct IsdnCardState *cs);
127 extern void hfc2bds0_interrupt(struct IsdnCardState *cs, u_char val);
128 extern void set_cs_func(struct IsdnCardState *cs);
Dw6692.h21 #define READW6692BFIFO(cs, bchan, ptr, count) \ argument
22 insb(cs->hw.w6692.iobase + W_B_RFIFO + (bchan ? 0x40 : 0), ptr, count)
24 #define WRITEW6692BFIFO(cs, bchan, ptr, count) \ argument
25 outsb(cs->hw.w6692.iobase + W_B_XFIFO + (bchan ? 0x40 : 0), ptr, count)
Disar.h218 extern int ISARVersion(struct IsdnCardState *cs, char *s);
219 extern void isar_int_main(struct IsdnCardState *cs);
220 extern void initisar(struct IsdnCardState *cs);
222 extern int isar_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic);
Djade.h130 extern int JadeVersion(struct IsdnCardState *cs, char *s);
131 extern void clear_pending_jade_ints(struct IsdnCardState *cs);
132 extern void initjade(struct IsdnCardState *cs);
Dhisax.h501 struct IsdnCardState *cs; member
536 struct IsdnCardState *cs; member
1246 extern void Logl2Frame(struct IsdnCardState *cs, struct sk_buff *skb, char *buf, int dir);
1251 void init_bcstate(struct IsdnCardState *cs, int bc);
1253 void setstack_HiSax(struct PStack *st, struct IsdnCardState *cs);
1291 void HiSax_putstatus(struct IsdnCardState *cs, char *head, char *fmt, ...);
1293 void VHiSax_putstatus(struct IsdnCardState *cs, char *head, char *fmt, va_list args);
1296 void LogFrame(struct IsdnCardState *cs, u_char *p, int size);
1297 void dlogframe(struct IsdnCardState *cs, struct sk_buff *skb, int dir);
1314 int ll_run(struct IsdnCardState *cs, int addfeatures);
[all …]
Dhfc_2bs0.h59 extern void inithfc(struct IsdnCardState *cs);
60 extern void releasehfc(struct IsdnCardState *cs);
Dq931.c1166 LogFrame(struct IsdnCardState *cs, u_char *buf, int size) in LogFrame() argument
1172 dp = cs->dlog; in LogFrame()
1182 HiSax_putstatus(cs, NULL, cs->dlog); in LogFrame()
1184 HiSax_putstatus(cs, "LogFrame: ", "warning Frame too big (%d)", size); in LogFrame()
1188 dlogframe(struct IsdnCardState *cs, struct sk_buff *skb, int dir) in dlogframe() argument
1200 dp = cs->dlog; in dlogframe()
1249 HiSax_putstatus(cs, NULL, cs->dlog); in dlogframe()
1353 } else if ((buf[0] == 8) && (cs->protocol == ISDN_PTYPE_NI1)) { /* NI-1 */ in dlogframe()
1439 } else if ((buf[0] == 8) && (cs->protocol == ISDN_PTYPE_EURO)) { /* EURO */ in dlogframe()
1512 HiSax_putstatus(cs, NULL, cs->dlog); in dlogframe()
/linux-4.4.14/drivers/isdn/gigaset/
Dcommon.c89 static int setflags(struct cardstate *cs, unsigned flags, unsigned delay) in setflags() argument
93 r = cs->ops->set_modem_ctrl(cs, cs->control_state, flags); in setflags()
94 cs->control_state = flags; in setflags()
106 int gigaset_enterconfigmode(struct cardstate *cs) in gigaset_enterconfigmode() argument
110 cs->control_state = TIOCM_RTS; in gigaset_enterconfigmode()
112 r = setflags(cs, TIOCM_DTR, 200); in gigaset_enterconfigmode()
115 r = setflags(cs, 0, 200); in gigaset_enterconfigmode()
119 r = setflags(cs, TIOCM_RTS, 100); in gigaset_enterconfigmode()
122 r = setflags(cs, 0, 100); in gigaset_enterconfigmode()
126 r = setflags(cs, TIOCM_RTS | TIOCM_DTR, 800); in gigaset_enterconfigmode()
[all …]
Dinterface.c21 static int if_lock(struct cardstate *cs, int *arg) in if_lock() argument
25 gig_dbg(DEBUG_IF, "%u: if_lock (%d)", cs->minor_index, cmd); in if_lock()
31 *arg = cs->mstate == MS_LOCKED; in if_lock()
35 if (!cmd && cs->mstate == MS_LOCKED && cs->connected) { in if_lock()
36 cs->ops->set_modem_ctrl(cs, 0, TIOCM_DTR | TIOCM_RTS); in if_lock()
37 cs->ops->baud_rate(cs, B115200); in if_lock()
38 cs->ops->set_line_ctrl(cs, CS8); in if_lock()
39 cs->control_state = TIOCM_DTR | TIOCM_RTS; in if_lock()
42 cs->waiting = 1; in if_lock()
43 if (!gigaset_add_event(cs, &cs->at_state, EV_IF_LOCK, in if_lock()
[all …]
Dev-layer.c407 static void add_cid_event(struct cardstate *cs, int cid, int type, in add_cid_event() argument
416 spin_lock_irqsave(&cs->ev_lock, flags); in add_cid_event()
418 tail = cs->ev_tail; in add_cid_event()
420 if (unlikely(next == cs->ev_head)) { in add_cid_event()
421 dev_err(cs->dev, "event queue full\n"); in add_cid_event()
424 event = cs->events + tail; in add_cid_event()
431 cs->ev_tail = next; in add_cid_event()
434 spin_unlock_irqrestore(&cs->ev_lock, flags); in add_cid_event()
445 void gigaset_handle_modem_response(struct cardstate *cs) in gigaset_handle_modem_response() argument
453 if (!cs->cbytes) { in gigaset_handle_modem_response()
[all …]
Dser-gigaset.c63 static int write_modem(struct cardstate *cs) in write_modem() argument
65 struct tty_struct *tty = cs->hw.ser->tty; in write_modem()
66 struct bc_state *bcs = &cs->bcs[0]; /* only one channel */ in write_modem()
84 flush_send_queue(cs); in write_modem()
104 static int send_cb(struct cardstate *cs) in send_cb() argument
106 struct tty_struct *tty = cs->hw.ser->tty; in send_cb()
113 cb = cs->cmdbuf; in send_cb()
123 flush_send_queue(cs); in send_cb()
129 sent, cb->len, cs->cmdbytes); in send_cb()
133 spin_lock_irqsave(&cs->cmdlock, flags); in send_cb()
[all …]
Dusb-gigaset.c154 static int gigaset_set_modem_ctrl(struct cardstate *cs, unsigned old_state, in gigaset_set_modem_ctrl() argument
157 struct usb_device *udev = cs->hw.usb->udev; in gigaset_set_modem_ctrl()
178 static int set_value(struct cardstate *cs, u8 req, u16 val) in set_value() argument
180 struct usb_device *udev = cs->hw.usb->udev; in set_value()
200 0, 0, cs->hw.usb->bchars, 6, 2000 /*?*/); in set_value()
211 static int gigaset_baud_rate(struct cardstate *cs, unsigned cflag) in gigaset_baud_rate() argument
231 dev_err(cs->dev, "unsupported baudrate request 0x%x," in gigaset_baud_rate()
237 return set_value(cs, 1, val); in gigaset_baud_rate()
244 static int gigaset_set_line_ctrl(struct cardstate *cs, unsigned cflag) in gigaset_set_line_ctrl() argument
263 dev_err(cs->dev, "CSIZE was not CS5-CS8, using default of 8\n"); in gigaset_set_line_ctrl()
[all …]
Di4l.c46 struct cardstate *cs = gigaset_get_cs_by_id(driverID); in writebuf_from_LL() local
51 if (!cs) { in writebuf_from_LL()
55 if (channel < 0 || channel >= cs->channels) { in writebuf_from_LL()
56 dev_err(cs->dev, "%s: invalid channel ID (%d)\n", in writebuf_from_LL()
60 bcs = &cs->bcs[channel]; in writebuf_from_LL()
64 dev_err(cs->dev, "%s: skb_linearize failed\n", __func__); in writebuf_from_LL()
75 dev_notice(cs->dev, "%s: not ACKing empty packet\n", in writebuf_from_LL()
80 dev_err(cs->dev, "%s: packet too large (%d bytes)\n", in writebuf_from_LL()
88 dev_err(cs->dev, "%s: insufficient skb headroom\n", __func__); in writebuf_from_LL()
104 return cs->ops->send_skb(bcs, skb); in writebuf_from_LL()
[all …]
Dproc.c21 struct cardstate *cs = dev_get_drvdata(dev); in show_cidmode() local
23 return sprintf(buf, "%u\n", cs->cidmode); in show_cidmode()
29 struct cardstate *cs = dev_get_drvdata(dev); in set_cidmode() local
40 if (mutex_lock_interruptible(&cs->mutex)) in set_cidmode()
43 cs->waiting = 1; in set_cidmode()
44 if (!gigaset_add_event(cs, &cs->at_state, EV_PROC_CIDMODE, in set_cidmode()
46 cs->waiting = 0; in set_cidmode()
47 mutex_unlock(&cs->mutex); in set_cidmode()
50 gigaset_schedule_event(cs); in set_cidmode()
52 wait_event(cs->waitqueue, !cs->waiting); in set_cidmode()
[all …]
Dbas-gigaset.c306 static int gigaset_set_modem_ctrl(struct cardstate *cs, unsigned old_state, in gigaset_set_modem_ctrl() argument
312 static int gigaset_baud_rate(struct cardstate *cs, unsigned cflag) in gigaset_baud_rate() argument
317 static int gigaset_set_line_ctrl(struct cardstate *cs, unsigned cflag) in gigaset_set_line_ctrl() argument
347 struct cardstate *cs = bcs->cs; in error_hangup() local
349 gigaset_add_event(cs, &bcs->at_state, EV_HUP, NULL, 0, NULL); in error_hangup()
350 gigaset_schedule_event(cs); in error_hangup()
361 static inline void error_reset(struct cardstate *cs) in error_reset() argument
364 update_basstate(cs->hw.bas, BS_RESETTING, 0); in error_reset()
365 if (req_submit(cs->bcs, HD_RESET_INTERRUPT_PIPE, 0, BAS_TIMEOUT)) in error_reset()
367 usb_queue_reset_device(cs->hw.bas->interface); in error_reset()
[all …]
Dcapi.c151 static inline void ignore_cstruct_param(struct cardstate *cs, _cstruct param, in ignore_cstruct_param() argument
155 dev_warn(cs->dev, "%s: ignoring unsupported parameter: %s\n", in ignore_cstruct_param()
326 static void send_data_b3_conf(struct cardstate *cs, struct capi_ctr *ctr, in send_data_b3_conf() argument
335 dev_err(cs->dev, "%s: out of memory\n", __func__); in send_data_b3_conf()
372 struct cardstate *cs = bcs->cs; in gigaset_skb_sent() local
373 struct gigaset_capi_ctr *iif = cs->iif; in gigaset_skb_sent()
398 send_data_b3_conf(cs, &iif->ctr, ap->id, CAPIMSG_MSGID(req), in gigaset_skb_sent()
417 struct cardstate *cs = bcs->cs; in gigaset_skb_rcvd() local
418 struct gigaset_capi_ctr *iif = cs->iif; in gigaset_skb_rcvd()
497 struct cardstate *cs = at_state->cs; in gigaset_isdn_icall() local
[all …]
Dasyncdata.c52 struct cardstate *cs = inbuf->cs; in cmd_loop() local
53 unsigned cbytes = cs->cbytes; in cmd_loop()
63 if (cbytes == 0 && cs->respdata[0] == '\r') { in cmd_loop()
65 cs->respdata[0] = 0; in cmd_loop()
72 dev_warn(cs->dev, "response too large (%d)\n", in cmd_loop()
76 cs->cbytes = cbytes; in cmd_loop()
78 cbytes, cs->respdata); in cmd_loop()
79 gigaset_handle_modem_response(cs); in cmd_loop()
83 cs->respdata[0] = c; in cmd_loop()
86 if (cs->dle && !(inbuf->inputstate & INS_DLE_command)) in cmd_loop()
[all …]
Dgigaset.h281 struct cardstate *cs; member
348 struct cardstate *cs; member
380 struct cardstate *cs; member
514 struct cardstate *cs; member
570 int (*write_cmd)(struct cardstate *cs, struct cmdbuf_t *cb);
573 int (*write_room)(struct cardstate *cs);
574 int (*chars_in_buffer)(struct cardstate *cs);
575 int (*brkchars)(struct cardstate *cs, const unsigned char buf[6]);
595 int (*initcshw)(struct cardstate *cs);
598 void (*freecshw)(struct cardstate *cs);
[all …]
Disocdata.c508 dev_warn(bcs->cs->dev, "received oversized packet discarded\n"); in hdlc_putbyte()
537 struct cardstate *cs = bcs->cs; in hdlc_done() local
552 dev_notice(cs->dev, "received short frame (%d octets)\n", in hdlc_done()
558 dev_notice(cs->dev, "frame check error\n"); in hdlc_done()
586 dev_notice(bcs->cs->dev, "received partial byte (%d bits)\n", inbits); in hdlc_frag()
896 struct cardstate *cs = inbuf->cs; in cmd_loop() local
897 unsigned cbytes = cs->cbytes; in cmd_loop()
904 if (cbytes == 0 && cs->respdata[0] == '\r') { in cmd_loop()
906 cs->respdata[0] = 0; in cmd_loop()
913 dev_warn(cs->dev, "response too large (%d)\n", in cmd_loop()
[all …]
Ddummyll.c53 void gigaset_isdn_start(struct cardstate *cs) in gigaset_isdn_start() argument
57 void gigaset_isdn_stop(struct cardstate *cs) in gigaset_isdn_stop() argument
61 int gigaset_isdn_regdev(struct cardstate *cs, const char *isdnid) in gigaset_isdn_regdev() argument
66 void gigaset_isdn_unregdev(struct cardstate *cs) in gigaset_isdn_unregdev() argument
/linux-4.4.14/kernel/time/
Dclocksource.c122 static void __clocksource_change_rating(struct clocksource *cs, int rating);
139 static void __clocksource_unstable(struct clocksource *cs) in __clocksource_unstable() argument
141 cs->flags &= ~(CLOCK_SOURCE_VALID_FOR_HRES | CLOCK_SOURCE_WATCHDOG); in __clocksource_unstable()
142 cs->flags |= CLOCK_SOURCE_UNSTABLE; in __clocksource_unstable()
156 void clocksource_mark_unstable(struct clocksource *cs) in clocksource_mark_unstable() argument
161 if (!(cs->flags & CLOCK_SOURCE_UNSTABLE)) { in clocksource_mark_unstable()
162 if (list_empty(&cs->wd_list)) in clocksource_mark_unstable()
163 list_add(&cs->wd_list, &watchdog_list); in clocksource_mark_unstable()
164 __clocksource_unstable(cs); in clocksource_mark_unstable()
171 struct clocksource *cs; in clocksource_watchdog() local
[all …]
/linux-4.4.14/drivers/isdn/divert/
Disdn_divert.c61 struct call_struc *cs = (struct call_struc *) arg; in deflect_timer_expire() local
64 del_timer(&cs->timer); /* delete active timer */ in deflect_timer_expire()
67 switch (cs->akt_state) { in deflect_timer_expire()
69 cs->ics.command = ISDN_CMD_HANGUP; /* cancel action */ in deflect_timer_expire()
70 divert_if.ll_cmd(&cs->ics); in deflect_timer_expire()
72 cs->akt_state = DEFLECT_AUTODEL; /* delete after timeout */ in deflect_timer_expire()
73 cs->timer.expires = jiffies + (HZ * AUTODEL_TIME); in deflect_timer_expire()
74 add_timer(&cs->timer); in deflect_timer_expire()
79 cs->ics.command = ISDN_CMD_REDIR; /* protocol */ in deflect_timer_expire()
80 strlcpy(cs->ics.parm.setup.phone, cs->deflect_dest, sizeof(cs->ics.parm.setup.phone)); in deflect_timer_expire()
[all …]
/linux-4.4.14/kernel/
Dcpuset.c145 static inline struct cpuset *parent_cs(struct cpuset *cs) in parent_cs() argument
147 return css_cs(cs->css.parent); in parent_cs()
176 static inline bool is_cpuset_online(const struct cpuset *cs) in is_cpuset_online() argument
178 return test_bit(CS_ONLINE, &cs->flags); in is_cpuset_online()
181 static inline int is_cpu_exclusive(const struct cpuset *cs) in is_cpu_exclusive() argument
183 return test_bit(CS_CPU_EXCLUSIVE, &cs->flags); in is_cpu_exclusive()
186 static inline int is_mem_exclusive(const struct cpuset *cs) in is_mem_exclusive() argument
188 return test_bit(CS_MEM_EXCLUSIVE, &cs->flags); in is_mem_exclusive()
191 static inline int is_mem_hardwall(const struct cpuset *cs) in is_mem_hardwall() argument
193 return test_bit(CS_MEM_HARDWALL, &cs->flags); in is_mem_hardwall()
[all …]
/linux-4.4.14/arch/arm/mach-omap2/
Dboard-flash.c57 __init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) in board_nor_init() argument
66 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1, in board_nor_init()
71 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1, in board_nor_init()
92 u8 nr_parts, u8 cs) in board_onenand_init() argument
94 board_onenand_data.cs = cs; in board_onenand_init()
136 __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, in board_nand_init() argument
139 board_nand_data.cs = cs; in board_nand_init()
155 u8 cs = 0; in get_gpmc0_type() local
168 cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf; in get_gpmc0_type()
173 cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) | in get_gpmc0_type()
[all …]
Dgpmc-nand.c86 BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM); in gpmc_nand_init()
88 err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, in gpmc_nand_init()
92 gpmc_nand_data->cs, err); in gpmc_nand_init()
108 err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t, &s); in gpmc_nand_init()
116 err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); in gpmc_nand_init()
124 gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); in gpmc_nand_init()
133 pdev = platform_device_alloc("omap2-nand", gpmc_nand_data->cs); in gpmc_nand_init()
156 gpmc_cs_free(gpmc_nand_data->cs); in gpmc_nand_init()
Dboard-flash.h42 u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t);
46 u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t) in board_nand_init() argument
55 u8 nr_parts, u8 cs);
58 u8 nr_parts, u8 cs) in board_onenand_init() argument
Dgpmc-onenand.c294 ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async); in omap2_onenand_setup_async()
298 ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async); in omap2_onenand_setup_async()
334 ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync); in omap2_onenand_setup_sync()
338 ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync); in omap2_onenand_setup_sync()
391 err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, in gpmc_onenand_init()
395 gpmc_onenand_data->cs, err); in gpmc_onenand_init()
404 gpmc_cs_free(gpmc_onenand_data->cs); in gpmc_onenand_init()
/linux-4.4.14/arch/mips/include/asm/netlogic/xlr/
Dflash.h37 #define FLASH_CSBASE_ADDR(cs) (cs) argument
38 #define FLASH_CSADDR_MASK(cs) (0x10 + (cs)) argument
39 #define FLASH_CSDEV_PARM(cs) (0x20 + (cs)) argument
40 #define FLASH_CSTIME_PARMA(cs) (0x30 + (cs)) argument
41 #define FLASH_CSTIME_PARMB(cs) (0x40 + (cs)) argument
48 #define FLASH_NAND_CLE(cs) (0x90 + (cs)) argument
49 #define FLASH_NAND_ALE(cs) (0xa0 + (cs)) argument
/linux-4.4.14/arch/mips/bcm63xx/
Dcs.c23 static int is_valid_cs(unsigned int cs) in is_valid_cs() argument
25 if (cs > 6) in is_valid_cs()
34 int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size) in bcm63xx_set_cs_base() argument
39 if (!is_valid_cs(cs)) in bcm63xx_set_cs_base()
54 bcm_mpi_writel(val, MPI_CSBASE_REG(cs)); in bcm63xx_set_cs_base()
65 int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait, in bcm63xx_set_cs_timing() argument
71 if (!is_valid_cs(cs)) in bcm63xx_set_cs_timing()
75 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); in bcm63xx_set_cs_timing()
82 bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); in bcm63xx_set_cs_timing()
93 int bcm63xx_set_cs_param(unsigned int cs, u32 params) in bcm63xx_set_cs_param() argument
[all …]
Ddev-pcmcia.c69 static int __init config_pcmcia_cs(unsigned int cs, in config_pcmcia_cs() argument
74 ret = bcm63xx_set_cs_status(cs, 0); in config_pcmcia_cs()
76 ret = bcm63xx_set_cs_base(cs, base, size); in config_pcmcia_cs()
78 ret = bcm63xx_set_cs_status(cs, 1); in config_pcmcia_cs()
83 unsigned int cs; member
88 .cs = MPI_CS_PCMCIA_COMMON,
93 .cs = MPI_CS_PCMCIA_ATTR,
98 .cs = MPI_CS_PCMCIA_IO,
132 ret = config_pcmcia_cs(pcmcia_cs[i].cs, in bcm63xx_pcmcia_register()
/linux-4.4.14/tools/perf/util/
Dcomm.c16 static struct comm_str *comm_str__get(struct comm_str *cs) in comm_str__get() argument
18 if (cs) in comm_str__get()
19 atomic_inc(&cs->refcnt); in comm_str__get()
20 return cs; in comm_str__get()
23 static void comm_str__put(struct comm_str *cs) in comm_str__put() argument
25 if (cs && atomic_dec_and_test(&cs->refcnt)) { in comm_str__put()
26 rb_erase(&cs->rb_node, &comm_str_root); in comm_str__put()
27 zfree(&cs->str); in comm_str__put()
28 free(cs); in comm_str__put()
34 struct comm_str *cs; in comm_str__alloc() local
[all …]
Ddata-convert-bt.c432 static int ctf_stream__flush(struct ctf_stream *cs) in ctf_stream__flush() argument
436 if (cs) { in ctf_stream__flush()
437 err = bt_ctf_stream_flush(cs->stream); in ctf_stream__flush()
439 pr_err("CTF stream %d flush failed\n", cs->cpu); in ctf_stream__flush()
442 cs->cpu, cs->count); in ctf_stream__flush()
444 cs->count = 0; in ctf_stream__flush()
452 struct ctf_stream *cs; in ctf_stream__create() local
458 cs = zalloc(sizeof(*cs)); in ctf_stream__create()
459 if (!cs) { in ctf_stream__create()
491 cs->cpu = cpu; in ctf_stream__create()
[all …]
/linux-4.4.14/drivers/net/slip/
Dslhc.c232 register struct cstate *cs = lcs->next; in slhc_compress() local
291 if( ip->saddr == cs->cs_ip.saddr in slhc_compress()
292 && ip->daddr == cs->cs_ip.daddr in slhc_compress()
293 && th->source == cs->cs_tcp.source in slhc_compress()
294 && th->dest == cs->cs_tcp.dest) in slhc_compress()
298 if ( cs == ocs ) in slhc_compress()
300 lcs = cs; in slhc_compress()
301 cs = cs->next; in slhc_compress()
323 } else if (cs == ocs) { in slhc_compress()
328 lcs->next = cs->next; in slhc_compress()
[all …]
/linux-4.4.14/drivers/s390/char/
Draw3270.h223 struct string *cs, *tmp; in alloc_string() local
227 list_for_each_entry(cs, free_list, list) { in alloc_string()
228 if (cs->size < size) in alloc_string()
230 if (cs->size > size + sizeof(struct string)) { in alloc_string()
231 char *endaddr = (char *) (cs + 1) + cs->size; in alloc_string()
234 cs->size -= size + sizeof(struct string); in alloc_string()
235 cs = tmp; in alloc_string()
237 list_del(&cs->list); in alloc_string()
238 cs->len = len; in alloc_string()
239 INIT_LIST_HEAD(&cs->list); in alloc_string()
[all …]
/linux-4.4.14/drivers/clocksource/
Dtime-pistachio.c51 struct clocksource cs; member
56 #define to_pistachio_clocksource(cs) \ argument
57 container_of(cs, struct pistachio_clocksource, cs)
71 pistachio_clocksource_read_cycles(struct clocksource *cs) in pistachio_clocksource_read_cycles() argument
73 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clocksource_read_cycles()
92 return pistachio_clocksource_read_cycles(&pcs_gpt.cs); in pistachio_read_sched_clock()
95 static void pistachio_clksrc_set_mode(struct clocksource *cs, int timeridx, in pistachio_clksrc_set_mode() argument
98 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_set_mode()
110 static void pistachio_clksrc_enable(struct clocksource *cs, int timeridx) in pistachio_clksrc_enable() argument
112 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_enable()
[all …]
Dem_sti.c45 struct clocksource cs; member
196 static struct em_sti_priv *cs_to_em_sti(struct clocksource *cs) in cs_to_em_sti() argument
198 return container_of(cs, struct em_sti_priv, cs); in cs_to_em_sti()
201 static cycle_t em_sti_clocksource_read(struct clocksource *cs) in em_sti_clocksource_read() argument
203 return em_sti_count(cs_to_em_sti(cs)); in em_sti_clocksource_read()
206 static int em_sti_clocksource_enable(struct clocksource *cs) in em_sti_clocksource_enable() argument
209 struct em_sti_priv *p = cs_to_em_sti(cs); in em_sti_clocksource_enable()
213 __clocksource_update_freq_hz(cs, p->rate); in em_sti_clocksource_enable()
217 static void em_sti_clocksource_disable(struct clocksource *cs) in em_sti_clocksource_disable() argument
219 em_sti_stop(cs_to_em_sti(cs), USER_CLOCKSOURCE); in em_sti_clocksource_disable()
[all …]
Dh8300_tpu.c36 struct clocksource cs; member
74 static inline struct tpu_priv *cs_to_priv(struct clocksource *cs) in cs_to_priv() argument
76 return container_of(cs, struct tpu_priv, cs); in cs_to_priv()
79 static cycle_t tpu_clocksource_read(struct clocksource *cs) in tpu_clocksource_read() argument
81 struct tpu_priv *p = cs_to_priv(cs); in tpu_clocksource_read()
93 static int tpu_clocksource_enable(struct clocksource *cs) in tpu_clocksource_enable() argument
95 struct tpu_priv *p = cs_to_priv(cs); in tpu_clocksource_enable()
108 static void tpu_clocksource_disable(struct clocksource *cs) in tpu_clocksource_disable() argument
110 struct tpu_priv *p = cs_to_priv(cs); in tpu_clocksource_disable()
144 p->cs.name = pdev->name; in tpu_setup()
[all …]
Dmmio.c56 struct clocksource_mmio *cs; in clocksource_mmio_init() local
61 cs = kzalloc(sizeof(struct clocksource_mmio), GFP_KERNEL); in clocksource_mmio_init()
62 if (!cs) in clocksource_mmio_init()
65 cs->reg = base; in clocksource_mmio_init()
66 cs->clksrc.name = name; in clocksource_mmio_init()
67 cs->clksrc.rating = rating; in clocksource_mmio_init()
68 cs->clksrc.read = read; in clocksource_mmio_init()
69 cs->clksrc.mask = CLOCKSOURCE_MASK(bits); in clocksource_mmio_init()
70 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in clocksource_mmio_init()
72 return clocksource_register_hz(&cs->clksrc, hz); in clocksource_mmio_init()
Dtimer-ti-32k.c60 struct clocksource cs; member
63 static inline struct ti_32k *to_ti_32k(struct clocksource *cs) in to_ti_32k() argument
65 return container_of(cs, struct ti_32k, cs); in to_ti_32k()
68 static cycle_t ti_32k_read_cycles(struct clocksource *cs) in ti_32k_read_cycles() argument
70 struct ti_32k *ti = to_ti_32k(cs); in ti_32k_read_cycles()
76 .cs = {
88 return ti_32k_read_cycles(&ti_32k_timer.cs); in omap_32k_read_sched_clock()
116 ret = clocksource_register_hz(&ti_32k_timer.cs, 32768); in ti_32k_timer_init()
Dh8300_timer16.c51 struct clocksource cs; member
100 static inline struct timer16_priv *cs_to_priv(struct clocksource *cs) in cs_to_priv() argument
102 return container_of(cs, struct timer16_priv, cs); in cs_to_priv()
105 static cycle_t timer16_clocksource_read(struct clocksource *cs) in timer16_clocksource_read() argument
107 struct timer16_priv *p = cs_to_priv(cs); in timer16_clocksource_read()
119 static int timer16_enable(struct clocksource *cs) in timer16_enable() argument
121 struct timer16_priv *p = cs_to_priv(cs); in timer16_enable()
135 static void timer16_disable(struct clocksource *cs) in timer16_disable() argument
137 struct timer16_priv *p = cs_to_priv(cs); in timer16_disable()
185 p->cs.name = pdev->name; in timer16_setup()
[all …]
Dtimer-sun5i.c157 struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc); in sun5i_clksrc_read() local
159 return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clksrc_read()
167 struct sun5i_timer_clksrc *cs = container_of(timer, struct sun5i_timer_clksrc, timer); in sun5i_rate_cb_clksrc() local
171 clocksource_unregister(&cs->clksrc); in sun5i_rate_cb_clksrc()
175 clocksource_register_hz(&cs->clksrc, ndata->new_rate); in sun5i_rate_cb_clksrc()
189 struct sun5i_timer_clksrc *cs; in sun5i_setup_clocksource() local
193 cs = kzalloc(sizeof(*cs), GFP_KERNEL); in sun5i_setup_clocksource()
194 if (!cs) in sun5i_setup_clocksource()
205 cs->timer.base = base; in sun5i_setup_clocksource()
206 cs->timer.clk = clk; in sun5i_setup_clocksource()
[all …]
Dsh_tmu.c52 struct clocksource cs; member
253 static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs) in cs_to_sh_tmu() argument
255 return container_of(cs, struct sh_tmu_channel, cs); in cs_to_sh_tmu()
258 static cycle_t sh_tmu_clocksource_read(struct clocksource *cs) in sh_tmu_clocksource_read() argument
260 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_read()
265 static int sh_tmu_clocksource_enable(struct clocksource *cs) in sh_tmu_clocksource_enable() argument
267 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_enable()
275 __clocksource_update_freq_hz(cs, ch->rate); in sh_tmu_clocksource_enable()
282 static void sh_tmu_clocksource_disable(struct clocksource *cs) in sh_tmu_clocksource_disable() argument
284 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_disable()
[all …]
Ddw_apb_timer.c47 clocksource_to_dw_apb_clocksource(struct clocksource *cs) in clocksource_to_dw_apb_clocksource() argument
49 return container_of(cs, struct dw_apb_clocksource, cs); in clocksource_to_dw_apb_clocksource()
339 static cycle_t __apbt_read_clocksource(struct clocksource *cs) in __apbt_read_clocksource() argument
343 clocksource_to_dw_apb_clocksource(cs); in __apbt_read_clocksource()
350 static void apbt_restart_clocksource(struct clocksource *cs) in apbt_restart_clocksource() argument
353 clocksource_to_dw_apb_clocksource(cs); in apbt_restart_clocksource()
381 dw_cs->cs.name = name; in dw_apb_clocksource_init()
382 dw_cs->cs.rating = rating; in dw_apb_clocksource_init()
383 dw_cs->cs.read = __apbt_read_clocksource; in dw_apb_clocksource_init()
384 dw_cs->cs.mask = CLOCKSOURCE_MASK(32); in dw_apb_clocksource_init()
[all …]
Dsh_cmt.c109 struct clocksource cs; member
610 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) in cs_to_sh_cmt() argument
612 return container_of(cs, struct sh_cmt_channel, cs); in cs_to_sh_cmt()
615 static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) in sh_cmt_clocksource_read() argument
617 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_read()
633 static int sh_cmt_clocksource_enable(struct clocksource *cs) in sh_cmt_clocksource_enable() argument
636 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_enable()
644 __clocksource_update_freq_hz(cs, ch->rate); in sh_cmt_clocksource_enable()
650 static void sh_cmt_clocksource_disable(struct clocksource *cs) in sh_cmt_clocksource_disable() argument
652 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_disable()
[all …]
Ddw_apb_timer_of.c88 struct dw_apb_clocksource *cs; in add_clocksource() local
93 cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate); in add_clocksource()
94 if (!cs) in add_clocksource()
97 dw_apb_clocksource_start(cs); in add_clocksource()
98 dw_apb_clocksource_register(cs); in add_clocksource()
Dcadence_ttc_timer.c92 struct clocksource cs; member
96 container_of(x, struct ttc_timer_clocksource, cs)
161 static cycle_t __ttc_clocksource_read(struct clocksource *cs) in __ttc_clocksource_read() argument
163 struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc; in __ttc_clocksource_read()
353 ttccs->cs.name = "ttc_clocksource"; in ttc_setup_clocksource()
354 ttccs->cs.rating = 200; in ttc_setup_clocksource()
355 ttccs->cs.read = __ttc_clocksource_read; in ttc_setup_clocksource()
356 ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width); in ttc_setup_clocksource()
357 ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; in ttc_setup_clocksource()
370 err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE); in ttc_setup_clocksource()
/linux-4.4.14/fs/fuse/
Ddev.c710 static void fuse_copy_init(struct fuse_copy_state *cs, int write, in fuse_copy_init() argument
713 memset(cs, 0, sizeof(*cs)); in fuse_copy_init()
714 cs->write = write; in fuse_copy_init()
715 cs->iter = iter; in fuse_copy_init()
719 static void fuse_copy_finish(struct fuse_copy_state *cs) in fuse_copy_finish() argument
721 if (cs->currbuf) { in fuse_copy_finish()
722 struct pipe_buffer *buf = cs->currbuf; in fuse_copy_finish()
724 if (cs->write) in fuse_copy_finish()
725 buf->len = PAGE_SIZE - cs->len; in fuse_copy_finish()
726 cs->currbuf = NULL; in fuse_copy_finish()
[all …]
/linux-4.4.14/include/linux/
Dclocksource.h71 cycle_t (*read)(struct clocksource *cs);
84 int (*enable)(struct clocksource *cs);
85 void (*disable)(struct clocksource *cs);
87 void (*suspend)(struct clocksource *cs);
88 void (*resume)(struct clocksource *cs);
184 extern void clocksource_change_rating(struct clocksource *cs, int rating);
188 extern void clocksource_mark_unstable(struct clocksource *cs);
200 __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq);
202 __clocksource_update_freq_scale(struct clocksource *cs, u32 scale, u32 freq);
208 static inline int __clocksource_register(struct clocksource *cs) in __clocksource_register() argument
[all …]
Domap-gpmc.h159 extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
164 extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
166 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
168 extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
169 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
170 extern void gpmc_cs_free(int cs);
/linux-4.4.14/arch/mips/netlogic/xlr/
Dplatform-flash.c89 int cs; member
100 FLASH_NAND_CLE(nand_priv.cs), cmd); in xlr_nand_ctrl()
103 FLASH_NAND_ALE(nand_priv.cs), cmd); in xlr_nand_ctrl()
144 uint64_t flash_map_base, int cs, struct resource *res) in setup_flash_resource() argument
148 base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs)); in setup_flash_resource()
149 mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs)); in setup_flash_resource()
159 int cs, boot_nand, boot_nor; in xlr_flash_init() local
188 cs = 0; in xlr_flash_init()
191 nand_priv.cs = cs; in xlr_flash_init()
193 setup_flash_resource(flash_mmio, flash_map_base, cs, in xlr_flash_init()
[all …]
/linux-4.4.14/drivers/memory/
Domap-gpmc.c264 void gpmc_cs_write_reg(int cs, int idx, u32 val) in gpmc_cs_write_reg() argument
268 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_write_reg()
272 static u32 gpmc_cs_read_reg(int cs, int idx) in gpmc_cs_read_reg() argument
276 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_read_reg()
299 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) in gpmc_get_clk_period() argument
309 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); in gpmc_get_clk_period()
324 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, in gpmc_ns_to_clk_ticks() argument
330 tick_ps = gpmc_get_clk_period(cs, cd); in gpmc_ns_to_clk_ticks()
350 unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs, in gpmc_clk_ticks_to_ns() argument
353 return ticks * gpmc_get_clk_period(cs, cd) / 1000; in gpmc_clk_ticks_to_ns()
[all …]
Dpl172.c86 struct device_node *np, u32 cs) in pl172_setup_static() argument
101 dev_err(&adev->dev, "invalid memory width cs%u\n", cs); in pl172_setup_static()
128 writel(cfg, pl172->base + MPMC_STATIC_CFG(cs)); in pl172_setup_static()
129 dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg); in pl172_setup_static()
133 MPMC_STATIC_WAIT_WEN(cs), in pl172_setup_static()
139 MPMC_STATIC_WAIT_OEN(cs), in pl172_setup_static()
145 MPMC_STATIC_WAIT_RD(cs), in pl172_setup_static()
151 MPMC_STATIC_WAIT_PAGE(cs), in pl172_setup_static()
157 MPMC_STATIC_WAIT_WR(cs), in pl172_setup_static()
163 MPMC_STATIC_WAIT_TURN(cs), in pl172_setup_static()
[all …]
Dti-aemif.c100 u8 cs; member
185 offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; in aemif_config_abus()
240 offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; in aemif_get_hw_params()
268 u32 cs; in of_aemif_parse_abus_config() local
271 if (of_property_read_u32(np, "ti,cs-chipselect", &cs)) { in of_aemif_parse_abus_config()
276 if (cs - aemif->cs_offset >= NUM_CS || cs < aemif->cs_offset) { in of_aemif_parse_abus_config()
277 dev_dbg(&pdev->dev, "cs number is incorrect %d", cs); in of_aemif_parse_abus_config()
287 data->cs = cs; in of_aemif_parse_abus_config()
382 aemif->cs_data[i].cs); in aemif_probe()
/linux-4.4.14/drivers/spi/
Dspi-fsl-spi.c89 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_spi_change_mode() local
94 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) in fsl_spi_change_mode()
101 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); in fsl_spi_change_mode()
107 mpc8xxx_spi_write_reg(mode, cs->hw_mode); in fsl_spi_change_mode()
116 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_spi_chipselect() local
126 mpc8xxx_spi->rx_shift = cs->rx_shift; in fsl_spi_chipselect()
127 mpc8xxx_spi->tx_shift = cs->tx_shift; in fsl_spi_chipselect()
128 mpc8xxx_spi->get_rx = cs->get_rx; in fsl_spi_chipselect()
129 mpc8xxx_spi->get_tx = cs->get_tx; in fsl_spi_chipselect()
172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, in mspi_apply_cpu_mode_quirks() argument
[all …]
Dspi-omap2-mcspi.c128 struct list_head cs; member
172 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
174 writel_relaxed(val, cs->base + idx); in mcspi_write_cs_reg()
179 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_read_cs_reg() local
181 return readl_relaxed(cs->base + idx); in mcspi_read_cs_reg()
186 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_cached_chconf0() local
188 return cs->chconf0; in mcspi_cached_chconf0()
193 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_chconf0() local
195 cs->chconf0 = val; in mcspi_write_chconf0()
232 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_enable() local
[all …]
Dspi-xlp.c106 int cs; /* slave device chip select */ member
113 int cs, int regoff) in xlp_spi_reg_read() argument
115 return readl(priv->base + regoff + cs * SPI_CS_OFFSET); in xlp_spi_reg_read()
118 static inline void xlp_spi_reg_write(struct xlp_spi_priv *priv, int cs, in xlp_spi_reg_write() argument
121 writel(val, priv->base + regoff + cs * SPI_CS_OFFSET); in xlp_spi_reg_write()
135 int cs; in xlp_spi_sysctl_setup() local
137 for (cs = 0; cs < XLP_SPI_MAX_CS; cs++) in xlp_spi_sysctl_setup()
139 XLP_SPI_SYS_RESET << cs); in xlp_spi_sysctl_setup()
147 int cs; in xlp_spi_setup() local
150 cs = spi->chip_select; in xlp_spi_setup()
[all …]
Dspi-bitbang.c141 struct spi_bitbang_cs *cs = spi->controller_state; in spi_bitbang_setup_transfer() local
157 cs->txrx_bufs = bitbang_txrx_8; in spi_bitbang_setup_transfer()
159 cs->txrx_bufs = bitbang_txrx_16; in spi_bitbang_setup_transfer()
161 cs->txrx_bufs = bitbang_txrx_32; in spi_bitbang_setup_transfer()
169 cs->nsecs = (1000000000/2) / hz; in spi_bitbang_setup_transfer()
170 if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000)) in spi_bitbang_setup_transfer()
183 struct spi_bitbang_cs *cs = spi->controller_state; in spi_bitbang_setup() local
188 if (!cs) { in spi_bitbang_setup()
189 cs = kzalloc(sizeof(*cs), GFP_KERNEL); in spi_bitbang_setup()
190 if (!cs) in spi_bitbang_setup()
[all …]
Dspi-bcm2835.c132 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); in bcm2835_spi_reset_hw() local
135 cs &= ~(BCM2835_SPI_CS_INTR | in bcm2835_spi_reset_hw()
140 cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; in bcm2835_spi_reset_hw()
143 bcm2835_wr(bs, BCM2835_SPI_CS, cs); in bcm2835_spi_reset_hw()
172 u32 cs) in bcm2835_spi_transfer_one_irq() argument
187 cs | BCM2835_SPI_CS_TA); in bcm2835_spi_transfer_one_irq()
198 cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA; in bcm2835_spi_transfer_one_irq()
199 bcm2835_wr(bs, BCM2835_SPI_CS, cs); in bcm2835_spi_transfer_one_irq()
306 u32 cs) in bcm2835_spi_transfer_one_dma() argument
316 return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); in bcm2835_spi_transfer_one_dma()
[all …]
Dspi-fsl-espi.c94 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_espi_change_mode() local
107 mpc8xxx_spi_write_reg(mode, cs->hw_mode); in fsl_espi_change_mode()
141 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_espi_setup_transfer() local
155 cs->rx_shift = 0; in fsl_espi_setup_transfer()
156 cs->tx_shift = 0; in fsl_espi_setup_transfer()
157 cs->get_rx = mpc8xxx_spi_rx_buf_u32; in fsl_espi_setup_transfer()
158 cs->get_tx = mpc8xxx_spi_tx_buf_u32; in fsl_espi_setup_transfer()
160 cs->rx_shift = 8 - bits_per_word; in fsl_espi_setup_transfer()
162 cs->rx_shift = 16 - bits_per_word; in fsl_espi_setup_transfer()
164 cs->get_tx = fsl_espi_tx_buf_lsb; in fsl_espi_setup_transfer()
[all …]
Dspi-s3c24xx.c71 int cs, int pol);
92 static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol) in s3c24xx_spi_gpiocs() argument
99 struct s3c24xx_spi_devstate *cs = spi->controller_state; in s3c24xx_spi_chipsel() local
108 writeb(cs->spcon, hw->regs + S3C2410_SPCON); in s3c24xx_spi_chipsel()
112 writeb(cs->spcon | S3C2410_SPCON_ENSCK, in s3c24xx_spi_chipsel()
123 struct s3c24xx_spi_devstate *cs = spi->controller_state; in s3c24xx_spi_update_state() local
133 if (spi->mode != cs->mode) { in s3c24xx_spi_update_state()
142 cs->mode = spi->mode; in s3c24xx_spi_update_state()
143 cs->spcon = spcon; in s3c24xx_spi_update_state()
146 if (cs->hz != hz) { in s3c24xx_spi_update_state()
[all …]
Dspi-ppc4xx.c172 struct spi_ppc4xx_cs *cs = spi->controller_state; in spi_ppc4xx_setupxfer() local
200 out_8(&hw->regs->mode, cs->mode); in spi_ppc4xx_setupxfer()
225 struct spi_ppc4xx_cs *cs = spi->controller_state; in spi_ppc4xx_setup() local
232 if (cs == NULL) { in spi_ppc4xx_setup()
233 cs = kzalloc(sizeof *cs, GFP_KERNEL); in spi_ppc4xx_setup()
234 if (!cs) in spi_ppc4xx_setup()
236 spi->controller_state = cs; in spi_ppc4xx_setup()
243 cs->mode = SPI_PPC4XX_MODE_SPE; in spi_ppc4xx_setup()
247 cs->mode |= SPI_CLK_MODE0; in spi_ppc4xx_setup()
250 cs->mode |= SPI_CLK_MODE1; in spi_ppc4xx_setup()
[all …]
Dspi-gpio.c219 unsigned long cs = spi_gpio->cs_gpios[spi->chip_select]; in spi_gpio_chipselect() local
225 if (cs != SPI_GPIO_NO_CHIPSELECT) { in spi_gpio_chipselect()
227 gpio_set_value_cansleep(cs, (spi->mode & SPI_CS_HIGH) ? is_active : !is_active); in spi_gpio_chipselect()
233 unsigned long cs; in spi_gpio_setup() local
243 cs = spi_gpio->cs_gpios[spi->chip_select]; in spi_gpio_setup()
248 cs = (uintptr_t) spi->controller_data; in spi_gpio_setup()
252 if (cs != SPI_GPIO_NO_CHIPSELECT) { in spi_gpio_setup()
253 status = gpio_request(cs, dev_name(&spi->dev)); in spi_gpio_setup()
256 status = gpio_direction_output(cs, in spi_gpio_setup()
262 spi_gpio->cs_gpios[spi->chip_select] = cs; in spi_gpio_setup()
[all …]
Dspi-mpc512x-psc.c86 struct mpc512x_psc_spi_cs *cs = spi->controller_state; in mpc512x_psc_spi_transfer_setup() local
88 cs->speed_hz = (t && t->speed_hz) in mpc512x_psc_spi_transfer_setup()
90 cs->bits_per_word = (t && t->bits_per_word) in mpc512x_psc_spi_transfer_setup()
92 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; in mpc512x_psc_spi_transfer_setup()
98 struct mpc512x_psc_spi_cs *cs = spi->controller_state; in mpc512x_psc_spi_activate_cs() local
126 speed = cs->speed_hz; in mpc512x_psc_spi_activate_cs()
133 mps->bits_per_word = cs->bits_per_word; in mpc512x_psc_spi_activate_cs()
370 struct mpc512x_psc_spi_cs *cs = spi->controller_state; in mpc512x_psc_spi_setup() local
376 if (!cs) { in mpc512x_psc_spi_setup()
377 cs = kzalloc(sizeof *cs, GFP_KERNEL); in mpc512x_psc_spi_setup()
[all …]
Dspi-mpc52xx-psc.c66 struct mpc52xx_psc_spi_cs *cs = spi->controller_state; in mpc52xx_psc_spi_transfer_setup() local
68 cs->speed_hz = (t && t->speed_hz) in mpc52xx_psc_spi_transfer_setup()
70 cs->bits_per_word = (t && t->bits_per_word) in mpc52xx_psc_spi_transfer_setup()
72 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; in mpc52xx_psc_spi_transfer_setup()
78 struct mpc52xx_psc_spi_cs *cs = spi->controller_state; in mpc52xx_psc_spi_activate_cs() local
108 if (cs->speed_hz) in mpc52xx_psc_spi_activate_cs()
109 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
113 mps->bits_per_word = cs->bits_per_word; in mpc52xx_psc_spi_activate_cs()
267 struct mpc52xx_psc_spi_cs *cs = spi->controller_state; in mpc52xx_psc_spi_setup() local
273 if (!cs) { in mpc52xx_psc_spi_setup()
[all …]
Dspi-imx.c64 u8 cs; member
218 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) argument
222 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) argument
223 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) argument
224 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) argument
225 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) argument
226 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) argument
331 ctrl |= MX51_ECSPI_CTRL_CS(config->cs); in mx51_ecspi_config()
335 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs); in mx51_ecspi_config()
338 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); in mx51_ecspi_config()
[all …]
Dspi-omap-100k.c190 struct omap1_spi100k_cs *cs = spi->controller_state; in omap1_spi100k_txrx_pio() local
196 word_len = cs->word_len; in omap1_spi100k_txrx_pio()
246 struct omap1_spi100k_cs *cs = spi->controller_state; in omap1_spi100k_setup_transfer() local
256 cs->word_len = word_len; in omap1_spi100k_setup_transfer()
273 struct omap1_spi100k_cs *cs = spi->controller_state; in omap1_spi100k_setup() local
277 if (!cs) { in omap1_spi100k_setup()
278 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL); in omap1_spi100k_setup()
279 if (!cs) in omap1_spi100k_setup()
281 cs->base = spi100k->base + spi->chip_select * 0x14; in omap1_spi100k_setup()
282 spi->controller_state = cs; in omap1_spi100k_setup()
Dspi-st-ssc4.c204 int cs = spi->cs_gpio; in spi_st_cleanup() local
206 if (gpio_is_valid(cs)) in spi_st_cleanup()
207 devm_gpio_free(&spi->dev, cs); in spi_st_cleanup()
217 int cs = spi->cs_gpio; in spi_st_setup() local
225 if (!gpio_is_valid(cs)) { in spi_st_setup()
226 dev_err(&spi->dev, "%d is not a valid gpio\n", cs); in spi_st_setup()
230 if (devm_gpio_request(&spi->dev, cs, dev_name(&spi->dev))) { in spi_st_setup()
231 dev_err(&spi->dev, "could not request gpio:%d\n", cs); in spi_st_setup()
235 ret = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH); in spi_st_setup()
Dspi-s3c64xx.c653 struct s3c64xx_spi_csinfo *cs = spi->controller_data; in s3c64xx_spi_prepare_message() local
666 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); in s3c64xx_spi_prepare_message()
749 struct s3c64xx_spi_csinfo *cs; in s3c64xx_get_slave_ctrldata() local
765 cs = kzalloc(sizeof(*cs), GFP_KERNEL); in s3c64xx_get_slave_ctrldata()
766 if (!cs) { in s3c64xx_get_slave_ctrldata()
772 cs->fb_delay = fb_delay; in s3c64xx_get_slave_ctrldata()
774 return cs; in s3c64xx_get_slave_ctrldata()
785 struct s3c64xx_spi_csinfo *cs = spi->controller_data; in s3c64xx_spi_setup() local
792 cs = s3c64xx_get_slave_ctrldata(spi); in s3c64xx_spi_setup()
793 spi->controller_data = cs; in s3c64xx_spi_setup()
[all …]
/linux-4.4.14/net/core/
Dnetclassid_cgroup.c34 struct cgroup_cls_state *cs; in cgrp_css_alloc() local
36 cs = kzalloc(sizeof(*cs), GFP_KERNEL); in cgrp_css_alloc()
37 if (!cs) in cgrp_css_alloc()
40 return &cs->css; in cgrp_css_alloc()
45 struct cgroup_cls_state *cs = css_cls_state(css); in cgrp_css_online() local
49 cs->classid = parent->classid; in cgrp_css_online()
101 struct cgroup_cls_state *cs = css_cls_state(css); in write_classid() local
103 cs->classid = (u32)value; in write_classid()
105 update_classid(css, (void *)(unsigned long)cs->classid); in write_classid()
/linux-4.4.14/sound/core/
Dpcm_iec958.c27 int snd_pcm_create_iec958_consumer(struct snd_pcm_runtime *runtime, u8 *cs, in snd_pcm_create_iec958_consumer() argument
83 memset(cs, 0, len); in snd_pcm_create_iec958_consumer()
85 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; in snd_pcm_create_iec958_consumer()
86 cs[1] = IEC958_AES1_CON_GENERAL; in snd_pcm_create_iec958_consumer()
87 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; in snd_pcm_create_iec958_consumer()
88 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | fs; in snd_pcm_create_iec958_consumer()
91 cs[4] = ws; in snd_pcm_create_iec958_consumer()
/linux-4.4.14/Documentation/devicetree/bindings/memory-controllers/
Dti-aemif.txt56 Child chip-select (cs) nodes contain the memory devices nodes connected to
60 Required child cs node properties:
73 - ti,cs-chipselect: number of chipselect. Indicates on the aemif driver
79 Optional child cs node properties:
81 - ti,cs-bus-width: width of the asynchronous device's data bus
84 - ti,cs-select-strobe-mode: enable/disable select strobe mode
89 - ti,cs-extended-wait-mode: enable/disable extended wait mode
95 - ti,cs-min-turnaround-ns: minimum turn around time, ns
102 - ti,cs-read-setup-ns: read setup width, ns
107 - ti,cs-read-strobe-ns: read strobe width, ns
[all …]
Darm,pl172.txt28 Child chip-select (cs) nodes contain the memory devices nodes connected to
31 Required child cs node properties:
44 - mpmc,cs: Chip select number. Indicates to the pl0172 driver
50 Optional child cs node config properties:
54 - mpmc,cs-active-high: Set chip select polarity to active high.
65 Optional child cs node timing properties:
107 mpmc,cs = <0>;
/linux-4.4.14/sound/usb/
Dclock.c41 struct uac_clock_source_descriptor *cs = NULL; in snd_usb_find_clock_source() local
43 while ((cs = snd_usb_find_csint_desc(ctrl_iface->extra, in snd_usb_find_clock_source()
45 cs, UAC2_CLOCK_SOURCE))) { in snd_usb_find_clock_source()
46 if (cs->bClockID == clock_id) in snd_usb_find_clock_source()
47 return cs; in snd_usb_find_clock_source()
57 struct uac_clock_selector_descriptor *cs = NULL; in snd_usb_find_clock_selector() local
59 while ((cs = snd_usb_find_csint_desc(ctrl_iface->extra, in snd_usb_find_clock_selector()
61 cs, UAC2_CLOCK_SELECTOR))) { in snd_usb_find_clock_selector()
62 if (cs->bClockID == clock_id) in snd_usb_find_clock_selector()
63 return cs; in snd_usb_find_clock_selector()
[all …]
/linux-4.4.14/arch/x86/include/asm/
Dptrace.h25 unsigned long cs; member
61 unsigned long cs; member
109 return ((regs->cs & SEGMENT_RPL_MASK) | (regs->flags & X86_VM_MASK)) >= USER_RPL; in user_mode()
111 return !!(regs->cs & 3); in user_mode()
132 return regs->cs == __USER_CS; in user_64bit_mode()
135 return regs->cs == __USER_CS || regs->cs == pv_info.extra_user_64bit_cs; in user_64bit_mode()
183 regs->cs == __KERNEL_CS) in regs_get_register()
/linux-4.4.14/arch/m68k/lib/
Dmemset.c21 char *cs = s; in memset() local
22 *cs++ = c; in memset()
23 s = cs; in memset()
69 char *cs = s; in memset() local
70 *cs = c; in memset()
/linux-4.4.14/tools/build/feature/
Dtest-pthread-attr-setaffinity-np.c9 cpu_set_t cs; in main() local
12 CPU_ZERO(&cs); in main()
14 ret = pthread_attr_setaffinity_np(&thread_attr, sizeof(cs), &cs); in main()
/linux-4.4.14/Documentation/ABI/testing/
Dsysfs-kernel-slab4 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
16 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
25 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
34 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
45 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
56 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
68 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
79 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
90 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
102 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
[all …]
/linux-4.4.14/arch/mips/include/asm/mach-bcm63xx/
Dbcm63xx_cs.h4 int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size);
5 int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
7 int bcm63xx_set_cs_param(unsigned int cs, u32 flags);
8 int bcm63xx_set_cs_status(unsigned int cs, int enable);
/linux-4.4.14/drivers/mtd/maps/
Dpismo.c33 struct pismo_cs_block cs[PISMO_NUM_CS]; member
159 const struct pismo_cs_block *cs, phys_addr_t base) in pismo_add_one() argument
165 region.type = cs->type; in pismo_add_one()
166 region.width = pismo_width_to_bytes(cs->width); in pismo_add_one()
167 region.access = le16_to_cpu(cs->access); in pismo_add_one()
168 region.size = le32_to_cpu(cs->size); in pismo_add_one()
171 dev_err(dev, "cs%u: bad width: %02x, ignoring\n", i, cs->width); in pismo_add_one()
182 i, cs->device, region.type, region.access, region.size / 1024); in pismo_add_one()
247 for (i = 0; i < ARRAY_SIZE(eeprom.cs); i++) in pismo_probe()
248 if (eeprom.cs[i].type != 0xff) in pismo_probe()
[all …]
/linux-4.4.14/arch/mips/cavium-octeon/
Docteon-platform.c775 int cs, bootbus; in octeon_prune_device_tree() local
796 for (cs = 0; cs < 8; cs++) { in octeon_prune_device_tree()
797 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); in octeon_prune_device_tree()
806 if (cs >= 7) { in octeon_prune_device_tree()
820 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); in octeon_prune_device_tree()
836 new_reg[0] = cpu_to_be32(cs); in octeon_prune_device_tree()
839 new_reg[3] = cpu_to_be32(cs + 1); in octeon_prune_device_tree()
852 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); in octeon_prune_device_tree()
853 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); in octeon_prune_device_tree()
854 ranges[(cs * 5) + 4] = cpu_to_be32(region_size); in octeon_prune_device_tree()
[all …]
Dflash_setup.c73 u32 cs; in octeon_flash_probe() local
77 r = of_property_read_u32(np, "reg", &cs); in octeon_flash_probe()
85 region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); in octeon_flash_probe()
/linux-4.4.14/drivers/usb/host/
Dxhci-mvebu.c34 const struct mbus_dram_window *cs = dram->cs + win; in xhci_mvebu_mbus_config() local
36 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | in xhci_mvebu_mbus_config()
40 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(win)); in xhci_mvebu_mbus_config()
Dehci-orion.c145 const struct mbus_dram_window *cs = dram->cs + i; in ehci_orion_conf_mbus_windows() local
147 wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) | in ehci_orion_conf_mbus_windows()
148 (cs->mbus_attr << 8) | in ehci_orion_conf_mbus_windows()
150 wrl(USB_WINDOW_BASE(i), cs->base); in ehci_orion_conf_mbus_windows()
/linux-4.4.14/tools/testing/selftests/x86/
Dsigreturn.c278 unsigned short cs, gs, fs, ss; member
290 return &sels->cs; in csptr()
368 int cs_bitness(unsigned short cs) in cs_bitness() argument
376 : [cs] "r" (cs)); in cs_bitness()
419 int cs = find_cs(cs_bits); in test_valid_sigreturn() local
420 if (cs == -1) { in test_valid_sigreturn()
441 sig_cs = cs; in test_valid_sigreturn()
484 if (req_sels->cs != res_sels->cs) { in test_valid_sigreturn()
486 req_sels->cs, res_sels->cs); in test_valid_sigreturn()
532 int cs = force_cs == -1 ? find_cs(cs_bits) : force_cs; in test_bad_iret() local
[all …]
/linux-4.4.14/arch/arm/boot/dts/
Dk2l-evm.dts53 ti,cs-chipselect = <0>;
55 ti,cs-min-turnaround-ns = <12>;
56 ti,cs-read-hold-ns = <6>;
57 ti,cs-read-strobe-ns = <23>;
58 ti,cs-read-setup-ns = <9>;
59 ti,cs-write-hold-ns = <8>;
60 ti,cs-write-strobe-ns = <23>;
61 ti,cs-write-setup-ns = <8>;
Dk2e-evm.dts76 ti,cs-chipselect = <0>;
78 ti,cs-min-turnaround-ns = <12>;
79 ti,cs-read-hold-ns = <6>;
80 ti,cs-read-strobe-ns = <23>;
81 ti,cs-read-setup-ns = <9>;
82 ti,cs-write-hold-ns = <8>;
83 ti,cs-write-strobe-ns = <23>;
84 ti,cs-write-setup-ns = <8>;
Dk2hk-evm.dts97 ti,cs-chipselect = <0>;
99 ti,cs-min-turnaround-ns = <12>;
100 ti,cs-read-hold-ns = <6>;
101 ti,cs-read-strobe-ns = <23>;
102 ti,cs-read-setup-ns = <9>;
103 ti,cs-write-hold-ns = <8>;
104 ti,cs-write-strobe-ns = <23>;
105 ti,cs-write-setup-ns = <8>;
Domap3430-sdp.dts66 gpmc,cs-on-ns = <0>;
67 gpmc,cs-rd-off-ns = <186>;
68 gpmc,cs-wr-off-ns = <186>;
112 gpmc,cs-on-ns = <0>;
113 gpmc,cs-rd-off-ns = <36>;
114 gpmc,cs-wr-off-ns = <36>;
157 gpmc,cs-on-ns = <0>;
158 gpmc,cs-rd-off-ns = <84>;
159 gpmc,cs-wr-off-ns = <72>;
Domap-gpmc-smsc911x.dtsi29 gpmc,cs-on-ns = <5>;
30 gpmc,cs-rd-off-ns = <150>;
31 gpmc,cs-wr-off-ns = <150>;
Domap-gpmc-smsc9221.dtsi32 gpmc,cs-on-ns = <0>;
33 gpmc,cs-rd-off-ns = <42>;
34 gpmc,cs-wr-off-ns = <36>;
Domap2420-h4.dts34 gpmc,cs-on-ns = <10>;
35 gpmc,cs-rd-off-ns = <160>;
36 gpmc,cs-wr-off-ns = <160>;
Domap3-overo-tobiduo-common.dtsi32 gpmc,cs-on-ns = <0>;
33 gpmc,cs-rd-off-ns = <42>;
34 gpmc,cs-wr-off-ns = <36>;
/linux-4.4.14/Documentation/devicetree/bindings/gpio/
Dspear_spics.txt21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
36 st-spics,cs-value-bit = <11>;
37 st-spics,cs-enable-mask = <3>;
38 st-spics,cs-enable-shift = <8>;
46 num-cs = <3>;
47 cs-gpios = <&gpio1 7 0>, <&spics 0>,
/linux-4.4.14/arch/x86/lib/
Dstring_32.c94 int strcmp(const char *cs, const char *ct) in strcmp() argument
109 : "1" (cs), "2" (ct) in strcmp()
117 int strncmp(const char *cs, const char *ct, size_t count) in strncmp() argument
134 : "1" (cs), "2" (ct), "3" (count) in strncmp()
179 void *memchr(const void *cs, int c, size_t count) in memchr() argument
191 : "a" (c), "0" (cs), "1" (count) in memchr()
Dstrstr_32.c3 char *strstr(const char *cs, const char *ct) in strstr() argument
27 : "0" (0), "1" (0xffffffff), "2" (cs), "g" (ct) in strstr()
/linux-4.4.14/arch/arm/mach-imx/
Dmx27.h117 #define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10) argument
118 #define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs)) argument
119 #define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) argument
120 #define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) argument
Dmx31.h111 #define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10) argument
112 #define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs)) argument
113 #define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) argument
114 #define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) argument
/linux-4.4.14/arch/nios2/kernel/
Dtime.c48 struct clocksource cs; member
58 to_nios2_clksource(struct clocksource *cs) in to_nios2_clksource() argument
60 return container_of(cs, struct nios2_clocksource, cs); in to_nios2_clksource()
84 static cycle_t nios2_timer_read(struct clocksource *cs) in nios2_timer_read() argument
86 struct nios2_clocksource *nios2_cs = to_nios2_clksource(cs); in nios2_timer_read()
99 .cs = {
110 return nios2_timer_read(&nios2_cs.cs); in get_cycles()
274 clocksource_register_hz(&nios2_cs.cs, freq); in nios2_clocksource_init()
/linux-4.4.14/Documentation/devicetree/bindings/spi/
Dspi-dw.txt10 - num-cs: see spi-bus.txt
13 - cs-gpios: see spi-bus.txt
22 num-cs = <2>;
23 cs-gpios = <&banka 0 0>;
Dbrcm,bcm2835-aux-spi.txt15 - cs-gpios: the cs-gpios (native cs is NOT supported)
27 cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>;
37 cs-gpios = <&gpio 43>, <&gpio 44>, <&gpio 45>;
Dsnps,dw-apb-ssi.txt11 - cs-gpios : Specifies the gpio pis to be used for chipselects.
12 - num-cs : The number of chipselects. If omitted, this will default to 4.
26 num-cs = <2>;
27 cs-gpios = <&gpio0 13 0>,
Dspi-bus.txt15 - cs-gpios - (optional) gpios chip select.
26 - num-cs : total number of chipselects
28 If cs-gpios is used the number of chip select will automatically increased
29 with max(cs-gpios > hw cs)
31 So if for example the controller has 2 CS lines, and the cs-gpios
34 cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;
54 - spi-cs-high - (optional) Empty property indicating device requires
72 via the SPI master node cs-gpios property.
Dspi-cadence.txt15 - num-cs : Number of chip selects used.
18 - is-decoded-cs : Flag to indicate whether decoder is used or not.
28 num-cs = <4>;
29 is-decoded-cs = <0>;
Dspi-fsl-dspi.txt20 - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
22 - fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
52 fsl,spi-cs-sck-delay = <100>;
53 fsl,spi-sck-cs-delay = <50>;
Domap-spi.txt7 - ti,spi-num-cs : Number of chipselect supported by the instance.
31 ti,spi-num-cs = <4>;
41 ti,spi-num-cs = <2>;
/linux-4.4.14/arch/arm/mach-footbridge/
Ddc21285-timer.c22 static cycle_t cksrc_dc21285_read(struct clocksource *cs) in cksrc_dc21285_read() argument
24 return cs->mask - *CSR_TIMER2_VALUE; in cksrc_dc21285_read()
27 static int cksrc_dc21285_enable(struct clocksource *cs) in cksrc_dc21285_enable() argument
29 *CSR_TIMER2_LOAD = cs->mask; in cksrc_dc21285_enable()
35 static void cksrc_dc21285_disable(struct clocksource *cs) in cksrc_dc21285_disable() argument
/linux-4.4.14/drivers/gpu/drm/bridge/
Ddw_hdmi-ahb-audio.c139 u8 cs[192][8]; member
197 u8 *cs; in dw_hdmi_reformat_s24() local
199 cs = dw->cs[dw->iec_offset++]; in dw_hdmi_reformat_s24()
208 sample |= *cs++ << 24; in dw_hdmi_reformat_s24()
219 u8 cs[4]; in dw_hdmi_create_cs() local
222 snd_pcm_create_iec958_consumer(runtime, cs, sizeof(cs)); in dw_hdmi_create_cs()
224 memset(dw->cs, 0, sizeof(dw->cs)); in dw_hdmi_create_cs()
227 cs[2] &= ~IEC958_AES2_CON_CHANNEL; in dw_hdmi_create_cs()
228 cs[2] |= (ch + 1) << 4; in dw_hdmi_create_cs()
230 for (i = 0; i < ARRAY_SIZE(cs); i++) { in dw_hdmi_create_cs()
[all …]
/linux-4.4.14/drivers/mtd/nand/
Dpxa3xx_nand.c180 int cs; member
224 int cs; member
778 if (info->cs == 0) { in pxa3xx_nand_irq()
897 struct pxa3xx_nand_host *host = info->host[info->cs]; in prepare_start_command()
950 host = info->host[info->cs]; in prepare_set_command()
955 if (info->cs != 0) in prepare_set_command()
1138 if (info->cs != host->cs) { in nand_cmdfunc()
1139 info->cs = host->cs; in nand_cmdfunc()
1186 if (info->cs != host->cs) { in nand_cmdfunc_extended()
1187 info->cs = host->cs; in nand_cmdfunc_extended()
[all …]
Dndfc.c204 u32 cs; in ndfc_probe() local
214 cs = be32_to_cpu(reg[0]); in ndfc_probe()
215 if (cs >= NDFC_MAX_CS) { in ndfc_probe()
216 dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs); in ndfc_probe()
220 ndfc = &ndfc_ctrl[cs]; in ndfc_probe()
221 ndfc->chip_select = cs; in ndfc_probe()
Dau1550nd.c29 int cs; member
226 alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL); in au1550_hwcontrol()
409 int ret, cs; in au1550nd_probe() local
445 cs = find_nand_cs(r->start); in au1550nd_probe()
446 if (cs < 0) { in au1550nd_probe()
451 ctx->cs = cs; in au1550nd_probe()
/linux-4.4.14/drivers/ata/
Dahci_mvebu.c43 const struct mbus_dram_window *cs = dram->cs + i; in ahci_mvebu_mbus_config() local
45 writel((cs->mbus_attr << 8) | in ahci_mvebu_mbus_config()
48 writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i)); in ahci_mvebu_mbus_config()
49 writel(((cs->size - 1) & 0xffff0000), in ahci_mvebu_mbus_config()
Dpata_at91.c48 unsigned int cs; member
257 regmap_fields_write(fields.setup, info->cs, in set_smc_timing()
262 regmap_fields_write(fields.pulse, info->cs, in set_smc_timing()
267 regmap_fields_write(fields.cycle, info->cs, in set_smc_timing()
270 regmap_fields_write(fields.mode, info->cs, info->mode | in set_smc_timing()
299 regmap_fields_read(fields.mode, info->cs, &mode); in pata_at91_data_xfer_noirq()
302 regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) | in pata_at91_data_xfer_noirq()
308 regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) | in pata_at91_data_xfer_noirq()
425 info->cs = board->chipselect; in pata_at91_probe()
/linux-4.4.14/drivers/ps3/
Dps3av_cmd.c40 int cs; member
45 .cs = PS3AV_CMD_VIDEO_CS_RGB_8,
49 .cs = PS3AV_CMD_VIDEO_CS_RGB_10,
53 .cs = PS3AV_CMD_VIDEO_CS_RGB_12,
57 .cs = PS3AV_CMD_VIDEO_CS_YUV444_8,
61 .cs = PS3AV_CMD_VIDEO_CS_YUV444_10,
65 .cs = PS3AV_CMD_VIDEO_CS_YUV444_12,
69 .cs = PS3AV_CMD_VIDEO_CS_YUV422_8,
73 .cs = PS3AV_CMD_VIDEO_CS_YUV422_10,
77 .cs = PS3AV_CMD_VIDEO_CS_YUV422_12,
[all …]
/linux-4.4.14/drivers/media/v4l2-core/
Dv4l2-ctrls.c2697 struct v4l2_ext_controls *cs, in prepare_ext_ctrls() argument
2705 for (i = 0, h = helpers; i < cs->count; i++, h++) { in prepare_ext_ctrls()
2706 struct v4l2_ext_control *c = &cs->controls[i]; in prepare_ext_ctrls()
2711 cs->error_idx = i; in prepare_ext_ctrls()
2713 if (cs->ctrl_class && V4L2_CTRL_ID2CLASS(id) != cs->ctrl_class) in prepare_ext_ctrls()
2764 for (i = 0; i < cs->count; i++) in prepare_ext_ctrls()
2766 for (i = 0, h = helpers; i < cs->count; i++, h++) { in prepare_ext_ctrls()
2800 int v4l2_g_ext_ctrls(struct v4l2_ctrl_handler *hdl, struct v4l2_ext_controls *cs) in v4l2_g_ext_ctrls() argument
2807 cs->error_idx = cs->count; in v4l2_g_ext_ctrls()
2808 cs->ctrl_class = V4L2_CTRL_ID2CLASS(cs->ctrl_class); in v4l2_g_ext_ctrls()
[all …]
/linux-4.4.14/arch/mips/include/asm/
Dmsa.h165 #define __BUILD_MSA_CTL_REG(name, cs) \ argument
172 " cfcmsa %0, $" #cs "\n" \
183 " ctcmsa $" #cs ", %0\n" \
203 #define __BUILD_MSA_CTL_REG(name, cs) \ argument
211 " .word %1 | (" #cs " << 11)\n" \
225 " .word %1 | (" #cs " << 6)\n" \
/linux-4.4.14/arch/mips/kernel/
Dcsrc-bcm1480.c28 static cycle_t bcm1480_hpt_read(struct clocksource *cs) in bcm1480_hpt_read() argument
48 struct clocksource *cs = &bcm1480_clocksource; in sb1480_clocksource_init() local
54 clocksource_register_hz(cs, zbbus); in sb1480_clocksource_init()
Dcsrc-sb1250.c44 static cycle_t sb1250_hpt_read(struct clocksource *cs) in sb1250_hpt_read() argument
64 struct clocksource *cs = &bcm1250_clocksource; in sb1250_clocksource_init() local
77 clocksource_register_hz(cs, V_SCD_TIMER_FREQ); in sb1250_clocksource_init()
Dcevt-txx9.c26 struct clocksource cs; member
30 static cycle_t txx9_cs_read(struct clocksource *cs) in txx9_cs_read() argument
33 container_of(cs, struct txx9_clocksource, cs); in txx9_cs_read()
41 .cs = {
60 clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk)); in txx9_clocksource_init()
/linux-4.4.14/Documentation/scsi/
DNinjaSCSI.txt10 pcmcia-cs: 3.1.27
19 If you installed pcmcia-cs already, pcmcia reports your card as UNKNOWN
22 You can also use "cardctl" program (this program is in pcmcia-cs source
47 [3] If you use this driver with Kernel 2.2, unpack pcmcia-cs in some directory
48 and make & install. This driver requires the pcmcia-cs header file.
50 $ tar zxvf cs-pcmcia-cs-3.x.x.tar.gz
63 If you use pcmcia-cs-3.1.8 or later, we can use "nsp_cs.conf" file.
98 [7] Start (or restart) pcmcia-cs.
/linux-4.4.14/arch/powerpc/boot/
Dcuboot-pq2.c84 int cs = cs_ranges_buf[i].csnum; in update_cs_ranges() local
85 if (cs >= ctrl_size / 8) in update_cs_ranges()
91 base = in_be32(&ctrl_addr[cs * 2]); in update_cs_ranges()
98 option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff; in update_cs_ranges()
104 out_be32(&ctrl_addr[cs * 2], 0); in update_cs_ranges()
105 out_be32(&ctrl_addr[cs * 2 + 1], in update_cs_ranges()
107 out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr); in update_cs_ranges()
D4xx.c176 u32 val, cs; in ibm4xx_denali_get_cs() local
196 cs = 0; in ibm4xx_denali_get_cs()
199 cs++; in ibm4xx_denali_get_cs()
202 return cs; in ibm4xx_denali_get_cs()
208 u32 cs, col, row, bank, dpath; in ibm4xx_denali_fixup_memsize() local
220 cs = ibm4xx_denali_get_cs(); in ibm4xx_denali_fixup_memsize()
221 if (!cs) in ibm4xx_denali_fixup_memsize()
223 if (cs > max_cs) in ibm4xx_denali_fixup_memsize()
255 memsize = cs * (1 << (col+row)) * bank * dpath; in ibm4xx_denali_fixup_memsize()
/linux-4.4.14/arch/arm/mach-orion5x/
Dpci.c426 const struct mbus_dram_window *cs = dram->cs + i; in orion5x_setup_pci_wins() local
427 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); in orion5x_setup_pci_wins()
434 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); in orion5x_setup_pci_wins()
436 val = (cs->base & 0xfffff000) | (val & 0xfff); in orion5x_setup_pci_wins()
442 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); in orion5x_setup_pci_wins()
444 writel((cs->size - 1) & 0xfffff000, in orion5x_setup_pci_wins()
445 PCI_BAR_SIZE_DDR_CS(cs->cs_index)); in orion5x_setup_pci_wins()
446 writel(cs->base & 0xfffff000, in orion5x_setup_pci_wins()
447 PCI_BAR_REMAP_DDR_CS(cs->cs_index)); in orion5x_setup_pci_wins()
452 win_enable &= ~(1 << cs->cs_index); in orion5x_setup_pci_wins()
Dcommon.h22 #define ORION_MBUS_DEVBUS_TARGET(cs) 0x01 argument
23 #define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs)) argument
/linux-4.4.14/arch/mips/txx9/generic/
Dmem_tx4927.c45 unsigned int cs = 0; in tx4927_process_sdccr() local
60 cs = 256 << sdccr_cs; in tx4927_process_sdccr()
64 return rs * cs * mw * bs; in tx4927_process_sdccr()
/linux-4.4.14/Documentation/devicetree/bindings/mtd/
Dgpmc-nor.txt14 - gpmc,cs-on-ns: Chip-select assertion time
15 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
16 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
44 gpmc,num-cs = <8>;
60 gpmc,cs-on-ns = <0>;
61 gpmc,cs-rd-off-ns = <186>;
62 gpmc,cs-wr-off-ns = <186>;
/linux-4.4.14/include/trace/events/
Dmce.h30 __field( u8, cs )
48 __entry->cs = m->cs;
58 __entry->cs, __entry->ip,
/linux-4.4.14/arch/arm/boot/compressed/
Dstring.c68 int memcmp(const void *cs, const void *ct, size_t count) in memcmp() argument
70 const unsigned char *su1 = cs, *su2 = ct, *end = su1 + count; in memcmp()
81 int strcmp(const char *cs, const char *ct) in strcmp() argument
87 c1 = *cs++; in strcmp()
/linux-4.4.14/arch/arm/plat-orion/
Dpcie.c155 const struct mbus_dram_window *cs = dram->cs + i; in orion_pcie_setup_wins() local
157 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); in orion_pcie_setup_wins()
159 writel(((cs->size - 1) & 0xffff0000) | in orion_pcie_setup_wins()
160 (cs->mbus_attr << 8) | in orion_pcie_setup_wins()
164 size += cs->size; in orion_pcie_setup_wins()
176 writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); in orion_pcie_setup_wins()
/linux-4.4.14/drivers/input/joystick/iforce/
Diforce-serio.c32 unsigned char cs; in iforce_serial_xmit() local
50 cs = 0x2b; in iforce_serial_xmit()
55 cs ^= iforce->xmit.buf[iforce->xmit.tail]; in iforce_serial_xmit()
60 cs ^= iforce->xmit.buf[iforce->xmit.tail]; in iforce_serial_xmit()
64 serio_write(iforce->serio, cs); in iforce_serial_xmit()
/linux-4.4.14/drivers/edac/
Dpasemi_edac.c100 u32 cs; in pasemi_edac_process_error_info() local
107 cs = (errlog1a & MCDEBUG_ERRLOG1A_MERR_CS_M) >> in pasemi_edac_process_error_info()
114 mci->csrows[cs]->first_page, 0, 0, in pasemi_edac_process_error_info()
115 cs, 0, -1, mci->ctl_name, ""); in pasemi_edac_process_error_info()
121 mci->csrows[cs]->first_page, 0, 0, in pasemi_edac_process_error_info()
122 cs, 0, -1, mci->ctl_name, ""); in pasemi_edac_process_error_info()
/linux-4.4.14/drivers/video/fbdev/
Dmetronomefb.c311 u16 cs; in metronome_display_cmd() local
321 opcode = cs = 0xCC41; in metronome_display_cmd()
323 opcode = cs = 0xCC40; in metronome_display_cmd()
330 cs += par->metromem_cmd->args[i++]; in metronome_display_cmd()
335 par->metromem_cmd->csum = cs; in metronome_display_cmd()
344 u16 cs; in metronome_powerup_cmd() local
348 cs = par->metromem_cmd->opcode; in metronome_powerup_cmd()
353 cs += par->metromem_cmd->args[i]; in metronome_powerup_cmd()
359 par->metromem_cmd->csum = cs; in metronome_powerup_cmd()
391 u16 cs; in metronome_init_cmd() local
[all …]
/linux-4.4.14/arch/x86/include/asm/xen/
Dinterface_32.h59 uint16_t cs; member
80 unsigned long cs; member
86 ((struct xen_callback){ .cs = (__cs), .eip = (unsigned long)(__eip) })
/linux-4.4.14/Documentation/devicetree/bindings/net/
Dgpmc-eth.txt29 - gpmc,cs-on-ns: Chip-select assertion time
30 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
31 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
55 gpmc,num-cs = <8>;
68 gpmc,cs-on-ns = <0>;
69 gpmc,cs-rd-off-ns = <186>;
70 gpmc,cs-wr-off-ns = <186>;
/linux-4.4.14/drivers/cpufreq/
Dcpufreq_conservative.c278 show_store_one(cs, sampling_rate);
279 show_store_one(cs, sampling_down_factor);
280 show_store_one(cs, up_threshold);
281 show_store_one(cs, down_threshold);
282 show_store_one(cs, ignore_nice_load);
283 show_store_one(cs, freq_step);
284 declare_show_sampling_rate_min(cs);
/linux-4.4.14/block/partitions/
Dsgi.c36 __be32 *ui, cs; in sgi_partition() local
55 cs = *ui--; in sgi_partition()
56 csum += be32_to_cpu(cs); in sgi_partition()
/linux-4.4.14/arch/mips/include/asm/mach-au1x00/
Dau1550_spi.h11 void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
12 void (*deactivate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
/linux-4.4.14/drivers/isdn/mISDN/
Ddsp_blowfish.c377 u32 cs; in dsp_bf_encrypt() local
426 cs = yl ^ (yl >> 3) ^ (yl >> 6) ^ (yl >> 9) ^ (yl >> 12) ^ (yl >> 15) in dsp_bf_encrypt()
441 bf_crypt_out[5] = ((yr >> 22) & 0x7f) | ((cs << 5) & 0x80); in dsp_bf_encrypt()
442 bf_crypt_out[6] = ((yr >> 15) & 0x7f) | ((cs << 6) & 0x80); in dsp_bf_encrypt()
443 bf_crypt_out[7] = ((yr >> 8) & 0x7f) | (cs << 7); in dsp_bf_encrypt()
470 u8 cs, cs0, cs1, cs2; in dsp_bf_decrypt() local
504 cs = yl ^ (yl >> 3) ^ (yl >> 6) ^ (yl >> 9) ^ (yl >> 12) ^ (yl >> 15) in dsp_bf_decrypt()
511 if ((cs & 0x7) != (((cs2 >> 5) & 4) | ((cs1 >> 6) & 2) | (cs0 >> 7))) { in dsp_bf_decrypt()
/linux-4.4.14/drivers/infiniband/hw/qib/
Dqib_sd7220.c1397 struct qib_chip_specific *cs = dd->cspec; in qib_run_relock() local
1414 timeoff = cs->relock_interval << 1; in qib_run_relock()
1417 cs->relock_interval = timeoff; in qib_run_relock()
1420 mod_timer(&cs->relock_timer, jiffies + timeoff); in qib_run_relock()
1425 struct qib_chip_specific *cs = dd->cspec; in set_7220_relock_poll() local
1429 if (cs->relock_timer_active) { in set_7220_relock_poll()
1430 cs->relock_interval = HZ; in set_7220_relock_poll()
1431 mod_timer(&cs->relock_timer, jiffies + HZ); in set_7220_relock_poll()
1441 if (!cs->relock_timer_active) { in set_7220_relock_poll()
1442 cs->relock_timer_active = 1; in set_7220_relock_poll()
[all …]
/linux-4.4.14/drivers/staging/lustre/lustre/mdc/
Dmdc_request.c1462 struct changelog_show *cs = data; in changelog_kkuc_cb() local
1470 cs->cs_obd->obd_name, rec->cr_hdr.lrh_type, in changelog_kkuc_cb()
1475 if (rec->cr.cr_index < cs->cs_startrec) { in changelog_kkuc_cb()
1478 rec->cr.cr_index, cs->cs_startrec); in changelog_kkuc_cb()
1492 lh = changelog_kuc_hdr(cs->cs_buf, len, cs->cs_flags); in changelog_kkuc_cb()
1495 rc = libcfs_kkuc_msg_put(cs->cs_fp, lh); in changelog_kkuc_cb()
1496 CDEBUG(D_CHANGELOG, "kucmsg fp %p len %d rc %d\n", cs->cs_fp, len, rc); in changelog_kkuc_cb()
1503 struct changelog_show *cs = csdata; in mdc_changelog_send_thread() local
1510 cs->cs_fp, cs->cs_startrec); in mdc_changelog_send_thread()
1512 cs->cs_buf = kzalloc(KUC_CHANGELOG_MSG_MAXSIZE, GFP_NOFS); in mdc_changelog_send_thread()
[all …]
/linux-4.4.14/sound/soc/kirkwood/
Dkirkwood-dma.c93 const struct mbus_dram_window *cs = dram->cs + i; in kirkwood_dma_conf_mbus_windows() local
94 if ((cs->base & 0xffff0000) < (dma & 0xffff0000)) { in kirkwood_dma_conf_mbus_windows()
95 writel(cs->base & 0xffff0000, in kirkwood_dma_conf_mbus_windows()
97 writel(((cs->size - 1) & 0xffff0000) | in kirkwood_dma_conf_mbus_windows()
98 (cs->mbus_attr << 8) | in kirkwood_dma_conf_mbus_windows()
/linux-4.4.14/arch/s390/lib/
Dstring.c203 int strcmp(const char *cs, const char *ct) in strcmp() argument
215 : "+d" (ret), "+d" (r0), "+a" (cs), "+a" (ct) in strcmp()
303 int memcmp(const void *cs, const void *ct, size_t n) in memcmp() argument
305 register unsigned long r2 asm("2") = (unsigned long) cs; in memcmp()
/linux-4.4.14/Documentation/devicetree/bindings/rtc/
Dnxp,rtc-2123.txt8 - spi-cs-high: PCF2123 needs chipselect high
15 spi-cs-high;
/linux-4.4.14/drivers/firmware/efi/libstub/
Dstring.c42 int strncmp(const char *cs, const char *ct, size_t count) in strncmp() argument
47 c1 = *cs++; in strncmp()
/linux-4.4.14/Documentation/devicetree/bindings/bus/
Dimx-weim.txt25 <cs-number> 0 <physical address of mapping> <size>
29 - fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
49 - fsl,weim-cs-timing: The timing array, contains timing values for the
71 fsl,weim-cs-gpr = <&gpr>;
79 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
/linux-4.4.14/drivers/mtd/nand/brcmnand/
Dbrcmnand.c86 u32 cs; member
184 int cs; member
553 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs, in brcmnand_cs_offset() argument
560 if (cs == 0 && ctrl->cs0_offsets) in brcmnand_cs_offset()
565 if (cs && offs_cs1) in brcmnand_cs_offset()
566 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
568 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
583 int cs = host->cs; in brcmnand_wr_corr_thresh() local
593 if (cs >= 5) in brcmnand_wr_corr_thresh()
595 shift = (cs % 5) * bits; in brcmnand_wr_corr_thresh()
[all …]
/linux-4.4.14/lib/
Dstring.c321 int strcmp(const char *cs, const char *ct) in strcmp() argument
326 c1 = *cs++; in strcmp()
345 int strncmp(const char *cs, const char *ct, size_t count) in strncmp() argument
350 c1 = *cs++; in strncmp()
562 char *strpbrk(const char *cs, const char *ct) in strpbrk() argument
566 for (sc1 = cs; *sc1 != '\0'; ++sc1) { in strpbrk()
765 __visible int memcmp(const void *cs, const void *ct, size_t count) in memcmp() argument
770 for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) in memcmp()
/linux-4.4.14/arch/blackfin/include/asm/
Dstring.h21 extern int strcmp(const char *cs, const char *ct);
24 extern int strncmp(const char *cs, const char *ct, size_t count);
/linux-4.4.14/arch/avr32/mach-at32ap/include/mach/
Dsmc.h110 extern int smc_set_configuration(int cs, const struct smc_config *config);
111 extern struct smc_config *smc_get_configuration(int cs);

1234