Lines Matching refs:cs
62 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val) in Write_hfc() argument
64 byteout(cs->hw.hfcsx.base + 1, regnum); in Write_hfc()
65 byteout(cs->hw.hfcsx.base, val); in Write_hfc()
69 Read_hfc(struct IsdnCardState *cs, u_char regnum) in Read_hfc() argument
73 byteout(cs->hw.hfcsx.base + 1, regnum); in Read_hfc()
74 ret = bytein(cs->hw.hfcsx.base); in Read_hfc()
83 fifo_select(struct IsdnCardState *cs, u_char fifo) in fifo_select() argument
85 if (fifo == cs->hw.hfcsx.last_fifo) in fifo_select()
88 byteout(cs->hw.hfcsx.base + 1, HFCSX_FIF_SEL); in fifo_select()
89 byteout(cs->hw.hfcsx.base, fifo); in fifo_select()
90 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in fifo_select()
92 byteout(cs->hw.hfcsx.base, fifo); in fifo_select()
93 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in fifo_select()
101 reset_fifo(struct IsdnCardState *cs, u_char fifo) in reset_fifo() argument
103 fifo_select(cs, fifo); /* first select the fifo */ in reset_fifo()
104 byteout(cs->hw.hfcsx.base + 1, HFCSX_CIRM); in reset_fifo()
105 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */ in reset_fifo()
107 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in reset_fifo()
117 write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans_max) in write_fifo() argument
126 fifo_select(cs, fifo); in write_fifo()
133 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ in write_fifo()
137 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); in write_fifo()
138 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); in write_fifo()
142 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); in write_fifo()
143 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); in write_fifo()
153 Write_hfc(cs, HFCSX_FIF_DWR, *src++); in write_fifo()
157 msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker; in write_fifo()
159 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk; in write_fifo()
160 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk; in write_fifo()
166 if (cs->debug & L1_DEB_ISAC_FIFO) in write_fifo()
167 debugl1(cs, "hfcsx_write_fifo %d more as %d frames", fifo, f_msk - 1); in write_fifo()
173 if (cs->debug & L1_DEB_ISAC_FIFO) in write_fifo()
174 debugl1(cs, "hfcsx_write_fifo %d f1(%x) f2(%x) z1(f1)(%x)", in write_fifo()
181 if (cs->debug & L1_DEB_ISAC_FIFO) in write_fifo()
182 debugl1(cs, "hfcsx_write_fifo %d count(%u/%d)", in write_fifo()
185 if (cs->debug & L1_DEB_ISAC_FIFO) in write_fifo()
186 debugl1(cs, "hfcsx_write_fifo %d no fifo mem", fifo); in write_fifo()
193 Write_hfc(cs, HFCSX_FIF_DWR, *src++); in write_fifo()
195 Read_hfc(cs, HFCSX_FIF_INCF1); /* increment F1 */ in write_fifo()
197 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in write_fifo()
207 read_fifo(struct IsdnCardState *cs, u_char fifo, int trans_max) in read_fifo() argument
213 fifo_select(cs, fifo); in read_fifo()
220 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ in read_fifo()
226 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); in read_fifo()
227 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); in read_fifo()
228 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); in read_fifo()
229 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); in read_fifo()
241 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD); in read_fifo()
248 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk; in read_fifo()
249 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk; in read_fifo()
253 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); in read_fifo()
254 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); in read_fifo()
255 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); in read_fifo()
256 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); in read_fifo()
258 if (cs->debug & L1_DEB_ISAC_FIFO) in read_fifo()
259 debugl1(cs, "hfcsx_read_fifo %d f1(%x) f2(%x) z1(f2)(%x) z2(f2)(%x)", in read_fifo()
267 if (cs->debug & L1_DEB_ISAC_FIFO) in read_fifo()
268 debugl1(cs, "hfcsx_read_fifo %d count %u)", in read_fifo()
272 if (cs->debug & L1_DEB_WARN) in read_fifo()
273 debugl1(cs, "hfcsx_read_fifo %d packet inv. len %d ", fifo , count); in read_fifo()
276 Read_hfc(cs, HFCSX_FIF_DRD); in read_fifo()
285 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD); in read_fifo()
287 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 1 */ in read_fifo()
288 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 2 */ in read_fifo()
289 if (Read_hfc(cs, HFCSX_FIF_DRD)) { in read_fifo()
291 if (cs->debug & L1_DEB_ISAC_FIFO) in read_fifo()
292 debugl1(cs, "hfcsx_read_fifo %d crc error", fifo); in read_fifo()
300 Read_hfc(cs, HFCSX_FIF_INCF2); /* increment F2 */ in read_fifo()
302 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in read_fifo()
312 release_io_hfcsx(struct IsdnCardState *cs) in release_io_hfcsx() argument
314 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ in release_io_hfcsx()
315 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in release_io_hfcsx()
316 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET); /* Reset On */ in release_io_hfcsx()
318 Write_hfc(cs, HFCSX_CIRM, 0); /* Reset Off */ in release_io_hfcsx()
319 del_timer(&cs->hw.hfcsx.timer); in release_io_hfcsx()
320 release_region(cs->hw.hfcsx.base, 2); /* release IO-Block */ in release_io_hfcsx()
321 kfree(cs->hw.hfcsx.extra); in release_io_hfcsx()
322 cs->hw.hfcsx.extra = NULL; in release_io_hfcsx()
329 static int set_fifo_size(struct IsdnCardState *cs) in set_fifo_size() argument
332 if (cs->hw.hfcsx.b_fifo_size) return (1); /* already determined */ in set_fifo_size()
334 if ((cs->hw.hfcsx.chip >> 4) == 9) { in set_fifo_size()
335 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K; in set_fifo_size()
339 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K; in set_fifo_size()
340 cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */ in set_fifo_size()
350 reset_hfcsx(struct IsdnCardState *cs) in reset_hfcsx() argument
352 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ in reset_hfcsx()
353 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in reset_hfcsx()
357 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm); /* Reset */ in reset_hfcsx()
359 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */ in reset_hfcsx()
361 if (Read_hfc(cs, HFCSX_STATUS) & 2) in reset_hfcsx()
363 cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */ in reset_hfcsx()
364 if (!set_fifo_size(cs)) continue; in reset_hfcsx()
368 cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK; /* no echo connect , threshold */ in reset_hfcsx()
369 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in reset_hfcsx()
371 Write_hfc(cs, HFCSX_CLKDEL, 0x0e); /* ST-Bit delay for TE-Mode */ in reset_hfcsx()
372 cs->hw.hfcsx.sctrl_e = HFCSX_AUTO_AWAKE; in reset_hfcsx()
373 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); /* S/T Auto awake */ in reset_hfcsx()
374 cs->hw.hfcsx.bswapped = 0; /* no exchange */ in reset_hfcsx()
375 cs->hw.hfcsx.nt_mode = 0; /* we are in TE mode */ in reset_hfcsx()
376 cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER; in reset_hfcsx()
377 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in reset_hfcsx()
379 cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC | in reset_hfcsx()
381 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in reset_hfcsx()
384 if (Read_hfc(cs, HFCSX_INT_S1)); in reset_hfcsx()
386 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 2); /* HFC ST 2 */ in reset_hfcsx()
388 Write_hfc(cs, HFCSX_STATES, 2); /* HFC ST 2 */ in reset_hfcsx()
389 cs->hw.hfcsx.mst_m = HFCSX_MASTER; /* HFC Master Mode */ in reset_hfcsx()
391 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in reset_hfcsx()
392 cs->hw.hfcsx.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */ in reset_hfcsx()
393 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in reset_hfcsx()
394 cs->hw.hfcsx.sctrl_r = 0; in reset_hfcsx()
395 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in reset_hfcsx()
404 cs->hw.hfcsx.conn = 0x36; /* set data flow directions */ in reset_hfcsx()
405 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in reset_hfcsx()
406 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */ in reset_hfcsx()
407 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */ in reset_hfcsx()
408 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */ in reset_hfcsx()
409 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */ in reset_hfcsx()
412 cs->hw.hfcsx.int_m2 = HFCSX_IRQ_ENABLE; in reset_hfcsx()
413 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in reset_hfcsx()
414 if (Read_hfc(cs, HFCSX_INT_S2)); in reset_hfcsx()
421 hfcsx_Timer(struct IsdnCardState *cs) in hfcsx_Timer() argument
423 cs->hw.hfcsx.timer.expires = jiffies + 75; in hfcsx_Timer()
435 Sel_BCS(struct IsdnCardState *cs, int channel) in Sel_BCS() argument
437 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel)) in Sel_BCS()
438 return (&cs->bcs[0]); in Sel_BCS()
439 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel)) in Sel_BCS()
440 return (&cs->bcs[1]); in Sel_BCS()
450 receive_dmsg(struct IsdnCardState *cs) in receive_dmsg() argument
455 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in receive_dmsg()
456 debugl1(cs, "rec_dmsg blocked"); in receive_dmsg()
461 skb = read_fifo(cs, HFCSX_SEL_D_RX, 0); in receive_dmsg()
463 skb_queue_tail(&cs->rq, skb); in receive_dmsg()
464 schedule_event(cs, D_RCVBUFREADY); in receive_dmsg()
468 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in receive_dmsg()
478 struct IsdnCardState *cs = bcs->cs; in main_rec_hfcsx() local
484 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in main_rec_hfcsx()
485 debugl1(cs, "rec_data %d blocked", bcs->channel); in main_rec_hfcsx()
488 skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? in main_rec_hfcsx()
498 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in main_rec_hfcsx()
508 hfcsx_fill_dfifo(struct IsdnCardState *cs) in hfcsx_fill_dfifo() argument
510 if (!cs->tx_skb) in hfcsx_fill_dfifo()
512 if (cs->tx_skb->len <= 0) in hfcsx_fill_dfifo()
515 if (write_fifo(cs, cs->tx_skb, HFCSX_SEL_D_TX, 0)) { in hfcsx_fill_dfifo()
516 dev_kfree_skb_any(cs->tx_skb); in hfcsx_fill_dfifo()
517 cs->tx_skb = NULL; in hfcsx_fill_dfifo()
528 struct IsdnCardState *cs = bcs->cs; in hfcsx_fill_fifo() local
535 if (write_fifo(cs, bcs->tx_skb, in hfcsx_fill_fifo()
536 ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? in hfcsx_fill_fifo()
562 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; in dch_nt_l2l1() local
575 debugl1(cs, "PH_TEST_LOOP B1"); in dch_nt_l2l1()
577 debugl1(cs, "PH_TEST_LOOP B2"); in dch_nt_l2l1()
579 debugl1(cs, "PH_TEST_LOOP DISABLED"); in dch_nt_l2l1()
583 if (cs->debug) in dch_nt_l2l1()
584 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr); in dch_nt_l2l1()
595 hfcsx_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) in hfcsx_auxcmd() argument
601 …(!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_… in hfcsx_auxcmd()
602 spin_lock_irqsave(&cs->lock, flags); in hfcsx_auxcmd()
603 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0); /* HFC ST G0 */ in hfcsx_auxcmd()
605 cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT; in hfcsx_auxcmd()
606 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */ in hfcsx_auxcmd()
608 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 1); /* HFC ST G1 */ in hfcsx_auxcmd()
610 Write_hfc(cs, HFCSX_STATES, 1 | HFCSX_ACTIVATE | HFCSX_DO_ACTION); in hfcsx_auxcmd()
611 cs->dc.hfcsx.ph_state = 1; in hfcsx_auxcmd()
612 cs->hw.hfcsx.nt_mode = 1; in hfcsx_auxcmd()
613 cs->hw.hfcsx.nt_timer = 0; in hfcsx_auxcmd()
614 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_auxcmd()
615 cs->stlist->l2.l2l1 = dch_nt_l2l1; in hfcsx_auxcmd()
616 debugl1(cs, "NT mode activated"); in hfcsx_auxcmd()
619 if ((cs->chanlimit > 1) || (cs->hw.hfcsx.bswapped) || in hfcsx_auxcmd()
620 (cs->hw.hfcsx.nt_mode) || (ic->arg != 12)) in hfcsx_auxcmd()
624 cs->logecho = 1; in hfcsx_auxcmd()
625 cs->hw.hfcsx.trm |= 0x20; /* enable echo chan */ in hfcsx_auxcmd()
626 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_B2REC; in hfcsx_auxcmd()
629 cs->logecho = 0; in hfcsx_auxcmd()
630 cs->hw.hfcsx.trm &= ~0x20; /* disable echo chan */ in hfcsx_auxcmd()
631 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_B2REC; in hfcsx_auxcmd()
633 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; in hfcsx_auxcmd()
634 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; in hfcsx_auxcmd()
635 cs->hw.hfcsx.conn |= 0x10; /* B2-IOM -> B2-ST */ in hfcsx_auxcmd()
636 cs->hw.hfcsx.ctmt &= ~2; in hfcsx_auxcmd()
637 spin_lock_irqsave(&cs->lock, flags); in hfcsx_auxcmd()
638 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in hfcsx_auxcmd()
639 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in hfcsx_auxcmd()
640 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in hfcsx_auxcmd()
641 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in hfcsx_auxcmd()
642 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in hfcsx_auxcmd()
643 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_auxcmd()
644 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_auxcmd()
652 receive_emsg(struct IsdnCardState *cs) in receive_emsg() argument
658 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in receive_emsg()
659 debugl1(cs, "echo_rec_data blocked"); in receive_emsg()
663 skb = read_fifo(cs, HFCSX_SEL_B2_RX, 0); in receive_emsg()
665 if (cs->debug & DEB_DLOG_HEX) { in receive_emsg()
666 ptr = cs->dlog; in receive_emsg()
677 HiSax_putstatus(cs, NULL, cs->dlog); in receive_emsg()
679 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len); in receive_emsg()
685 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in receive_emsg()
696 struct IsdnCardState *cs = dev_id; in hfcsx_interrupt() local
703 if (!(cs->hw.hfcsx.int_m2 & 0x08)) in hfcsx_interrupt()
706 spin_lock_irqsave(&cs->lock, flags); in hfcsx_interrupt()
707 if (HFCSX_ANYINT & (stat = Read_hfc(cs, HFCSX_STATUS))) { in hfcsx_interrupt()
708 val = Read_hfc(cs, HFCSX_INT_S1); in hfcsx_interrupt()
709 if (cs->debug & L1_DEB_ISAC) in hfcsx_interrupt()
710 debugl1(cs, "HFC-SX: stat(%02x) s1(%02x)", stat, val); in hfcsx_interrupt()
712 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_interrupt()
715 if (cs->debug & L1_DEB_ISAC) in hfcsx_interrupt()
716 debugl1(cs, "HFC-SX irq %x %s", val, in hfcsx_interrupt()
717 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ? in hfcsx_interrupt()
719 val &= cs->hw.hfcsx.int_m1; in hfcsx_interrupt()
721 exval = Read_hfc(cs, HFCSX_STATES) & 0xf; in hfcsx_interrupt()
722 if (cs->debug & L1_DEB_ISAC) in hfcsx_interrupt()
723 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcsx.ph_state, in hfcsx_interrupt()
725 cs->dc.hfcsx.ph_state = exval; in hfcsx_interrupt()
726 schedule_event(cs, D_L1STATECHANGE); in hfcsx_interrupt()
730 if (cs->hw.hfcsx.nt_mode) { in hfcsx_interrupt()
731 if ((--cs->hw.hfcsx.nt_timer) < 0) in hfcsx_interrupt()
732 schedule_event(cs, D_L1STATECHANGE); in hfcsx_interrupt()
735 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_interrupt()
738 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
739 cs->hw.hfcsx.int_s1 |= val; in hfcsx_interrupt()
740 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_interrupt()
743 if (cs->hw.hfcsx.int_s1 & 0x18) { in hfcsx_interrupt()
745 val = cs->hw.hfcsx.int_s1; in hfcsx_interrupt()
746 cs->hw.hfcsx.int_s1 = exval; in hfcsx_interrupt()
749 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { in hfcsx_interrupt()
750 if (cs->debug) in hfcsx_interrupt()
751 debugl1(cs, "hfcsx spurious 0x08 IRQ"); in hfcsx_interrupt()
756 if (cs->logecho) in hfcsx_interrupt()
757 receive_emsg(cs); in hfcsx_interrupt()
758 else if (!(bcs = Sel_BCS(cs, 1))) { in hfcsx_interrupt()
759 if (cs->debug) in hfcsx_interrupt()
760 debugl1(cs, "hfcsx spurious 0x10 IRQ"); in hfcsx_interrupt()
765 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { in hfcsx_interrupt()
766 if (cs->debug) in hfcsx_interrupt()
767 debugl1(cs, "hfcsx spurious 0x01 IRQ"); in hfcsx_interrupt()
770 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
772 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
774 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcsx_interrupt()
777 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
779 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
781 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcsx_interrupt()
789 if (!(bcs = Sel_BCS(cs, 1))) { in hfcsx_interrupt()
790 if (cs->debug) in hfcsx_interrupt()
791 debugl1(cs, "hfcsx spurious 0x02 IRQ"); in hfcsx_interrupt()
794 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
796 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
798 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcsx_interrupt()
801 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
803 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
805 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcsx_interrupt()
813 receive_dmsg(cs); in hfcsx_interrupt()
816 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) in hfcsx_interrupt()
817 del_timer(&cs->dbusytimer); in hfcsx_interrupt()
818 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) in hfcsx_interrupt()
819 schedule_event(cs, D_CLEARBUSY); in hfcsx_interrupt()
820 if (cs->tx_skb) { in hfcsx_interrupt()
821 if (cs->tx_skb->len) { in hfcsx_interrupt()
822 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
823 hfcsx_fill_dfifo(cs); in hfcsx_interrupt()
824 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
826 debugl1(cs, "hfcsx_fill_dfifo irq blocked"); in hfcsx_interrupt()
830 dev_kfree_skb_irq(cs->tx_skb); in hfcsx_interrupt()
831 cs->tx_cnt = 0; in hfcsx_interrupt()
832 cs->tx_skb = NULL; in hfcsx_interrupt()
835 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { in hfcsx_interrupt()
836 cs->tx_cnt = 0; in hfcsx_interrupt()
837 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
838 hfcsx_fill_dfifo(cs); in hfcsx_interrupt()
839 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
841 debugl1(cs, "hfcsx_fill_dfifo irq blocked"); in hfcsx_interrupt()
844 schedule_event(cs, D_XMTBUFREADY); in hfcsx_interrupt()
847 if (cs->hw.hfcsx.int_s1 && count--) { in hfcsx_interrupt()
848 val = cs->hw.hfcsx.int_s1; in hfcsx_interrupt()
849 cs->hw.hfcsx.int_s1 = 0; in hfcsx_interrupt()
850 if (cs->debug & L1_DEB_ISAC) in hfcsx_interrupt()
851 debugl1(cs, "HFC-SX irq %x loop %d", val, 15 - count); in hfcsx_interrupt()
855 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_interrupt()
863 hfcsx_dbusy_timer(struct IsdnCardState *cs) in hfcsx_dbusy_timer() argument
873 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; in HFCSX_l1hw() local
879 if (cs->debug & DEB_DLOG_HEX) in HFCSX_l1hw()
880 LogFrame(cs, skb->data, skb->len); in HFCSX_l1hw()
881 if (cs->debug & DEB_DLOG_VERBOSE) in HFCSX_l1hw()
882 dlogframe(cs, skb, 0); in HFCSX_l1hw()
883 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
884 if (cs->tx_skb) { in HFCSX_l1hw()
885 skb_queue_tail(&cs->sq, skb); in HFCSX_l1hw()
887 if (cs->debug & L1_DEB_LAPD) in HFCSX_l1hw()
888 Logl2Frame(cs, skb, "PH_DATA Queued", 0); in HFCSX_l1hw()
891 cs->tx_skb = skb; in HFCSX_l1hw()
892 cs->tx_cnt = 0; in HFCSX_l1hw()
894 if (cs->debug & L1_DEB_LAPD) in HFCSX_l1hw()
895 Logl2Frame(cs, skb, "PH_DATA", 0); in HFCSX_l1hw()
897 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in HFCSX_l1hw()
898 hfcsx_fill_dfifo(cs); in HFCSX_l1hw()
899 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in HFCSX_l1hw()
901 debugl1(cs, "hfcsx_fill_dfifo blocked"); in HFCSX_l1hw()
904 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
907 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
908 if (cs->tx_skb) { in HFCSX_l1hw()
909 if (cs->debug & L1_DEB_WARN) in HFCSX_l1hw()
910 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); in HFCSX_l1hw()
911 skb_queue_tail(&cs->sq, skb); in HFCSX_l1hw()
912 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
915 if (cs->debug & DEB_DLOG_HEX) in HFCSX_l1hw()
916 LogFrame(cs, skb->data, skb->len); in HFCSX_l1hw()
917 if (cs->debug & DEB_DLOG_VERBOSE) in HFCSX_l1hw()
918 dlogframe(cs, skb, 0); in HFCSX_l1hw()
919 cs->tx_skb = skb; in HFCSX_l1hw()
920 cs->tx_cnt = 0; in HFCSX_l1hw()
922 if (cs->debug & L1_DEB_LAPD) in HFCSX_l1hw()
923 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); in HFCSX_l1hw()
925 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in HFCSX_l1hw()
926 hfcsx_fill_dfifo(cs); in HFCSX_l1hw()
927 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in HFCSX_l1hw()
929 debugl1(cs, "hfcsx_fill_dfifo blocked"); in HFCSX_l1hw()
930 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
934 if (cs->debug & L1_DEB_LAPD) in HFCSX_l1hw()
935 debugl1(cs, "-> PH_REQUEST_PULL"); in HFCSX_l1hw()
937 if (!cs->tx_skb) { in HFCSX_l1hw()
944 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
945 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3); /* HFC ST 3 */ in HFCSX_l1hw()
947 Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */ in HFCSX_l1hw()
948 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; in HFCSX_l1hw()
949 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
950 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); in HFCSX_l1hw()
951 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
952 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); in HFCSX_l1hw()
955 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
956 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); in HFCSX_l1hw()
957 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
960 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
961 cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER; in HFCSX_l1hw()
962 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
963 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
966 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
967 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; in HFCSX_l1hw()
968 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
969 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
972 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
975 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* tx slot */ in HFCSX_l1hw()
976 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* rx slot */ in HFCSX_l1hw()
977 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1; in HFCSX_l1hw()
978 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in HFCSX_l1hw()
981 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* tx slot */ in HFCSX_l1hw()
982 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* rx slot */ in HFCSX_l1hw()
983 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08; in HFCSX_l1hw()
984 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in HFCSX_l1hw()
987 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
988 if (cs->debug & L1_DEB_WARN) in HFCSX_l1hw()
989 debugl1(cs, "hfcsx_l1hw loop invalid %4lx", (unsigned long)arg); in HFCSX_l1hw()
992 cs->hw.hfcsx.trm |= 0x80; /* enable IOM-loop */ in HFCSX_l1hw()
993 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in HFCSX_l1hw()
994 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
997 if (cs->debug & L1_DEB_WARN) in HFCSX_l1hw()
998 debugl1(cs, "hfcsx_l1hw unknown pr %4x", pr); in HFCSX_l1hw()
1007 setstack_hfcsx(struct PStack *st, struct IsdnCardState *cs) in setstack_hfcsx() argument
1018 struct IsdnCardState *cs = bcs->cs; in hfcsx_send_data() local
1020 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_send_data()
1022 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_send_data()
1024 debugl1(cs, "send_data %d blocked", bcs->channel); in hfcsx_send_data()
1033 struct IsdnCardState *cs = bcs->cs; in mode_hfcsx() local
1036 if (cs->debug & L1_DEB_HSCX) in mode_hfcsx()
1037 debugl1(cs, "HFCSX bchannel mode %d bchan %d/%d", in mode_hfcsx()
1042 if (cs->chanlimit > 1) { in mode_hfcsx()
1043 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcsx()
1044 cs->hw.hfcsx.sctrl_e &= ~0x80; in mode_hfcsx()
1048 cs->hw.hfcsx.bswapped = 1; /* B1 and B2 exchanged */ in mode_hfcsx()
1049 cs->hw.hfcsx.sctrl_e |= 0x80; in mode_hfcsx()
1051 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcsx()
1052 cs->hw.hfcsx.sctrl_e &= ~0x80; in mode_hfcsx()
1056 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcsx()
1057 cs->hw.hfcsx.sctrl_e &= ~0x80; in mode_hfcsx()
1063 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; in mode_hfcsx()
1064 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; in mode_hfcsx()
1066 cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA; in mode_hfcsx()
1067 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA; in mode_hfcsx()
1070 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1072 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1077 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; in mode_hfcsx()
1078 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; in mode_hfcsx()
1080 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; in mode_hfcsx()
1081 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; in mode_hfcsx()
1084 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1085 cs->hw.hfcsx.ctmt |= 2; in mode_hfcsx()
1086 cs->hw.hfcsx.conn &= ~0x18; in mode_hfcsx()
1088 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1089 cs->hw.hfcsx.ctmt |= 1; in mode_hfcsx()
1090 cs->hw.hfcsx.conn &= ~0x03; in mode_hfcsx()
1095 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; in mode_hfcsx()
1096 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; in mode_hfcsx()
1098 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; in mode_hfcsx()
1099 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; in mode_hfcsx()
1102 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1103 cs->hw.hfcsx.ctmt &= ~2; in mode_hfcsx()
1104 cs->hw.hfcsx.conn &= ~0x18; in mode_hfcsx()
1106 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1107 cs->hw.hfcsx.ctmt &= ~1; in mode_hfcsx()
1108 cs->hw.hfcsx.conn &= ~0x03; in mode_hfcsx()
1113 cs->hw.hfcsx.conn |= 0x10; in mode_hfcsx()
1114 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; in mode_hfcsx()
1115 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; in mode_hfcsx()
1116 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1118 cs->hw.hfcsx.conn |= 0x02; in mode_hfcsx()
1119 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; in mode_hfcsx()
1120 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; in mode_hfcsx()
1121 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1125 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); in mode_hfcsx()
1126 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in mode_hfcsx()
1127 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in mode_hfcsx()
1128 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in mode_hfcsx()
1129 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in mode_hfcsx()
1130 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in mode_hfcsx()
1132 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX); in mode_hfcsx()
1133 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX); in mode_hfcsx()
1149 spin_lock_irqsave(&bcs->cs->lock, flags); in hfcsx_l2l1()
1155 bcs->cs->BC_Send_Data(bcs); in hfcsx_l2l1()
1157 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfcsx_l2l1()
1160 spin_lock_irqsave(&bcs->cs->lock, flags); in hfcsx_l2l1()
1167 bcs->cs->BC_Send_Data(bcs); in hfcsx_l2l1()
1169 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfcsx_l2l1()
1179 spin_lock_irqsave(&bcs->cs->lock, flags); in hfcsx_l2l1()
1182 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfcsx_l2l1()
1189 spin_lock_irqsave(&bcs->cs->lock, flags); in hfcsx_l2l1()
1193 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfcsx_l2l1()
1221 open_hfcsxstate(struct IsdnCardState *cs, struct BCState *bcs) in open_hfcsxstate() argument
1257 struct IsdnCardState *cs = in hfcsx_bh() local
1261 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) { in hfcsx_bh()
1262 if (!cs->hw.hfcsx.nt_mode) in hfcsx_bh()
1263 switch (cs->dc.hfcsx.ph_state) { in hfcsx_bh()
1265 l1_msg(cs, HW_RESET | INDICATION, NULL); in hfcsx_bh()
1268 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); in hfcsx_bh()
1271 l1_msg(cs, HW_RSYNC | INDICATION, NULL); in hfcsx_bh()
1274 l1_msg(cs, HW_INFO2 | INDICATION, NULL); in hfcsx_bh()
1277 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); in hfcsx_bh()
1282 switch (cs->dc.hfcsx.ph_state) { in hfcsx_bh()
1284 spin_lock_irqsave(&cs->lock, flags); in hfcsx_bh()
1285 if (cs->hw.hfcsx.nt_timer < 0) { in hfcsx_bh()
1286 cs->hw.hfcsx.nt_timer = 0; in hfcsx_bh()
1287 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; in hfcsx_bh()
1288 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1290 if (Read_hfc(cs, HFCSX_INT_S1)); in hfcsx_bh()
1292 Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE); in hfcsx_bh()
1294 Write_hfc(cs, HFCSX_STATES, 4); in hfcsx_bh()
1295 cs->dc.hfcsx.ph_state = 4; in hfcsx_bh()
1297 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER; in hfcsx_bh()
1298 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1299 cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER; in hfcsx_bh()
1300 cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125; in hfcsx_bh()
1301 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_bh()
1302 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_bh()
1303 cs->hw.hfcsx.nt_timer = NT_T1_COUNT; in hfcsx_bh()
1304 Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3); /* allow G2 -> G3 transition */ in hfcsx_bh()
1306 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_bh()
1311 spin_lock_irqsave(&cs->lock, flags); in hfcsx_bh()
1312 cs->hw.hfcsx.nt_timer = 0; in hfcsx_bh()
1313 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; in hfcsx_bh()
1314 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1315 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_bh()
1322 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) in hfcsx_bh()
1323 DChannel_proc_rcv(cs); in hfcsx_bh()
1324 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) in hfcsx_bh()
1325 DChannel_proc_xmt(cs); in hfcsx_bh()
1332 static void inithfcsx(struct IsdnCardState *cs) in inithfcsx() argument
1334 cs->setstack_d = setstack_hfcsx; in inithfcsx()
1335 cs->BC_Send_Data = &hfcsx_send_data; in inithfcsx()
1336 cs->bcs[0].BC_SetStack = setstack_2b; in inithfcsx()
1337 cs->bcs[1].BC_SetStack = setstack_2b; in inithfcsx()
1338 cs->bcs[0].BC_Close = close_hfcsx; in inithfcsx()
1339 cs->bcs[1].BC_Close = close_hfcsx; in inithfcsx()
1340 mode_hfcsx(cs->bcs, 0, 0); in inithfcsx()
1341 mode_hfcsx(cs->bcs + 1, 0, 1); in inithfcsx()
1350 hfcsx_card_msg(struct IsdnCardState *cs, int mt, void *arg) in hfcsx_card_msg() argument
1354 if (cs->debug & L1_DEB_ISAC) in hfcsx_card_msg()
1355 debugl1(cs, "HFCSX: card_msg %x", mt); in hfcsx_card_msg()
1358 spin_lock_irqsave(&cs->lock, flags); in hfcsx_card_msg()
1359 reset_hfcsx(cs); in hfcsx_card_msg()
1360 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_card_msg()
1363 release_io_hfcsx(cs); in hfcsx_card_msg()
1366 spin_lock_irqsave(&cs->lock, flags); in hfcsx_card_msg()
1367 inithfcsx(cs); in hfcsx_card_msg()
1368 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_card_msg()
1371 spin_lock_irqsave(&cs->lock, flags); in hfcsx_card_msg()
1372 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; in hfcsx_card_msg()
1373 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_card_msg()
1375 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in hfcsx_card_msg()
1376 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_card_msg()
1398 struct IsdnCardState *cs = card->cs; in setup_hfcsx() local
1445 cs->hw.hfcsx.base = card->para[1] & 0xfffe; in setup_hfcsx()
1446 cs->irq = card->para[0]; in setup_hfcsx()
1447 cs->hw.hfcsx.int_s1 = 0; in setup_hfcsx()
1448 cs->dc.hfcsx.ph_state = 0; in setup_hfcsx()
1449 cs->hw.hfcsx.fifo = 255; in setup_hfcsx()
1450 if ((cs->typ == ISDN_CTYPE_HFC_SX) || in setup_hfcsx()
1451 (cs->typ == ISDN_CTYPE_HFC_SP_PCMCIA)) { in setup_hfcsx()
1452 if ((!cs->hw.hfcsx.base) || !request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn")) { in setup_hfcsx()
1455 cs->hw.hfcsx.base); in setup_hfcsx()
1458 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF); in setup_hfcsx()
1459 byteout(cs->hw.hfcsx.base + 1, in setup_hfcsx()
1460 ((cs->hw.hfcsx.base >> 8) & 3) | 0x54); in setup_hfcsx()
1462 cs->hw.hfcsx.chip = Read_hfc(cs, HFCSX_CHIP_ID); in setup_hfcsx()
1463 switch (cs->hw.hfcsx.chip >> 4) { in setup_hfcsx()
1473 cs->hw.hfcsx.chip >> 4); in setup_hfcsx()
1474 release_region(cs->hw.hfcsx.base, 2); in setup_hfcsx()
1477 if (!ccd_sp_irqtab[cs->irq & 0xF]) { in setup_hfcsx()
1479 "HFC_SX: invalid irq %d specified\n", cs->irq & 0xF); in setup_hfcsx()
1480 release_region(cs->hw.hfcsx.base, 2); in setup_hfcsx()
1483 if (!(cs->hw.hfcsx.extra = in setup_hfcsx()
1485 release_region(cs->hw.hfcsx.base, 2); in setup_hfcsx()
1490 tmp[0], (u_int) cs->hw.hfcsx.base, cs->irq, HZ); in setup_hfcsx()
1491 cs->hw.hfcsx.int_m2 = 0; /* disable alle interrupts */ in setup_hfcsx()
1492 cs->hw.hfcsx.int_m1 = 0; in setup_hfcsx()
1493 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in setup_hfcsx()
1494 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in setup_hfcsx()
1498 cs->dbusytimer.function = (void *) hfcsx_dbusy_timer; in setup_hfcsx()
1499 cs->dbusytimer.data = (long) cs; in setup_hfcsx()
1500 init_timer(&cs->dbusytimer); in setup_hfcsx()
1501 INIT_WORK(&cs->tqueue, hfcsx_bh); in setup_hfcsx()
1502 cs->readisac = NULL; in setup_hfcsx()
1503 cs->writeisac = NULL; in setup_hfcsx()
1504 cs->readisacfifo = NULL; in setup_hfcsx()
1505 cs->writeisacfifo = NULL; in setup_hfcsx()
1506 cs->BC_Read_Reg = NULL; in setup_hfcsx()
1507 cs->BC_Write_Reg = NULL; in setup_hfcsx()
1508 cs->irq_func = &hfcsx_interrupt; in setup_hfcsx()
1510 cs->hw.hfcsx.timer.function = (void *) hfcsx_Timer; in setup_hfcsx()
1511 cs->hw.hfcsx.timer.data = (long) cs; in setup_hfcsx()
1512 cs->hw.hfcsx.b_fifo_size = 0; /* fifo size still unknown */ in setup_hfcsx()
1513 cs->hw.hfcsx.cirm = ccd_sp_irqtab[cs->irq & 0xF]; /* RAM not evaluated */ in setup_hfcsx()
1514 init_timer(&cs->hw.hfcsx.timer); in setup_hfcsx()
1516 reset_hfcsx(cs); in setup_hfcsx()
1517 cs->cardmsg = &hfcsx_card_msg; in setup_hfcsx()
1518 cs->auxcmd = &hfcsx_auxcmd; in setup_hfcsx()