1/*
2 * Copyright (C) 2006-2007 PA Semi, Inc
3 *
4 * Author: Egor Martovetsky <egor@pasemi.com>
5 * Maintained by: Olof Johansson <olof@lixom.net>
6 *
7 * Driver for the PWRficient onchip memory controllers
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
21 */
22
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/pci.h>
27#include <linux/pci_ids.h>
28#include <linux/edac.h>
29#include "edac_core.h"
30
31#define MODULE_NAME "pasemi_edac"
32
33#define MCCFG_MCEN				0x300
34#define   MCCFG_MCEN_MMC_EN			0x00000001
35#define MCCFG_ERRCOR				0x388
36#define   MCCFG_ERRCOR_RNK_FAIL_DET_EN		0x00000100
37#define   MCCFG_ERRCOR_ECC_GEN_EN		0x00000010
38#define   MCCFG_ERRCOR_ECC_CRR_EN		0x00000001
39#define MCCFG_SCRUB				0x384
40#define   MCCFG_SCRUB_RGLR_SCRB_EN		0x00000001
41#define MCDEBUG_ERRCTL1				0x728
42#define   MCDEBUG_ERRCTL1_RFL_LOG_EN		0x00080000
43#define   MCDEBUG_ERRCTL1_MBE_LOG_EN		0x00040000
44#define   MCDEBUG_ERRCTL1_SBE_LOG_EN		0x00020000
45#define MCDEBUG_ERRSTA				0x730
46#define   MCDEBUG_ERRSTA_RFL_STATUS		0x00000004
47#define   MCDEBUG_ERRSTA_MBE_STATUS		0x00000002
48#define   MCDEBUG_ERRSTA_SBE_STATUS		0x00000001
49#define MCDEBUG_ERRCNT1				0x734
50#define   MCDEBUG_ERRCNT1_SBE_CNT_OVRFLO	0x00000080
51#define MCDEBUG_ERRLOG1A			0x738
52#define   MCDEBUG_ERRLOG1A_MERR_TYPE_M		0x30000000
53#define   MCDEBUG_ERRLOG1A_MERR_TYPE_NONE	0x00000000
54#define   MCDEBUG_ERRLOG1A_MERR_TYPE_SBE	0x10000000
55#define   MCDEBUG_ERRLOG1A_MERR_TYPE_MBE	0x20000000
56#define   MCDEBUG_ERRLOG1A_MERR_TYPE_RFL	0x30000000
57#define   MCDEBUG_ERRLOG1A_MERR_BA_M		0x00700000
58#define   MCDEBUG_ERRLOG1A_MERR_BA_S		20
59#define   MCDEBUG_ERRLOG1A_MERR_CS_M		0x00070000
60#define   MCDEBUG_ERRLOG1A_MERR_CS_S		16
61#define   MCDEBUG_ERRLOG1A_SYNDROME_M		0x0000ffff
62#define MCDRAM_RANKCFG				0x114
63#define   MCDRAM_RANKCFG_EN			0x00000001
64#define   MCDRAM_RANKCFG_TYPE_SIZE_M		0x000001c0
65#define   MCDRAM_RANKCFG_TYPE_SIZE_S		6
66
67#define PASEMI_EDAC_NR_CSROWS			8
68#define PASEMI_EDAC_NR_CHANS			1
69#define PASEMI_EDAC_ERROR_GRAIN			64
70
71static int last_page_in_mmc;
72static int system_mmc_id;
73
74
75static u32 pasemi_edac_get_error_info(struct mem_ctl_info *mci)
76{
77	struct pci_dev *pdev = to_pci_dev(mci->pdev);
78	u32 tmp;
79
80	pci_read_config_dword(pdev, MCDEBUG_ERRSTA,
81			      &tmp);
82
83	tmp &= (MCDEBUG_ERRSTA_RFL_STATUS | MCDEBUG_ERRSTA_MBE_STATUS
84		| MCDEBUG_ERRSTA_SBE_STATUS);
85
86	if (tmp) {
87		if (tmp & MCDEBUG_ERRSTA_SBE_STATUS)
88			pci_write_config_dword(pdev, MCDEBUG_ERRCNT1,
89					       MCDEBUG_ERRCNT1_SBE_CNT_OVRFLO);
90		pci_write_config_dword(pdev, MCDEBUG_ERRSTA, tmp);
91	}
92
93	return tmp;
94}
95
96static void pasemi_edac_process_error_info(struct mem_ctl_info *mci, u32 errsta)
97{
98	struct pci_dev *pdev = to_pci_dev(mci->pdev);
99	u32 errlog1a;
100	u32 cs;
101
102	if (!errsta)
103		return;
104
105	pci_read_config_dword(pdev, MCDEBUG_ERRLOG1A, &errlog1a);
106
107	cs = (errlog1a & MCDEBUG_ERRLOG1A_MERR_CS_M) >>
108		MCDEBUG_ERRLOG1A_MERR_CS_S;
109
110	/* uncorrectable/multi-bit errors */
111	if (errsta & (MCDEBUG_ERRSTA_MBE_STATUS |
112		      MCDEBUG_ERRSTA_RFL_STATUS)) {
113		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
114				     mci->csrows[cs]->first_page, 0, 0,
115				     cs, 0, -1, mci->ctl_name, "");
116	}
117
118	/* correctable/single-bit errors */
119	if (errsta & MCDEBUG_ERRSTA_SBE_STATUS)
120		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
121				     mci->csrows[cs]->first_page, 0, 0,
122				     cs, 0, -1, mci->ctl_name, "");
123}
124
125static void pasemi_edac_check(struct mem_ctl_info *mci)
126{
127	u32 errsta;
128
129	errsta = pasemi_edac_get_error_info(mci);
130	if (errsta)
131		pasemi_edac_process_error_info(mci, errsta);
132}
133
134static int pasemi_edac_init_csrows(struct mem_ctl_info *mci,
135				   struct pci_dev *pdev,
136				   enum edac_type edac_mode)
137{
138	struct csrow_info *csrow;
139	struct dimm_info *dimm;
140	u32 rankcfg;
141	int index;
142
143	for (index = 0; index < mci->nr_csrows; index++) {
144		csrow = mci->csrows[index];
145		dimm = csrow->channels[0]->dimm;
146
147		pci_read_config_dword(pdev,
148				      MCDRAM_RANKCFG + (index * 12),
149				      &rankcfg);
150
151		if (!(rankcfg & MCDRAM_RANKCFG_EN))
152			continue;
153
154		switch ((rankcfg & MCDRAM_RANKCFG_TYPE_SIZE_M) >>
155			MCDRAM_RANKCFG_TYPE_SIZE_S) {
156		case 0:
157			dimm->nr_pages = 128 << (20 - PAGE_SHIFT);
158			break;
159		case 1:
160			dimm->nr_pages = 256 << (20 - PAGE_SHIFT);
161			break;
162		case 2:
163		case 3:
164			dimm->nr_pages = 512 << (20 - PAGE_SHIFT);
165			break;
166		case 4:
167			dimm->nr_pages = 1024 << (20 - PAGE_SHIFT);
168			break;
169		case 5:
170			dimm->nr_pages = 2048 << (20 - PAGE_SHIFT);
171			break;
172		default:
173			edac_mc_printk(mci, KERN_ERR,
174				"Unrecognized Rank Config. rankcfg=%u\n",
175				rankcfg);
176			return -EINVAL;
177		}
178
179		csrow->first_page = last_page_in_mmc;
180		csrow->last_page = csrow->first_page + dimm->nr_pages - 1;
181		last_page_in_mmc += dimm->nr_pages;
182		csrow->page_mask = 0;
183		dimm->grain = PASEMI_EDAC_ERROR_GRAIN;
184		dimm->mtype = MEM_DDR;
185		dimm->dtype = DEV_UNKNOWN;
186		dimm->edac_mode = edac_mode;
187	}
188	return 0;
189}
190
191static int pasemi_edac_probe(struct pci_dev *pdev,
192			     const struct pci_device_id *ent)
193{
194	struct mem_ctl_info *mci = NULL;
195	struct edac_mc_layer layers[2];
196	u32 errctl1, errcor, scrub, mcen;
197
198	pci_read_config_dword(pdev, MCCFG_MCEN, &mcen);
199	if (!(mcen & MCCFG_MCEN_MMC_EN))
200		return -ENODEV;
201
202	/*
203	 * We should think about enabling other error detection later on
204	 */
205
206	pci_read_config_dword(pdev, MCDEBUG_ERRCTL1, &errctl1);
207	errctl1 |= MCDEBUG_ERRCTL1_SBE_LOG_EN |
208		MCDEBUG_ERRCTL1_MBE_LOG_EN |
209		MCDEBUG_ERRCTL1_RFL_LOG_EN;
210	pci_write_config_dword(pdev, MCDEBUG_ERRCTL1, errctl1);
211
212	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
213	layers[0].size = PASEMI_EDAC_NR_CSROWS;
214	layers[0].is_virt_csrow = true;
215	layers[1].type = EDAC_MC_LAYER_CHANNEL;
216	layers[1].size = PASEMI_EDAC_NR_CHANS;
217	layers[1].is_virt_csrow = false;
218	mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers,
219			    0);
220	if (mci == NULL)
221		return -ENOMEM;
222
223	pci_read_config_dword(pdev, MCCFG_ERRCOR, &errcor);
224	errcor |= MCCFG_ERRCOR_RNK_FAIL_DET_EN |
225		MCCFG_ERRCOR_ECC_GEN_EN |
226		MCCFG_ERRCOR_ECC_CRR_EN;
227
228	mci->pdev = &pdev->dev;
229	mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR;
230	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
231	mci->edac_cap = (errcor & MCCFG_ERRCOR_ECC_GEN_EN) ?
232		((errcor & MCCFG_ERRCOR_ECC_CRR_EN) ?
233		 (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_EC) :
234		EDAC_FLAG_NONE;
235	mci->mod_name = MODULE_NAME;
236	mci->dev_name = pci_name(pdev);
237	mci->ctl_name = "pasemi,pwrficient-mc";
238	mci->edac_check = pasemi_edac_check;
239	mci->ctl_page_to_phys = NULL;
240	pci_read_config_dword(pdev, MCCFG_SCRUB, &scrub);
241	mci->scrub_cap = SCRUB_FLAG_HW_PROG | SCRUB_FLAG_HW_SRC;
242	mci->scrub_mode =
243		((errcor & MCCFG_ERRCOR_ECC_CRR_EN) ? SCRUB_FLAG_HW_SRC : 0) |
244		((scrub & MCCFG_SCRUB_RGLR_SCRB_EN) ? SCRUB_FLAG_HW_PROG : 0);
245
246	if (pasemi_edac_init_csrows(mci, pdev,
247				    (mci->edac_cap & EDAC_FLAG_SECDED) ?
248				    EDAC_SECDED :
249				    ((mci->edac_cap & EDAC_FLAG_EC) ?
250				     EDAC_EC : EDAC_NONE)))
251		goto fail;
252
253	/*
254	 * Clear status
255	 */
256	pasemi_edac_get_error_info(mci);
257
258	if (edac_mc_add_mc(mci))
259		goto fail;
260
261	/* get this far and it's successful */
262	return 0;
263
264fail:
265	edac_mc_free(mci);
266	return -ENODEV;
267}
268
269static void pasemi_edac_remove(struct pci_dev *pdev)
270{
271	struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev);
272
273	if (!mci)
274		return;
275
276	edac_mc_free(mci);
277}
278
279
280static const struct pci_device_id pasemi_edac_pci_tbl[] = {
281	{ PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa00a) },
282	{ }
283};
284
285MODULE_DEVICE_TABLE(pci, pasemi_edac_pci_tbl);
286
287static struct pci_driver pasemi_edac_driver = {
288	.name = MODULE_NAME,
289	.probe = pasemi_edac_probe,
290	.remove = pasemi_edac_remove,
291	.id_table = pasemi_edac_pci_tbl,
292};
293
294static int __init pasemi_edac_init(void)
295{
296       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
297       opstate_init();
298
299	return pci_register_driver(&pasemi_edac_driver);
300}
301
302static void __exit pasemi_edac_exit(void)
303{
304	pci_unregister_driver(&pasemi_edac_driver);
305}
306
307module_init(pasemi_edac_init);
308module_exit(pasemi_edac_exit);
309
310MODULE_LICENSE("GPL");
311MODULE_AUTHOR("Egor Martovetsky <egor@pasemi.com>");
312MODULE_DESCRIPTION("MC support for PA Semi PWRficient memory controller");
313module_param(edac_op_state, int, 0444);
314MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
315
316