Lines Matching refs:cs
29 dummyf(struct IsdnCardState *cs, u_char *data, int size) in dummyf() argument
35 ReadReg(struct IsdnCardState *cs, int data, u_char reg) in ReadReg() argument
40 if (cs->hw.hfcD.cip != reg) { in ReadReg()
41 cs->hw.hfcD.cip = reg; in ReadReg()
42 byteout(cs->hw.hfcD.addr | 1, reg); in ReadReg()
44 ret = bytein(cs->hw.hfcD.addr); in ReadReg()
46 if (cs->debug & L1_DEB_HSCX_FIFO && (data != 2)) in ReadReg()
47 debugl1(cs, "t3c RD %02x %02x", reg, ret); in ReadReg()
50 ret = bytein(cs->hw.hfcD.addr | 1); in ReadReg()
55 WriteReg(struct IsdnCardState *cs, int data, u_char reg, u_char value) in WriteReg() argument
57 if (cs->hw.hfcD.cip != reg) { in WriteReg()
58 cs->hw.hfcD.cip = reg; in WriteReg()
59 byteout(cs->hw.hfcD.addr | 1, reg); in WriteReg()
62 byteout(cs->hw.hfcD.addr, value); in WriteReg()
64 if (cs->debug & L1_DEB_HSCX_FIFO && (data != HFCD_DATA_NODEB)) in WriteReg()
65 debugl1(cs, "t3c W%c %02x %02x", data ? 'D' : 'C', reg, value); in WriteReg()
72 readreghfcd(struct IsdnCardState *cs, u_char offset) in readreghfcd() argument
74 return (ReadReg(cs, HFCD_DATA, offset)); in readreghfcd()
78 writereghfcd(struct IsdnCardState *cs, u_char offset, u_char value) in writereghfcd() argument
80 WriteReg(cs, HFCD_DATA, offset, value); in writereghfcd()
84 WaitForBusy(struct IsdnCardState *cs) in WaitForBusy() argument
88 while (!(ReadReg(cs, HFCD_DATA, HFCD_STAT) & HFCD_BUSY) && to) { in WaitForBusy()
98 WaitNoBusy(struct IsdnCardState *cs) in WaitNoBusy() argument
102 while ((ReadReg(cs, HFCD_STATUS, HFCD_STATUS) & HFCD_BUSY) && to) { in WaitNoBusy()
112 SelFiFo(struct IsdnCardState *cs, u_char FiFo) in SelFiFo() argument
116 if (cs->hw.hfcD.fifo == FiFo) in SelFiFo()
132 debugl1(cs, "SelFiFo Error"); in SelFiFo()
135 cs->hw.hfcD.fifo = FiFo; in SelFiFo()
136 WaitNoBusy(cs); in SelFiFo()
137 cs->BC_Write_Reg(cs, HFCD_DATA, cip, 0); in SelFiFo()
138 WaitForBusy(cs); in SelFiFo()
148 return (bcs->cs->hw.hfcD.bfifosize); in GetFreeFifoBytes_B()
151 s += bcs->cs->hw.hfcD.bfifosize; in GetFreeFifoBytes_B()
152 s = bcs->cs->hw.hfcD.bfifosize - s; in GetFreeFifoBytes_B()
157 GetFreeFifoBytes_D(struct IsdnCardState *cs) in GetFreeFifoBytes_D() argument
161 if (cs->hw.hfcD.f1 == cs->hw.hfcD.f2) in GetFreeFifoBytes_D()
162 return (cs->hw.hfcD.dfifosize); in GetFreeFifoBytes_D()
163 s = cs->hw.hfcD.send[cs->hw.hfcD.f1] - cs->hw.hfcD.send[cs->hw.hfcD.f2]; in GetFreeFifoBytes_D()
165 s += cs->hw.hfcD.dfifosize; in GetFreeFifoBytes_D()
166 s = cs->hw.hfcD.dfifosize - s; in GetFreeFifoBytes_D()
171 ReadZReg(struct IsdnCardState *cs, u_char reg) in ReadZReg() argument
175 WaitNoBusy(cs); in ReadZReg()
176 val = 256 * ReadReg(cs, HFCD_DATA, reg | HFCB_Z_HIGH); in ReadZReg()
177 WaitNoBusy(cs); in ReadZReg()
178 val += ReadReg(cs, HFCD_DATA, reg | HFCB_Z_LOW); in ReadZReg()
187 struct IsdnCardState *cs = bcs->cs; in hfc_empty_fifo() local
192 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) in hfc_empty_fifo()
193 debugl1(cs, "hfc_empty_fifo"); in hfc_empty_fifo()
196 if (cs->debug & L1_DEB_WARN) in hfc_empty_fifo()
197 debugl1(cs, "hfc_empty_fifo: incoming packet too large"); in hfc_empty_fifo()
200 WaitNoBusy(cs); in hfc_empty_fifo()
201 ReadReg(cs, HFCD_DATA_NODEB, cip); in hfc_empty_fifo()
205 if (cs->debug & L1_DEB_WARN) in hfc_empty_fifo()
206 debugl1(cs, "hfc_empty_fifo: incoming packet too small"); in hfc_empty_fifo()
211 while ((idx++ < count) && WaitNoBusy(cs)) in hfc_empty_fifo()
212 ReadReg(cs, HFCD_DATA_NODEB, cip); in hfc_empty_fifo()
221 if (!WaitNoBusy(cs)) in hfc_empty_fifo()
223 *ptr = ReadReg(cs, HFCD_DATA_NODEB, cip); in hfc_empty_fifo()
228 debugl1(cs, "RFIFO BUSY error"); in hfc_empty_fifo()
233 WaitNoBusy(cs); in hfc_empty_fifo()
234 chksum = (ReadReg(cs, HFCD_DATA, cip) << 8); in hfc_empty_fifo()
235 WaitNoBusy(cs); in hfc_empty_fifo()
236 chksum += ReadReg(cs, HFCD_DATA, cip); in hfc_empty_fifo()
237 WaitNoBusy(cs); in hfc_empty_fifo()
238 stat = ReadReg(cs, HFCD_DATA, cip); in hfc_empty_fifo()
239 if (cs->debug & L1_DEB_HSCX) in hfc_empty_fifo()
240 debugl1(cs, "hfc_empty_fifo %d chksum %x stat %x", in hfc_empty_fifo()
243 debugl1(cs, "FIFO CRC error"); in hfc_empty_fifo()
252 WaitForBusy(cs); in hfc_empty_fifo()
253 WaitNoBusy(cs); in hfc_empty_fifo()
254 stat = ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F2_INC | in hfc_empty_fifo()
256 WaitForBusy(cs); in hfc_empty_fifo()
263 struct IsdnCardState *cs = bcs->cs; in hfc_fill_fifo() local
272 SelFiFo(cs, HFCB_SEND | HFCB_CHANNEL(bcs->channel)); in hfc_fill_fifo()
274 WaitNoBusy(cs); in hfc_fill_fifo()
275 bcs->hw.hfc.f1 = ReadReg(cs, HFCD_DATA, cip); in hfc_fill_fifo()
276 WaitNoBusy(cs); in hfc_fill_fifo()
278 WaitNoBusy(cs); in hfc_fill_fifo()
279 bcs->hw.hfc.f2 = ReadReg(cs, HFCD_DATA, cip); in hfc_fill_fifo()
280 …bcs->hw.hfc.send[bcs->hw.hfc.f1] = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_SEND | HFCB_CHANNEL(bcs… in hfc_fill_fifo()
281 if (cs->debug & L1_DEB_HSCX) in hfc_fill_fifo()
282 debugl1(cs, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)", in hfc_fill_fifo()
289 if (cs->debug & L1_DEB_HSCX) in hfc_fill_fifo()
290 debugl1(cs, "hfc_fill_fifo more as 30 frames"); in hfc_fill_fifo()
294 if (cs->debug & L1_DEB_HSCX) in hfc_fill_fifo()
295 debugl1(cs, "hfc_fill_fifo %d count(%u/%d),%lx", in hfc_fill_fifo()
299 if (cs->debug & L1_DEB_HSCX) in hfc_fill_fifo()
300 debugl1(cs, "hfc_fill_fifo no fifo mem"); in hfc_fill_fifo()
305 WaitForBusy(cs); in hfc_fill_fifo()
306 WaitNoBusy(cs); in hfc_fill_fifo()
307 WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx++]); in hfc_fill_fifo()
309 if (!WaitNoBusy(cs)) in hfc_fill_fifo()
311 WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx]); in hfc_fill_fifo()
315 debugl1(cs, "FIFO Send BUSY error"); in hfc_fill_fifo()
330 WaitForBusy(cs); in hfc_fill_fifo()
331 WaitNoBusy(cs); in hfc_fill_fifo()
332 ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F1_INC | HFCB_SEND | HFCB_CHANNEL(bcs->channel)); in hfc_fill_fifo()
333 WaitForBusy(cs); in hfc_fill_fifo()
341 struct IsdnCardState *cs = bcs->cs; in hfc_send_data() local
343 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfc_send_data()
345 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfc_send_data()
347 debugl1(cs, "send_data %d blocked", bcs->channel); in hfc_send_data()
353 struct IsdnCardState *cs = bcs->cs; in main_rec_2bds0() local
361 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in main_rec_2bds0()
362 debugl1(cs, "rec_data %d blocked", bcs->channel); in main_rec_2bds0()
365 SelFiFo(cs, HFCB_REC | HFCB_CHANNEL(bcs->channel)); in main_rec_2bds0()
367 WaitNoBusy(cs); in main_rec_2bds0()
368 f1 = ReadReg(cs, HFCD_DATA, cip); in main_rec_2bds0()
370 WaitNoBusy(cs); in main_rec_2bds0()
371 f2 = ReadReg(cs, HFCD_DATA, cip); in main_rec_2bds0()
373 if (cs->debug & L1_DEB_HSCX) in main_rec_2bds0()
374 debugl1(cs, "hfc rec %d f1(%d) f2(%d)", in main_rec_2bds0()
376 z1 = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_REC | HFCB_CHANNEL(bcs->channel)); in main_rec_2bds0()
377 z2 = ReadZReg(cs, HFCB_FIFO | HFCB_Z2 | HFCB_REC | HFCB_CHANNEL(bcs->channel)); in main_rec_2bds0()
380 rcnt += cs->hw.hfcD.bfifosize; in main_rec_2bds0()
382 if (cs->debug & L1_DEB_HSCX) in main_rec_2bds0()
383 debugl1(cs, "hfc rec %d z1(%x) z2(%x) cnt(%d)", in main_rec_2bds0()
398 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in main_rec_2bds0()
407 struct IsdnCardState *cs = bcs->cs; in mode_2bs0() local
409 if (cs->debug & L1_DEB_HSCX) in mode_2bs0()
410 debugl1(cs, "HFCD bchannel mode %d bchan %d/%d", in mode_2bs0()
417 cs->hw.hfcD.conn |= 0x18; in mode_2bs0()
418 cs->hw.hfcD.sctrl &= ~SCTRL_B2_ENA; in mode_2bs0()
420 cs->hw.hfcD.conn |= 0x3; in mode_2bs0()
421 cs->hw.hfcD.sctrl &= ~SCTRL_B1_ENA; in mode_2bs0()
426 cs->hw.hfcD.ctmt |= 2; in mode_2bs0()
427 cs->hw.hfcD.conn &= ~0x18; in mode_2bs0()
428 cs->hw.hfcD.sctrl |= SCTRL_B2_ENA; in mode_2bs0()
430 cs->hw.hfcD.ctmt |= 1; in mode_2bs0()
431 cs->hw.hfcD.conn &= ~0x3; in mode_2bs0()
432 cs->hw.hfcD.sctrl |= SCTRL_B1_ENA; in mode_2bs0()
437 cs->hw.hfcD.ctmt &= ~2; in mode_2bs0()
438 cs->hw.hfcD.conn &= ~0x18; in mode_2bs0()
439 cs->hw.hfcD.sctrl |= SCTRL_B2_ENA; in mode_2bs0()
441 cs->hw.hfcD.ctmt &= ~1; in mode_2bs0()
442 cs->hw.hfcD.conn &= ~0x3; in mode_2bs0()
443 cs->hw.hfcD.sctrl |= SCTRL_B1_ENA; in mode_2bs0()
447 WriteReg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl); in mode_2bs0()
448 WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); in mode_2bs0()
449 WriteReg(cs, HFCD_DATA, HFCD_CONN, cs->hw.hfcD.conn); in mode_2bs0()
461 spin_lock_irqsave(&bcs->cs->lock, flags); in hfc_l2l1()
467 bcs->cs->BC_Send_Data(bcs); in hfc_l2l1()
469 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfc_l2l1()
472 spin_lock_irqsave(&bcs->cs->lock, flags); in hfc_l2l1()
478 bcs->cs->BC_Send_Data(bcs); in hfc_l2l1()
480 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfc_l2l1()
490 spin_lock_irqsave(&bcs->cs->lock, flags); in hfc_l2l1()
493 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfc_l2l1()
500 spin_lock_irqsave(&bcs->cs->lock, flags); in hfc_l2l1()
504 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfc_l2l1()
526 open_hfcstate(struct IsdnCardState *cs, struct BCState *bcs) in open_hfcstate() argument
556 struct IsdnCardState *cs = in hfcd_bh() local
559 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) { in hfcd_bh()
560 switch (cs->dc.hfcd.ph_state) { in hfcd_bh()
562 l1_msg(cs, HW_RESET | INDICATION, NULL); in hfcd_bh()
565 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); in hfcd_bh()
568 l1_msg(cs, HW_RSYNC | INDICATION, NULL); in hfcd_bh()
571 l1_msg(cs, HW_INFO2 | INDICATION, NULL); in hfcd_bh()
574 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); in hfcd_bh()
580 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) in hfcd_bh()
581 DChannel_proc_rcv(cs); in hfcd_bh()
582 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) in hfcd_bh()
583 DChannel_proc_xmt(cs); in hfcd_bh()
587 int receive_dmsg(struct IsdnCardState *cs) in receive_dmsg() argument
597 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in receive_dmsg()
598 debugl1(cs, "rec_dmsg blocked"); in receive_dmsg()
601 SelFiFo(cs, 4 | HFCD_REC); in receive_dmsg()
603 WaitNoBusy(cs); in receive_dmsg()
604 f1 = cs->readisac(cs, cip) & 0xf; in receive_dmsg()
606 WaitNoBusy(cs); in receive_dmsg()
607 f2 = cs->readisac(cs, cip) & 0xf; in receive_dmsg()
609 z1 = ReadZReg(cs, HFCD_FIFO | HFCD_Z1 | HFCD_REC); in receive_dmsg()
610 z2 = ReadZReg(cs, HFCD_FIFO | HFCD_Z2 | HFCD_REC); in receive_dmsg()
613 rcnt += cs->hw.hfcD.dfifosize; in receive_dmsg()
615 if (cs->debug & L1_DEB_ISAC) in receive_dmsg()
616 debugl1(cs, "hfcd recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)", in receive_dmsg()
621 if (cs->debug & L1_DEB_WARN) in receive_dmsg()
622 debugl1(cs, "empty_fifo d: incoming packet too large"); in receive_dmsg()
624 if (!(WaitNoBusy(cs))) in receive_dmsg()
626 ReadReg(cs, HFCD_DATA_NODEB, cip); in receive_dmsg()
630 if (cs->debug & L1_DEB_WARN) in receive_dmsg()
631 debugl1(cs, "empty_fifo d: incoming packet too small"); in receive_dmsg()
632 while ((idx++ < rcnt) && WaitNoBusy(cs)) in receive_dmsg()
633 ReadReg(cs, HFCD_DATA_NODEB, cip); in receive_dmsg()
637 if (!(WaitNoBusy(cs))) in receive_dmsg()
639 *ptr = ReadReg(cs, HFCD_DATA_NODEB, cip); in receive_dmsg()
644 debugl1(cs, "RFIFO D BUSY error"); in receive_dmsg()
649 cs->err_rx++; in receive_dmsg()
652 WaitNoBusy(cs); in receive_dmsg()
653 chksum = (ReadReg(cs, HFCD_DATA, cip) << 8); in receive_dmsg()
654 WaitNoBusy(cs); in receive_dmsg()
655 chksum += ReadReg(cs, HFCD_DATA, cip); in receive_dmsg()
656 WaitNoBusy(cs); in receive_dmsg()
657 stat = ReadReg(cs, HFCD_DATA, cip); in receive_dmsg()
658 if (cs->debug & L1_DEB_ISAC) in receive_dmsg()
659 debugl1(cs, "empty_dfifo chksum %x stat %x", in receive_dmsg()
662 debugl1(cs, "FIFO CRC error"); in receive_dmsg()
666 cs->err_crc++; in receive_dmsg()
669 skb_queue_tail(&cs->rq, skb); in receive_dmsg()
670 schedule_event(cs, D_RCVBUFREADY); in receive_dmsg()
675 WaitForBusy(cs); in receive_dmsg()
677 WaitNoBusy(cs); in receive_dmsg()
678 stat = ReadReg(cs, HFCD_DATA, cip); in receive_dmsg()
679 WaitForBusy(cs); in receive_dmsg()
681 WaitNoBusy(cs); in receive_dmsg()
682 f2 = cs->readisac(cs, cip) & 0xf; in receive_dmsg()
684 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in receive_dmsg()
689 hfc_fill_dfifo(struct IsdnCardState *cs) in hfc_fill_dfifo() argument
695 if (!cs->tx_skb) in hfc_fill_dfifo()
697 if (cs->tx_skb->len <= 0) in hfc_fill_dfifo()
700 SelFiFo(cs, 4 | HFCD_SEND); in hfc_fill_dfifo()
702 WaitNoBusy(cs); in hfc_fill_dfifo()
703 cs->hw.hfcD.f1 = ReadReg(cs, HFCD_DATA, cip) & 0xf; in hfc_fill_dfifo()
704 WaitNoBusy(cs); in hfc_fill_dfifo()
706 cs->hw.hfcD.f2 = ReadReg(cs, HFCD_DATA, cip) & 0xf; in hfc_fill_dfifo()
707 cs->hw.hfcD.send[cs->hw.hfcD.f1] = ReadZReg(cs, HFCD_FIFO | HFCD_Z1 | HFCD_SEND); in hfc_fill_dfifo()
708 if (cs->debug & L1_DEB_ISAC) in hfc_fill_dfifo()
709 debugl1(cs, "hfc_fill_Dfifo f1(%d) f2(%d) z1(%x)", in hfc_fill_dfifo()
710 cs->hw.hfcD.f1, cs->hw.hfcD.f2, in hfc_fill_dfifo()
711 cs->hw.hfcD.send[cs->hw.hfcD.f1]); in hfc_fill_dfifo()
712 fcnt = cs->hw.hfcD.f1 - cs->hw.hfcD.f2; in hfc_fill_dfifo()
716 if (cs->debug & L1_DEB_HSCX) in hfc_fill_dfifo()
717 debugl1(cs, "hfc_fill_Dfifo more as 14 frames"); in hfc_fill_dfifo()
720 count = GetFreeFifoBytes_D(cs); in hfc_fill_dfifo()
721 if (cs->debug & L1_DEB_ISAC) in hfc_fill_dfifo()
722 debugl1(cs, "hfc_fill_Dfifo count(%u/%d)", in hfc_fill_dfifo()
723 cs->tx_skb->len, count); in hfc_fill_dfifo()
724 if (count < cs->tx_skb->len) { in hfc_fill_dfifo()
725 if (cs->debug & L1_DEB_ISAC) in hfc_fill_dfifo()
726 debugl1(cs, "hfc_fill_Dfifo no fifo mem"); in hfc_fill_dfifo()
731 WaitForBusy(cs); in hfc_fill_dfifo()
732 WaitNoBusy(cs); in hfc_fill_dfifo()
733 WriteReg(cs, HFCD_DATA_NODEB, cip, cs->tx_skb->data[idx++]); in hfc_fill_dfifo()
734 while (idx < cs->tx_skb->len) { in hfc_fill_dfifo()
735 if (!(WaitNoBusy(cs))) in hfc_fill_dfifo()
737 WriteReg(cs, HFCD_DATA_NODEB, cip, cs->tx_skb->data[idx]); in hfc_fill_dfifo()
740 if (idx != cs->tx_skb->len) { in hfc_fill_dfifo()
741 debugl1(cs, "DFIFO Send BUSY error"); in hfc_fill_dfifo()
744 WaitForBusy(cs); in hfc_fill_dfifo()
745 WaitNoBusy(cs); in hfc_fill_dfifo()
746 ReadReg(cs, HFCD_DATA, HFCD_FIFO | HFCD_F1_INC | HFCD_SEND); in hfc_fill_dfifo()
747 dev_kfree_skb_any(cs->tx_skb); in hfc_fill_dfifo()
748 cs->tx_skb = NULL; in hfc_fill_dfifo()
749 WaitForBusy(cs); in hfc_fill_dfifo()
754 struct BCState *Sel_BCS(struct IsdnCardState *cs, int channel) in Sel_BCS() argument
756 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel)) in Sel_BCS()
757 return (&cs->bcs[0]); in Sel_BCS()
758 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel)) in Sel_BCS()
759 return (&cs->bcs[1]); in Sel_BCS()
765 hfc2bds0_interrupt(struct IsdnCardState *cs, u_char val) in hfc2bds0_interrupt() argument
771 if (cs->debug & L1_DEB_ISAC) in hfc2bds0_interrupt()
772 debugl1(cs, "HFCD irq %x %s", val, in hfc2bds0_interrupt()
773 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ? in hfc2bds0_interrupt()
775 val &= cs->hw.hfcD.int_m1; in hfc2bds0_interrupt()
777 exval = cs->readisac(cs, HFCD_STATES) & 0xf; in hfc2bds0_interrupt()
778 if (cs->debug & L1_DEB_ISAC) in hfc2bds0_interrupt()
779 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcd.ph_state, in hfc2bds0_interrupt()
781 cs->dc.hfcd.ph_state = exval; in hfc2bds0_interrupt()
782 schedule_event(cs, D_L1STATECHANGE); in hfc2bds0_interrupt()
786 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfc2bds0_interrupt()
787 cs->hw.hfcD.int_s1 |= val; in hfc2bds0_interrupt()
790 if (cs->hw.hfcD.int_s1 & 0x18) { in hfc2bds0_interrupt()
792 val = cs->hw.hfcD.int_s1; in hfc2bds0_interrupt()
793 cs->hw.hfcD.int_s1 = exval; in hfc2bds0_interrupt()
796 if (!(bcs = Sel_BCS(cs, 0))) { in hfc2bds0_interrupt()
797 if (cs->debug) in hfc2bds0_interrupt()
798 debugl1(cs, "hfcd spurious 0x08 IRQ"); in hfc2bds0_interrupt()
803 if (!(bcs = Sel_BCS(cs, 1))) { in hfc2bds0_interrupt()
804 if (cs->debug) in hfc2bds0_interrupt()
805 debugl1(cs, "hfcd spurious 0x10 IRQ"); in hfc2bds0_interrupt()
810 if (!(bcs = Sel_BCS(cs, 0))) { in hfc2bds0_interrupt()
811 if (cs->debug) in hfc2bds0_interrupt()
812 debugl1(cs, "hfcd spurious 0x01 IRQ"); in hfc2bds0_interrupt()
815 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfc2bds0_interrupt()
817 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfc2bds0_interrupt()
819 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfc2bds0_interrupt()
822 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfc2bds0_interrupt()
824 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfc2bds0_interrupt()
826 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfc2bds0_interrupt()
834 if (!(bcs = Sel_BCS(cs, 1))) { in hfc2bds0_interrupt()
835 if (cs->debug) in hfc2bds0_interrupt()
836 debugl1(cs, "hfcd spurious 0x02 IRQ"); in hfc2bds0_interrupt()
839 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfc2bds0_interrupt()
841 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfc2bds0_interrupt()
843 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfc2bds0_interrupt()
846 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfc2bds0_interrupt()
848 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfc2bds0_interrupt()
850 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfc2bds0_interrupt()
858 receive_dmsg(cs); in hfc2bds0_interrupt()
861 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) in hfc2bds0_interrupt()
862 del_timer(&cs->dbusytimer); in hfc2bds0_interrupt()
863 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) in hfc2bds0_interrupt()
864 schedule_event(cs, D_CLEARBUSY); in hfc2bds0_interrupt()
865 if (cs->tx_skb) { in hfc2bds0_interrupt()
866 if (cs->tx_skb->len) { in hfc2bds0_interrupt()
867 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfc2bds0_interrupt()
868 hfc_fill_dfifo(cs); in hfc2bds0_interrupt()
869 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfc2bds0_interrupt()
871 debugl1(cs, "hfc_fill_dfifo irq blocked"); in hfc2bds0_interrupt()
875 dev_kfree_skb_irq(cs->tx_skb); in hfc2bds0_interrupt()
876 cs->tx_cnt = 0; in hfc2bds0_interrupt()
877 cs->tx_skb = NULL; in hfc2bds0_interrupt()
880 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { in hfc2bds0_interrupt()
881 cs->tx_cnt = 0; in hfc2bds0_interrupt()
882 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfc2bds0_interrupt()
883 hfc_fill_dfifo(cs); in hfc2bds0_interrupt()
884 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfc2bds0_interrupt()
886 debugl1(cs, "hfc_fill_dfifo irq blocked"); in hfc2bds0_interrupt()
889 schedule_event(cs, D_XMTBUFREADY); in hfc2bds0_interrupt()
892 if (cs->hw.hfcD.int_s1 && count--) { in hfc2bds0_interrupt()
893 val = cs->hw.hfcD.int_s1; in hfc2bds0_interrupt()
894 cs->hw.hfcD.int_s1 = 0; in hfc2bds0_interrupt()
895 if (cs->debug & L1_DEB_ISAC) in hfc2bds0_interrupt()
896 debugl1(cs, "HFCD irq %x loop %d", val, 15-count); in hfc2bds0_interrupt()
905 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; in HFCD_l1hw() local
911 if (cs->debug & DEB_DLOG_HEX) in HFCD_l1hw()
912 LogFrame(cs, skb->data, skb->len); in HFCD_l1hw()
913 if (cs->debug & DEB_DLOG_VERBOSE) in HFCD_l1hw()
914 dlogframe(cs, skb, 0); in HFCD_l1hw()
915 spin_lock_irqsave(&cs->lock, flags); in HFCD_l1hw()
916 if (cs->tx_skb) { in HFCD_l1hw()
917 skb_queue_tail(&cs->sq, skb); in HFCD_l1hw()
919 if (cs->debug & L1_DEB_LAPD) in HFCD_l1hw()
920 Logl2Frame(cs, skb, "PH_DATA Queued", 0); in HFCD_l1hw()
923 cs->tx_skb = skb; in HFCD_l1hw()
924 cs->tx_cnt = 0; in HFCD_l1hw()
926 if (cs->debug & L1_DEB_LAPD) in HFCD_l1hw()
927 Logl2Frame(cs, skb, "PH_DATA", 0); in HFCD_l1hw()
929 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in HFCD_l1hw()
930 hfc_fill_dfifo(cs); in HFCD_l1hw()
931 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in HFCD_l1hw()
933 debugl1(cs, "hfc_fill_dfifo blocked"); in HFCD_l1hw()
936 spin_unlock_irqrestore(&cs->lock, flags); in HFCD_l1hw()
939 spin_lock_irqsave(&cs->lock, flags); in HFCD_l1hw()
940 if (cs->tx_skb) { in HFCD_l1hw()
941 if (cs->debug & L1_DEB_WARN) in HFCD_l1hw()
942 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); in HFCD_l1hw()
943 skb_queue_tail(&cs->sq, skb); in HFCD_l1hw()
944 spin_unlock_irqrestore(&cs->lock, flags); in HFCD_l1hw()
947 if (cs->debug & DEB_DLOG_HEX) in HFCD_l1hw()
948 LogFrame(cs, skb->data, skb->len); in HFCD_l1hw()
949 if (cs->debug & DEB_DLOG_VERBOSE) in HFCD_l1hw()
950 dlogframe(cs, skb, 0); in HFCD_l1hw()
951 cs->tx_skb = skb; in HFCD_l1hw()
952 cs->tx_cnt = 0; in HFCD_l1hw()
954 if (cs->debug & L1_DEB_LAPD) in HFCD_l1hw()
955 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); in HFCD_l1hw()
957 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in HFCD_l1hw()
958 hfc_fill_dfifo(cs); in HFCD_l1hw()
959 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in HFCD_l1hw()
961 debugl1(cs, "hfc_fill_dfifo blocked"); in HFCD_l1hw()
962 spin_unlock_irqrestore(&cs->lock, flags); in HFCD_l1hw()
966 if (cs->debug & L1_DEB_LAPD) in HFCD_l1hw()
967 debugl1(cs, "-> PH_REQUEST_PULL"); in HFCD_l1hw()
969 if (!cs->tx_skb) { in HFCD_l1hw()
976 spin_lock_irqsave(&cs->lock, flags); in HFCD_l1hw()
977 cs->writeisac(cs, HFCD_STATES, HFCD_LOAD_STATE | 3); /* HFC ST 3 */ in HFCD_l1hw()
979 cs->writeisac(cs, HFCD_STATES, 3); /* HFC ST 2 */ in HFCD_l1hw()
980 cs->hw.hfcD.mst_m |= HFCD_MASTER; in HFCD_l1hw()
981 cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m); in HFCD_l1hw()
982 cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION); in HFCD_l1hw()
983 spin_unlock_irqrestore(&cs->lock, flags); in HFCD_l1hw()
984 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); in HFCD_l1hw()
987 spin_lock_irqsave(&cs->lock, flags); in HFCD_l1hw()
988 cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION); in HFCD_l1hw()
989 spin_unlock_irqrestore(&cs->lock, flags); in HFCD_l1hw()
992 spin_lock_irqsave(&cs->lock, flags); in HFCD_l1hw()
993 cs->hw.hfcD.mst_m &= ~HFCD_MASTER; in HFCD_l1hw()
994 cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m); in HFCD_l1hw()
995 spin_unlock_irqrestore(&cs->lock, flags); in HFCD_l1hw()
998 spin_lock_irqsave(&cs->lock, flags); in HFCD_l1hw()
999 cs->hw.hfcD.mst_m |= HFCD_MASTER; in HFCD_l1hw()
1000 cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m); in HFCD_l1hw()
1001 spin_unlock_irqrestore(&cs->lock, flags); in HFCD_l1hw()
1004 if (cs->debug & L1_DEB_WARN) in HFCD_l1hw()
1005 debugl1(cs, "hfcd_l1hw unknown pr %4x", pr); in HFCD_l1hw()
1011 setstack_hfcd(struct PStack *st, struct IsdnCardState *cs) in setstack_hfcd() argument
1017 hfc_dbusy_timer(struct IsdnCardState *cs) in hfc_dbusy_timer() argument
1038 init2bds0(struct IsdnCardState *cs) in init2bds0() argument
1040 cs->setstack_d = setstack_hfcd; in init2bds0()
1041 if (!cs->hw.hfcD.send) in init2bds0()
1042 cs->hw.hfcD.send = init_send_hfcd(16); in init2bds0()
1043 if (!cs->bcs[0].hw.hfc.send) in init2bds0()
1044 cs->bcs[0].hw.hfc.send = init_send_hfcd(32); in init2bds0()
1045 if (!cs->bcs[1].hw.hfc.send) in init2bds0()
1046 cs->bcs[1].hw.hfc.send = init_send_hfcd(32); in init2bds0()
1047 cs->BC_Send_Data = &hfc_send_data; in init2bds0()
1048 cs->bcs[0].BC_SetStack = setstack_2b; in init2bds0()
1049 cs->bcs[1].BC_SetStack = setstack_2b; in init2bds0()
1050 cs->bcs[0].BC_Close = close_2bs0; in init2bds0()
1051 cs->bcs[1].BC_Close = close_2bs0; in init2bds0()
1052 mode_2bs0(cs->bcs, 0, 0); in init2bds0()
1053 mode_2bs0(cs->bcs + 1, 0, 1); in init2bds0()
1057 release2bds0(struct IsdnCardState *cs) in release2bds0() argument
1059 kfree(cs->bcs[0].hw.hfc.send); in release2bds0()
1060 cs->bcs[0].hw.hfc.send = NULL; in release2bds0()
1061 kfree(cs->bcs[1].hw.hfc.send); in release2bds0()
1062 cs->bcs[1].hw.hfc.send = NULL; in release2bds0()
1063 kfree(cs->hw.hfcD.send); in release2bds0()
1064 cs->hw.hfcD.send = NULL; in release2bds0()
1068 set_cs_func(struct IsdnCardState *cs) in set_cs_func() argument
1070 cs->readisac = &readreghfcd; in set_cs_func()
1071 cs->writeisac = &writereghfcd; in set_cs_func()
1072 cs->readisacfifo = &dummyf; in set_cs_func()
1073 cs->writeisacfifo = &dummyf; in set_cs_func()
1074 cs->BC_Read_Reg = &ReadReg; in set_cs_func()
1075 cs->BC_Write_Reg = &WriteReg; in set_cs_func()
1076 cs->dbusytimer.function = (void *) hfc_dbusy_timer; in set_cs_func()
1077 cs->dbusytimer.data = (long) cs; in set_cs_func()
1078 init_timer(&cs->dbusytimer); in set_cs_func()
1079 INIT_WORK(&cs->tqueue, hfcd_bh); in set_cs_func()