Lines Matching refs:cs
78 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
80 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80)); in ReadISAC()
84 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
86 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value); in WriteISAC()
90 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
92 readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size); in ReadISACfifo()
96 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
98 writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size); in WriteISACfifo()
103 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
105 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
109 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) in WriteHSCX() argument
111 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
116 set_ipac_active(struct IsdnCardState *cs, u_int active) in set_ipac_active() argument
119 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, in set_ipac_active()
127 #define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base, \ argument
128 cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0))
129 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \ argument
130 cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0), data)
131 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.base, \ argument
132 cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
133 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ax.base, \ argument
134 cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
141 struct IsdnCardState *cs = dev_id; in bkm_interrupt_ipac() local
145 spin_lock_irqsave(&cs->lock, flags); in bkm_interrupt_ipac()
146 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA); in bkm_interrupt_ipac()
148 spin_unlock_irqrestore(&cs->lock, flags); in bkm_interrupt_ipac()
152 if (cs->debug & L1_DEB_IPAC) in bkm_interrupt_ipac()
153 debugl1(cs, "IPAC ISTA %02X", ista); in bkm_interrupt_ipac()
155 val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40); in bkm_interrupt_ipac()
163 hscx_int_main(cs, val); in bkm_interrupt_ipac()
167 val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80); in bkm_interrupt_ipac()
169 isac_interrupt(cs, val); in bkm_interrupt_ipac()
174 isac_interrupt(cs, val); in bkm_interrupt_ipac()
176 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA); in bkm_interrupt_ipac()
183 sct_quadro_subtypes[cs->subtyp]); in bkm_interrupt_ipac()
184 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF); in bkm_interrupt_ipac()
185 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0); in bkm_interrupt_ipac()
186 spin_unlock_irqrestore(&cs->lock, flags); in bkm_interrupt_ipac()
191 release_io_sct_quadro(struct IsdnCardState *cs) in release_io_sct_quadro() argument
193 release_region(cs->hw.ax.base & 0xffffffc0, 128); in release_io_sct_quadro()
194 if (cs->subtyp == SCT_1) in release_io_sct_quadro()
195 release_region(cs->hw.ax.plx_adr, 64); in release_io_sct_quadro()
199 enable_bkm_int(struct IsdnCardState *cs, unsigned bEnable) in enable_bkm_int() argument
201 if (cs->typ == ISDN_CTYPE_SCT_QUADRO) { in enable_bkm_int()
203 wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) | 0x41)); in enable_bkm_int()
205 wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) & ~0x41)); in enable_bkm_int()
210 reset_bkm(struct IsdnCardState *cs) in reset_bkm() argument
212 if (cs->subtyp == SCT_1) { in reset_bkm()
213 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) & ~4)); in reset_bkm()
216 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) | 4)); in reset_bkm()
222 BKM_card_msg(struct IsdnCardState *cs, int mt, void *arg) in BKM_card_msg() argument
228 spin_lock_irqsave(&cs->lock, flags); in BKM_card_msg()
230 set_ipac_active(cs, 0); in BKM_card_msg()
231 enable_bkm_int(cs, 0); in BKM_card_msg()
232 reset_bkm(cs); in BKM_card_msg()
233 spin_unlock_irqrestore(&cs->lock, flags); in BKM_card_msg()
237 spin_lock_irqsave(&cs->lock, flags); in BKM_card_msg()
238 set_ipac_active(cs, 0); in BKM_card_msg()
239 enable_bkm_int(cs, 0); in BKM_card_msg()
240 spin_unlock_irqrestore(&cs->lock, flags); in BKM_card_msg()
241 release_io_sct_quadro(cs); in BKM_card_msg()
244 spin_lock_irqsave(&cs->lock, flags); in BKM_card_msg()
245 cs->debug |= L1_DEB_IPAC; in BKM_card_msg()
246 set_ipac_active(cs, 1); in BKM_card_msg()
247 inithscxisac(cs, 3); in BKM_card_msg()
249 enable_bkm_int(cs, 1); in BKM_card_msg()
250 spin_unlock_irqrestore(&cs->lock, flags); in BKM_card_msg()
278 struct IsdnCardState *cs = card->cs; in setup_sct_quadro() local
285 if (cs->typ == ISDN_CTYPE_SCT_QUADRO) { in setup_sct_quadro()
286 cs->subtyp = SCT_1; /* Preset */ in setup_sct_quadro()
292 cs->subtyp = card->para[0]; in setup_sct_quadro()
298 if ((cs->subtyp != SCT_1) && ((sub_sys_id != PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) || in setup_sct_quadro()
301 if (cs->subtyp == SCT_1) { in setup_sct_quadro()
322 sct_quadro_subtypes[cs->subtyp]); in setup_sct_quadro()
330 sct_quadro_subtypes[cs->subtyp]); in setup_sct_quadro()
343 sct_quadro_subtypes[cs->subtyp]); in setup_sct_quadro()
354 sct_quadro_subtypes[cs->subtyp]); in setup_sct_quadro()
363 cs->irq = pci_irq; in setup_sct_quadro()
364 cs->irq_flags |= IRQF_SHARED; in setup_sct_quadro()
370 cs->hw.ax.plx_adr = pci_ioaddr1; in setup_sct_quadro()
372 switch (cs->subtyp) { in setup_sct_quadro()
374 cs->hw.ax.base = pci_ioaddr5 + 0x00; in setup_sct_quadro()
390 cs->hw.ax.base = pci_ioaddr4 + 0x08; in setup_sct_quadro()
395 cs->hw.ax.base = pci_ioaddr3 + 0x10; in setup_sct_quadro()
400 cs->hw.ax.base = pci_ioaddr2 + 0x20; in setup_sct_quadro()
406 cs->hw.ax.data_adr = cs->hw.ax.base + 4; in setup_sct_quadro()
410 sct_quadro_subtypes[cs->subtyp], in setup_sct_quadro()
411 cs->hw.ax.plx_adr, in setup_sct_quadro()
412 cs->hw.ax.base, in setup_sct_quadro()
413 cs->hw.ax.data_adr, in setup_sct_quadro()
414 cs->irq); in setup_sct_quadro()
416 test_and_set_bit(HW_IPAC, &cs->HW_Flags); in setup_sct_quadro()
418 cs->readisac = &ReadISAC; in setup_sct_quadro()
419 cs->writeisac = &WriteISAC; in setup_sct_quadro()
420 cs->readisacfifo = &ReadISACfifo; in setup_sct_quadro()
421 cs->writeisacfifo = &WriteISACfifo; in setup_sct_quadro()
423 cs->BC_Read_Reg = &ReadHSCX; in setup_sct_quadro()
424 cs->BC_Write_Reg = &WriteHSCX; in setup_sct_quadro()
425 cs->BC_Send_Data = &hscx_fill_fifo; in setup_sct_quadro()
426 cs->cardmsg = &BKM_card_msg; in setup_sct_quadro()
427 cs->irq_func = &bkm_interrupt_ipac; in setup_sct_quadro()
430 sct_quadro_subtypes[cs->subtyp], in setup_sct_quadro()
431 readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID)); in setup_sct_quadro()