| /linux-4.1.27/drivers/staging/fbtft/ |
| H A D | fb_bd663474.c | 50 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */ init_display()
54 write_reg(par, 0x100, 0x0000); /* power supply setup */ init_display()
55 write_reg(par, 0x101, 0x0000); init_display()
56 write_reg(par, 0x102, 0x3110); init_display()
57 write_reg(par, 0x103, 0xe200); init_display()
58 write_reg(par, 0x110, 0x009d); init_display()
59 write_reg(par, 0x111, 0x0022); init_display()
60 write_reg(par, 0x100, 0x0120); init_display()
63 write_reg(par, 0x100, 0x3120); init_display()
66 write_reg(par, 0x001, 0x0100); init_display()
67 write_reg(par, 0x002, 0x0000); init_display()
68 write_reg(par, 0x003, 0x1230); init_display()
69 write_reg(par, 0x006, 0x0000); init_display()
70 write_reg(par, 0x007, 0x0101); init_display()
71 write_reg(par, 0x008, 0x0808); init_display()
72 write_reg(par, 0x009, 0x0000); init_display()
73 write_reg(par, 0x00b, 0x0000); init_display()
74 write_reg(par, 0x00c, 0x0000); init_display()
75 write_reg(par, 0x00d, 0x0018); init_display()
77 write_reg(par, 0x012, 0x0000); init_display()
78 write_reg(par, 0x013, 0x0000); init_display()
79 write_reg(par, 0x018, 0x0000); init_display()
80 write_reg(par, 0x019, 0x0000); init_display()
82 write_reg(par, 0x203, 0x0000); init_display()
83 write_reg(par, 0x204, 0x0000); init_display()
85 write_reg(par, 0x210, 0x0000); init_display()
86 write_reg(par, 0x211, 0x00ef); init_display()
87 write_reg(par, 0x212, 0x0000); init_display()
88 write_reg(par, 0x213, 0x013f); init_display()
89 write_reg(par, 0x214, 0x0000); init_display()
90 write_reg(par, 0x215, 0x0000); init_display()
91 write_reg(par, 0x216, 0x0000); init_display()
92 write_reg(par, 0x217, 0x0000); init_display()
95 write_reg(par, 0x300, 0x5343); init_display()
96 write_reg(par, 0x301, 0x1021); init_display()
97 write_reg(par, 0x302, 0x0003); init_display()
98 write_reg(par, 0x303, 0x0011); init_display()
99 write_reg(par, 0x304, 0x050a); init_display()
100 write_reg(par, 0x305, 0x4342); init_display()
101 write_reg(par, 0x306, 0x1100); init_display()
102 write_reg(par, 0x307, 0x0003); init_display()
103 write_reg(par, 0x308, 0x1201); init_display()
104 write_reg(par, 0x309, 0x050a); init_display()
107 write_reg(par, 0x400, 0x4027); init_display()
108 write_reg(par, 0x401, 0x0000); init_display()
109 write_reg(par, 0x402, 0x0000); /* First screen drive position (1) */ init_display()
110 write_reg(par, 0x403, 0x013f); /* First screen drive position (2) */ init_display()
111 write_reg(par, 0x404, 0x0000); init_display()
113 write_reg(par, 0x200, 0x0000); init_display()
114 write_reg(par, 0x201, 0x0000); init_display()
115 write_reg(par, 0x100, 0x7120); init_display()
116 write_reg(par, 0x007, 0x0103); init_display()
118 write_reg(par, 0x007, 0x0113); init_display()
131 write_reg(par, 0x0200, xs); set_addr_win()
132 write_reg(par, 0x0201, ys); set_addr_win()
135 write_reg(par, 0x0200, WIDTH - 1 - xs); set_addr_win()
136 write_reg(par, 0x0201, HEIGHT - 1 - ys); set_addr_win()
139 write_reg(par, 0x0200, WIDTH - 1 - ys); set_addr_win()
140 write_reg(par, 0x0201, xs); set_addr_win()
143 write_reg(par, 0x0200, ys); set_addr_win()
144 write_reg(par, 0x0201, HEIGHT - 1 - xs); set_addr_win()
147 write_reg(par, 0x202); /* Write Data to GRAM */ set_addr_win()
157 write_reg(par, 0x003, 0x1230); set_var()
160 write_reg(par, 0x003, 0x1200); set_var()
163 write_reg(par, 0x003, 0x1228); set_var()
166 write_reg(par, 0x003, 0x1218); set_var()
|
| H A D | fb_hx8347d.c | 44 write_reg(par, 0xEA, 0x00); init_display()
45 write_reg(par, 0xEB, 0x20); init_display()
46 write_reg(par, 0xEC, 0x0C); init_display()
47 write_reg(par, 0xED, 0xC4); init_display()
48 write_reg(par, 0xE8, 0x40); init_display()
49 write_reg(par, 0xE9, 0x38); init_display()
50 write_reg(par, 0xF1, 0x01); init_display()
51 write_reg(par, 0xF2, 0x10); init_display()
52 write_reg(par, 0x27, 0xA3); init_display()
55 write_reg(par, 0x1B, 0x1B); init_display()
56 write_reg(par, 0x1A, 0x01); init_display()
57 write_reg(par, 0x24, 0x2F); init_display()
58 write_reg(par, 0x25, 0x57); init_display()
61 write_reg(par, 0x23, 0x8D); /* for flicker adjust */ init_display()
64 write_reg(par, 0x18, 0x36); init_display()
65 write_reg(par, 0x19, 0x01); /* start osc */ init_display()
66 write_reg(par, 0x01, 0x00); /* wakeup */ init_display()
67 write_reg(par, 0x1F, 0x88); init_display()
69 write_reg(par, 0x1F, 0x80); init_display()
71 write_reg(par, 0x1F, 0x90); init_display()
73 write_reg(par, 0x1F, 0xD0); init_display()
77 write_reg(par, 0x17, 0x05); /* 65k */ init_display()
80 write_reg(par, 0x36, 0x00); init_display()
83 write_reg(par, 0x28, 0x38); init_display()
85 write_reg(par, 0x28, 0x3C); init_display()
88 write_reg(par, 0x16, 0x60 | (par->bgr << 3)); init_display()
98 write_reg(par, 0x02, (xs >> 8) & 0xFF); set_addr_win()
99 write_reg(par, 0x03, xs & 0xFF); set_addr_win()
100 write_reg(par, 0x04, (xe >> 8) & 0xFF); set_addr_win()
101 write_reg(par, 0x05, xe & 0xFF); set_addr_win()
102 write_reg(par, 0x06, (ys >> 8) & 0xFF); set_addr_win()
103 write_reg(par, 0x07, ys & 0xFF); set_addr_win()
104 write_reg(par, 0x08, (ye >> 8) & 0xFF); set_addr_win()
105 write_reg(par, 0x09, ye & 0xFF); set_addr_win()
106 write_reg(par, 0x22); set_addr_win()
137 write_reg(par, 0x40 + (i * 0x10), CURVE(i, 0)); set_gamma()
138 write_reg(par, 0x41 + (i * 0x10), CURVE(i, 1)); set_gamma()
139 write_reg(par, 0x42 + (i * 0x10), CURVE(i, 2)); set_gamma()
140 write_reg(par, 0x43 + (i * 0x10), CURVE(i, 3)); set_gamma()
141 write_reg(par, 0x44 + (i * 0x10), CURVE(i, 4)); set_gamma()
142 write_reg(par, 0x45 + (i * 0x10), CURVE(i, 5)); set_gamma()
143 write_reg(par, 0x46 + (i * 0x10), CURVE(i, 6)); set_gamma()
144 write_reg(par, 0x47 + (i * 0x10), CURVE(i, 7)); set_gamma()
145 write_reg(par, 0x48 + (i * 0x10), CURVE(i, 8)); set_gamma()
146 write_reg(par, 0x49 + (i * 0x10), CURVE(i, 9)); set_gamma()
147 write_reg(par, 0x4A + (i * 0x10), CURVE(i, 10)); set_gamma()
148 write_reg(par, 0x4B + (i * 0x10), CURVE(i, 11)); set_gamma()
149 write_reg(par, 0x4C + (i * 0x10), CURVE(i, 12)); set_gamma()
151 write_reg(par, 0x5D, (CURVE(1, 0) << 4) | CURVE(0, 0)); set_gamma()
|
| H A D | fb_tinylcd.c | 39 write_reg(par, 0xB0, 0x80); init_display()
40 write_reg(par, 0xC0, 0x0A, 0x0A); init_display()
41 write_reg(par, 0xC1, 0x45, 0x07); init_display()
42 write_reg(par, 0xC2, 0x33); init_display()
43 write_reg(par, 0xC5, 0x00, 0x42, 0x80); init_display()
44 write_reg(par, 0xB1, 0xD0, 0x11); init_display()
45 write_reg(par, 0xB4, 0x02); init_display()
46 write_reg(par, 0xB6, 0x00, 0x22, 0x3B); init_display()
47 write_reg(par, 0xB7, 0x07); init_display()
48 write_reg(par, 0x36, 0x58); init_display()
49 write_reg(par, 0xF0, 0x36, 0xA5, 0xD3); init_display()
50 write_reg(par, 0xE5, 0x80); init_display()
51 write_reg(par, 0xE5, 0x01); init_display()
52 write_reg(par, 0xB3, 0x00); init_display()
53 write_reg(par, 0xE5, 0x00); init_display()
54 write_reg(par, 0xF0, 0x36, 0xA5, 0x53); init_display()
55 write_reg(par, 0xE0, 0x00, 0x35, 0x33, 0x00, 0x00, 0x00, init_display()
57 write_reg(par, 0x3A, 0x55); init_display()
58 write_reg(par, 0x11); init_display()
60 write_reg(par, 0x29); init_display()
71 write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF); set_addr_win()
74 write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF); set_addr_win()
77 write_reg(par, 0x2C); set_addr_win()
86 write_reg(par, 0xB6, 0x00, 0x02, 0x3B); set_var()
87 write_reg(par, 0x36, 0x28); set_var()
90 write_reg(par, 0xB6, 0x00, 0x22, 0x3B); set_var()
91 write_reg(par, 0x36, 0x58); set_var()
94 write_reg(par, 0xB6, 0x00, 0x22, 0x3B); set_var()
95 write_reg(par, 0x36, 0x38); set_var()
98 write_reg(par, 0xB6, 0x00, 0x22, 0x3B); set_var()
99 write_reg(par, 0x36, 0x08); set_var()
|
| H A D | fb_ili9320.c | 42 write_reg(par, 0x0000); read_devicecode()
66 write_reg(par, 0x00E5, 0x8000); /* Set the Vcore voltage and this setting is must. */ init_display()
67 write_reg(par, 0x0000, 0x0001); /* Start internal OSC. */ init_display()
68 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ init_display()
69 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ init_display()
70 write_reg(par, 0x0004, 0x0000); /* Resize register */ init_display()
71 write_reg(par, 0x0008, 0x0202); /* set the back and front porch */ init_display()
72 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ init_display()
73 write_reg(par, 0x000A, 0x0000); /* FMARK function */ init_display()
74 write_reg(par, 0x000C, 0x0000); /* RGB interface setting */ init_display()
75 write_reg(par, 0x000D, 0x0000); /* Frame marker Position */ init_display()
76 write_reg(par, 0x000F, 0x0000); /* RGB interface polarity */ init_display()
79 write_reg(par, 0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ init_display()
80 write_reg(par, 0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ init_display()
81 write_reg(par, 0x0012, 0x0000); /* VREG1OUT voltage */ init_display()
82 write_reg(par, 0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */ init_display()
84 write_reg(par, 0x0010, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ init_display()
85 write_reg(par, 0x0011, 0x0031); /* R11h=0x0031 at VCI=3.3V DC1[2:0], DC0[2:0], VC[2:0] */ init_display()
87 write_reg(par, 0x0012, 0x0138); /* R12h=0x0138 at VCI=3.3V VREG1OUT voltage */ init_display()
89 write_reg(par, 0x0013, 0x1800); /* R13h=0x1800 at VCI=3.3V VDV[4:0] for VCOM amplitude */ init_display()
90 write_reg(par, 0x0029, 0x0008); /* R29h=0x0008 at VCI=3.3V VCM[4:0] for VCOMH */ init_display()
92 write_reg(par, 0x0020, 0x0000); /* GRAM horizontal Address */ init_display()
93 write_reg(par, 0x0021, 0x0000); /* GRAM Vertical Address */ init_display()
96 write_reg(par, 0x0050, 0x0000); /* Horizontal GRAM Start Address */ init_display()
97 write_reg(par, 0x0051, 0x00EF); /* Horizontal GRAM End Address */ init_display()
98 write_reg(par, 0x0052, 0x0000); /* Vertical GRAM Start Address */ init_display()
99 write_reg(par, 0x0053, 0x013F); /* Vertical GRAM Start Address */ init_display()
100 write_reg(par, 0x0060, 0x2700); /* Gate Scan Line */ init_display()
101 write_reg(par, 0x0061, 0x0001); /* NDL,VLE, REV */ init_display()
102 write_reg(par, 0x006A, 0x0000); /* set scrolling line */ init_display()
105 write_reg(par, 0x0080, 0x0000); init_display()
106 write_reg(par, 0x0081, 0x0000); init_display()
107 write_reg(par, 0x0082, 0x0000); init_display()
108 write_reg(par, 0x0083, 0x0000); init_display()
109 write_reg(par, 0x0084, 0x0000); init_display()
110 write_reg(par, 0x0085, 0x0000); init_display()
113 write_reg(par, 0x0090, 0x0010); init_display()
114 write_reg(par, 0x0092, 0x0000); init_display()
115 write_reg(par, 0x0093, 0x0003); init_display()
116 write_reg(par, 0x0095, 0x0110); init_display()
117 write_reg(par, 0x0097, 0x0000); init_display()
118 write_reg(par, 0x0098, 0x0000); init_display()
119 write_reg(par, 0x0007, 0x0173); /* 262K color and display ON */ init_display()
133 write_reg(par, 0x0020, xs); set_addr_win()
134 write_reg(par, 0x0021, ys); set_addr_win()
137 write_reg(par, 0x0020, WIDTH - 1 - xs); set_addr_win()
138 write_reg(par, 0x0021, HEIGHT - 1 - ys); set_addr_win()
141 write_reg(par, 0x0020, WIDTH - 1 - ys); set_addr_win()
142 write_reg(par, 0x0021, xs); set_addr_win()
145 write_reg(par, 0x0020, ys); set_addr_win()
146 write_reg(par, 0x0021, HEIGHT - 1 - xs); set_addr_win()
149 write_reg(par, 0x0022); /* Write Data to GRAM */ set_addr_win()
158 write_reg(par, 0x3, (par->bgr << 12) | 0x30); set_var()
161 write_reg(par, 0x3, (par->bgr << 12) | 0x28); set_var()
164 write_reg(par, 0x3, (par->bgr << 12) | 0x00); set_var()
167 write_reg(par, 0x3, (par->bgr << 12) | 0x18); set_var()
194 write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4)); set_gamma()
195 write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6)); set_gamma()
196 write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8)); set_gamma()
197 write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2)); set_gamma()
198 write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0)); set_gamma()
200 write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4)); set_gamma()
201 write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6)); set_gamma()
202 write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8)); set_gamma()
203 write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2)); set_gamma()
204 write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0)); set_gamma()
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| H A D | fb_ili9325.c | 120 write_reg(par, 0x00E3, 0x3008); /* Set internal timing */ init_display()
121 write_reg(par, 0x00E7, 0x0012); /* Set internal timing */ init_display()
122 write_reg(par, 0x00EF, 0x1231); /* Set internal timing */ init_display()
123 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ init_display()
124 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ init_display()
125 write_reg(par, 0x0004, 0x0000); /* Resize register */ init_display()
126 write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */ init_display()
127 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ init_display()
128 write_reg(par, 0x000A, 0x0000); /* FMARK function */ init_display()
129 write_reg(par, 0x000C, 0x0000); /* RGB interface setting */ init_display()
130 write_reg(par, 0x000D, 0x0000); /* Frame marker Position */ init_display()
131 write_reg(par, 0x000F, 0x0000); /* RGB interface polarity */ init_display()
134 write_reg(par, 0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ init_display()
135 write_reg(par, 0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ init_display()
136 write_reg(par, 0x0012, 0x0000); /* VREG1OUT voltage */ init_display()
137 write_reg(par, 0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */ init_display()
139 write_reg(par, 0x0010, /* SAP, BT[3:0], AP, DSTB, SLP, STB */ init_display()
141 write_reg(par, 0x0011, 0x220 | vc); /* DC1[2:0], DC0[2:0], VC[2:0] */ init_display()
143 write_reg(par, 0x0012, vrh); /* Internal reference voltage= Vci; */ init_display()
145 write_reg(par, 0x0013, vdv << 8); /* Set VDV[4:0] for VCOM amplitude */ init_display()
146 write_reg(par, 0x0029, vcm); /* Set VCM[5:0] for VCOMH */ init_display()
147 write_reg(par, 0x002B, 0x000C); /* Set Frame Rate */ init_display()
149 write_reg(par, 0x0020, 0x0000); /* GRAM horizontal Address */ init_display()
150 write_reg(par, 0x0021, 0x0000); /* GRAM Vertical Address */ init_display()
153 write_reg(par, 0x0050, 0x0000); /* Horizontal GRAM Start Address */ init_display()
154 write_reg(par, 0x0051, 0x00EF); /* Horizontal GRAM End Address */ init_display()
155 write_reg(par, 0x0052, 0x0000); /* Vertical GRAM Start Address */ init_display()
156 write_reg(par, 0x0053, 0x013F); /* Vertical GRAM Start Address */ init_display()
157 write_reg(par, 0x0060, 0xA700); /* Gate Scan Line */ init_display()
158 write_reg(par, 0x0061, 0x0001); /* NDL,VLE, REV */ init_display()
159 write_reg(par, 0x006A, 0x0000); /* set scrolling line */ init_display()
162 write_reg(par, 0x0080, 0x0000); init_display()
163 write_reg(par, 0x0081, 0x0000); init_display()
164 write_reg(par, 0x0082, 0x0000); init_display()
165 write_reg(par, 0x0083, 0x0000); init_display()
166 write_reg(par, 0x0084, 0x0000); init_display()
167 write_reg(par, 0x0085, 0x0000); init_display()
170 write_reg(par, 0x0090, 0x0010); init_display()
171 write_reg(par, 0x0092, 0x0600); init_display()
172 write_reg(par, 0x0007, 0x0133); /* 262K color and display ON */ init_display()
185 write_reg(par, 0x0020, xs); set_addr_win()
186 write_reg(par, 0x0021, ys); set_addr_win()
189 write_reg(par, 0x0020, WIDTH - 1 - xs); set_addr_win()
190 write_reg(par, 0x0021, HEIGHT - 1 - ys); set_addr_win()
193 write_reg(par, 0x0020, WIDTH - 1 - ys); set_addr_win()
194 write_reg(par, 0x0021, xs); set_addr_win()
197 write_reg(par, 0x0020, ys); set_addr_win()
198 write_reg(par, 0x0021, HEIGHT - 1 - xs); set_addr_win()
201 write_reg(par, 0x0022); /* Write Data to GRAM */ set_addr_win()
211 write_reg(par, 0x03, 0x0030 | (par->bgr << 12)); set_var()
214 write_reg(par, 0x03, 0x0000 | (par->bgr << 12)); set_var()
217 write_reg(par, 0x03, 0x0028 | (par->bgr << 12)); set_var()
220 write_reg(par, 0x03, 0x0018 | (par->bgr << 12)); set_var()
248 write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4)); set_gamma()
249 write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6)); set_gamma()
250 write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8)); set_gamma()
251 write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2)); set_gamma()
252 write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0)); set_gamma()
254 write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4)); set_gamma()
255 write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6)); set_gamma()
256 write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8)); set_gamma()
257 write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2)); set_gamma()
258 write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0)); set_gamma()
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| H A D | fb_ra8875.c | 82 write_reg(par, 0x88, 0x0A); init_display()
83 write_reg(par, 0x89, 0x02); init_display()
86 write_reg(par, 0x10, 0x0C); init_display()
88 write_reg(par, 0x04, 0x03); init_display()
91 write_reg(par, 0x14, 0x27); init_display()
92 write_reg(par, 0x15, 0x00); init_display()
93 write_reg(par, 0x16, 0x05); init_display()
94 write_reg(par, 0x17, 0x04); init_display()
95 write_reg(par, 0x18, 0x03); init_display()
97 write_reg(par, 0x19, 0xEF); init_display()
98 write_reg(par, 0x1A, 0x00); init_display()
99 write_reg(par, 0x1B, 0x05); init_display()
100 write_reg(par, 0x1C, 0x00); init_display()
101 write_reg(par, 0x1D, 0x0E); init_display()
102 write_reg(par, 0x1E, 0x00); init_display()
103 write_reg(par, 0x1F, 0x02); init_display()
106 write_reg(par, 0x88, 0x0A); init_display()
107 write_reg(par, 0x89, 0x02); init_display()
110 write_reg(par, 0x10, 0x0C); init_display()
112 write_reg(par, 0x04, 0x82); init_display()
115 write_reg(par, 0x14, 0x3B); init_display()
116 write_reg(par, 0x15, 0x00); init_display()
117 write_reg(par, 0x16, 0x01); init_display()
118 write_reg(par, 0x17, 0x00); init_display()
119 write_reg(par, 0x18, 0x05); init_display()
121 write_reg(par, 0x19, 0x0F); init_display()
122 write_reg(par, 0x1A, 0x01); init_display()
123 write_reg(par, 0x1B, 0x02); init_display()
124 write_reg(par, 0x1C, 0x00); init_display()
125 write_reg(par, 0x1D, 0x07); init_display()
126 write_reg(par, 0x1E, 0x00); init_display()
127 write_reg(par, 0x1F, 0x09); init_display()
130 write_reg(par, 0x88, 0x0B); init_display()
131 write_reg(par, 0x89, 0x02); init_display()
134 write_reg(par, 0x10, 0x0C); init_display()
136 write_reg(par, 0x04, 0x01); init_display()
139 write_reg(par, 0x14, 0x4F); init_display()
140 write_reg(par, 0x15, 0x05); init_display()
141 write_reg(par, 0x16, 0x0F); init_display()
142 write_reg(par, 0x17, 0x01); init_display()
143 write_reg(par, 0x18, 0x00); init_display()
145 write_reg(par, 0x19, 0xDF); init_display()
146 write_reg(par, 0x1A, 0x01); init_display()
147 write_reg(par, 0x1B, 0x0A); init_display()
148 write_reg(par, 0x1C, 0x00); init_display()
149 write_reg(par, 0x1D, 0x0E); init_display()
150 write_reg(par, 0x1E, 0x00); init_display()
151 write_reg(par, 0x1F, 0x01); init_display()
154 write_reg(par, 0x88, 0x0B); init_display()
155 write_reg(par, 0x89, 0x02); init_display()
158 write_reg(par, 0x10, 0x0C); init_display()
160 write_reg(par, 0x04, 0x81); init_display()
163 write_reg(par, 0x14, 0x63); init_display()
164 write_reg(par, 0x15, 0x03); init_display()
165 write_reg(par, 0x16, 0x03); init_display()
166 write_reg(par, 0x17, 0x02); init_display()
167 write_reg(par, 0x18, 0x00); init_display()
169 write_reg(par, 0x19, 0xDF); init_display()
170 write_reg(par, 0x1A, 0x01); init_display()
171 write_reg(par, 0x1B, 0x14); init_display()
172 write_reg(par, 0x1C, 0x00); init_display()
173 write_reg(par, 0x1D, 0x06); init_display()
174 write_reg(par, 0x1E, 0x00); init_display()
175 write_reg(par, 0x1F, 0x01); init_display()
182 write_reg(par, 0x8a, 0x81); init_display()
183 write_reg(par, 0x8b, 0xFF); init_display()
187 write_reg(par, 0x01, 0x80); init_display()
199 write_reg(par, 0x30, xs & 0x00FF); set_addr_win()
200 write_reg(par, 0x31, (xs & 0xFF00) >> 8); set_addr_win()
201 write_reg(par, 0x32, ys & 0x00FF); set_addr_win()
202 write_reg(par, 0x33, (ys & 0xFF00) >> 8); set_addr_win()
203 write_reg(par, 0x34, (xs+xe) & 0x00FF); set_addr_win()
204 write_reg(par, 0x35, ((xs+xe) & 0xFF00) >> 8); set_addr_win()
205 write_reg(par, 0x36, (ys+ye) & 0x00FF); set_addr_win()
206 write_reg(par, 0x37, ((ys+ye) & 0xFF00) >> 8); set_addr_win()
209 write_reg(par, 0x46, xs & 0xff); set_addr_win()
210 write_reg(par, 0x47, (xs >> 8) & 0x03); set_addr_win()
211 write_reg(par, 0x48, ys & 0xff); set_addr_win()
212 write_reg(par, 0x49, (ys >> 8) & 0x01); set_addr_win()
214 write_reg(par, 0x02); set_addr_win()
|
| H A D | fb_s6d1121.c | 52 write_reg(par, 0x0011, 0x2004); init_display()
53 write_reg(par, 0x0013, 0xCC00); init_display()
54 write_reg(par, 0x0015, 0x2600); init_display()
55 write_reg(par, 0x0014, 0x252A); init_display()
56 write_reg(par, 0x0012, 0x0033); init_display()
57 write_reg(par, 0x0013, 0xCC04); init_display()
58 write_reg(par, 0x0013, 0xCC06); init_display()
59 write_reg(par, 0x0013, 0xCC4F); init_display()
60 write_reg(par, 0x0013, 0x674F); init_display()
61 write_reg(par, 0x0011, 0x2003); init_display()
62 write_reg(par, 0x0016, 0x0007); init_display()
63 write_reg(par, 0x0002, 0x0013); init_display()
64 write_reg(par, 0x0003, 0x0003); init_display()
65 write_reg(par, 0x0001, 0x0127); init_display()
66 write_reg(par, 0x0008, 0x0303); init_display()
67 write_reg(par, 0x000A, 0x000B); init_display()
68 write_reg(par, 0x000B, 0x0003); init_display()
69 write_reg(par, 0x000C, 0x0000); init_display()
70 write_reg(par, 0x0041, 0x0000); init_display()
71 write_reg(par, 0x0050, 0x0000); init_display()
72 write_reg(par, 0x0060, 0x0005); init_display()
73 write_reg(par, 0x0070, 0x000B); init_display()
74 write_reg(par, 0x0071, 0x0000); init_display()
75 write_reg(par, 0x0078, 0x0000); init_display()
76 write_reg(par, 0x007A, 0x0000); init_display()
77 write_reg(par, 0x0079, 0x0007); init_display()
78 write_reg(par, 0x0007, 0x0051); init_display()
79 write_reg(par, 0x0007, 0x0053); init_display()
80 write_reg(par, 0x0079, 0x0000); init_display()
82 write_reg(par, 0x0022); /* Write Data to GRAM */ init_display()
95 write_reg(par, 0x0020, xs); set_addr_win()
96 write_reg(par, 0x0021, ys); set_addr_win()
99 write_reg(par, 0x0020, WIDTH - 1 - xs); set_addr_win()
100 write_reg(par, 0x0021, HEIGHT - 1 - ys); set_addr_win()
103 write_reg(par, 0x0020, WIDTH - 1 - ys); set_addr_win()
104 write_reg(par, 0x0021, xs); set_addr_win()
107 write_reg(par, 0x0020, ys); set_addr_win()
108 write_reg(par, 0x0021, HEIGHT - 1 - xs); set_addr_win()
111 write_reg(par, 0x0022); /* Write Data to GRAM */ set_addr_win()
121 write_reg(par, 0x03, 0x0003 | (par->bgr << 12)); set_var()
124 write_reg(par, 0x03, 0x0000 | (par->bgr << 12)); set_var()
127 write_reg(par, 0x03, 0x000A | (par->bgr << 12)); set_var()
130 write_reg(par, 0x03, 0x0009 | (par->bgr << 12)); set_var()
159 write_reg(par, 0x0030, CURVE(0, 1) << 8 | CURVE(0, 0)); set_gamma()
160 write_reg(par, 0x0031, CURVE(0, 3) << 8 | CURVE(0, 2)); set_gamma()
161 write_reg(par, 0x0032, CURVE(0, 5) << 8 | CURVE(0, 3)); set_gamma()
162 write_reg(par, 0x0033, CURVE(0, 7) << 8 | CURVE(0, 6)); set_gamma()
163 write_reg(par, 0x0034, CURVE(0, 9) << 8 | CURVE(0, 8)); set_gamma()
164 write_reg(par, 0x0035, CURVE(0, 11) << 8 | CURVE(0, 10)); set_gamma()
166 write_reg(par, 0x0036, CURVE(1, 1) << 8 | CURVE(1, 0)); set_gamma()
167 write_reg(par, 0x0037, CURVE(1, 3) << 8 | CURVE(1, 2)); set_gamma()
168 write_reg(par, 0x0038, CURVE(1, 5) << 8 | CURVE(1, 4)); set_gamma()
169 write_reg(par, 0x0039, CURVE(1, 7) << 8 | CURVE(1, 6)); set_gamma()
170 write_reg(par, 0x003A, CURVE(1, 9) << 8 | CURVE(1, 8)); set_gamma()
171 write_reg(par, 0x003B, CURVE(1, 11) << 8 | CURVE(1, 10)); set_gamma()
173 write_reg(par, 0x003C, CURVE(0, 13) << 8 | CURVE(0, 12)); set_gamma()
174 write_reg(par, 0x003D, CURVE(1, 13) << 8 | CURVE(1, 12)); set_gamma()
|
| H A D | fb_upd161704.c | 50 write_reg(par, 0x0003, 0x0001); /* Soft reset */ init_display()
53 write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */ init_display()
57 write_reg(par, 0x0024, 0x007B); /* amplitude setting */ init_display()
59 write_reg(par, 0x0025, 0x003B); /* amplitude setting */ init_display()
60 write_reg(par, 0x0026, 0x0034); /* amplitude setting */ init_display()
62 write_reg(par, 0x0027, 0x0004); /* amplitude setting */ init_display()
63 write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */ init_display()
65 write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */ init_display()
66 write_reg(par, 0x0061, 0x001C); /* adjustment V10 positive polarity */ init_display()
68 write_reg(par, 0x0062, 0x002C); /* adjustment V9 negative polarity */ init_display()
69 write_reg(par, 0x0063, 0x0022); /* adjustment V34 positive polarity */ init_display()
71 write_reg(par, 0x0064, 0x0027); /* adjustment V31 negative polarity */ init_display()
73 write_reg(par, 0x0065, 0x0014); /* adjustment V61 negative polarity */ init_display()
75 write_reg(par, 0x0066, 0x0010); /* adjustment V61 negative polarity */ init_display()
78 write_reg(par, 0x002E, 0x002D); init_display()
81 write_reg(par, 0x0019, 0x0000); /* DC/DC output setting */ init_display()
83 write_reg(par, 0x001A, 0x1000); /* DC/DC frequency setting */ init_display()
84 write_reg(par, 0x001B, 0x0023); /* DC/DC rising setting */ init_display()
85 write_reg(par, 0x001C, 0x0C01); /* Regulator voltage setting */ init_display()
86 write_reg(par, 0x001D, 0x0000); /* Regulator current setting */ init_display()
87 write_reg(par, 0x001E, 0x0009); /* VCOM output setting */ init_display()
88 write_reg(par, 0x001F, 0x0035); /* VCOM amplitude setting */ init_display()
89 write_reg(par, 0x0020, 0x0015); /* VCOMM cencter setting */ init_display()
90 write_reg(par, 0x0018, 0x1E7B); /* DC/DC operation setting */ init_display()
93 write_reg(par, 0x0008, 0x0000); /* Minimum X address */ init_display()
94 write_reg(par, 0x0009, 0x00EF); /* Maximum X address */ init_display()
95 write_reg(par, 0x000a, 0x0000); /* Minimum Y address */ init_display()
96 write_reg(par, 0x000b, 0x013F); /* Maximum Y address */ init_display()
99 write_reg(par, 0x0029, 0x0000); /* [LCDSIZE] X MIN. size set */ init_display()
100 write_reg(par, 0x002A, 0x0000); /* [LCDSIZE] Y MIN. size set */ init_display()
101 write_reg(par, 0x002B, 0x00EF); /* [LCDSIZE] X MAX. size set */ init_display()
102 write_reg(par, 0x002C, 0x013F); /* [LCDSIZE] Y MAX. size set */ init_display()
105 write_reg(par, 0x0032, 0x0002); init_display()
108 write_reg(par, 0x0033, 0x0000); init_display()
111 write_reg(par, 0x0037, 0x0000); init_display()
114 write_reg(par, 0x003B, 0x0001); init_display()
118 write_reg(par, 0x0004, 0x0000); init_display()
121 write_reg(par, 0x0005, 0x0000); /*Window access 00:Normal, 10:Window */ init_display()
124 write_reg(par, 0x0001, 0x0000); init_display()
127 write_reg(par, 0x0000, 0x0000); /* display on */ init_display()
140 write_reg(par, 0x0006, xs); set_addr_win()
141 write_reg(par, 0x0007, ys); set_addr_win()
144 write_reg(par, 0x0006, WIDTH - 1 - xs); set_addr_win()
145 write_reg(par, 0x0007, HEIGHT - 1 - ys); set_addr_win()
148 write_reg(par, 0x0006, WIDTH - 1 - ys); set_addr_win()
149 write_reg(par, 0x0007, xs); set_addr_win()
152 write_reg(par, 0x0006, ys); set_addr_win()
153 write_reg(par, 0x0007, HEIGHT - 1 - xs); set_addr_win()
157 write_reg(par, 0x0e); /* Write Data to GRAM */ set_addr_win()
167 write_reg(par, 0x01, 0x0000); set_var()
168 write_reg(par, 0x05, 0x0000); set_var()
171 write_reg(par, 0x01, 0x00C0); set_var()
172 write_reg(par, 0x05, 0x0000); set_var()
175 write_reg(par, 0x01, 0x0080); set_var()
176 write_reg(par, 0x05, 0x0001); set_var()
179 write_reg(par, 0x01, 0x0040); set_var()
180 write_reg(par, 0x05, 0x0001); set_var()
|
| H A D | fb_ssd1289.c | 50 write_reg(par, 0x00, 0x0001); init_display()
51 write_reg(par, 0x03, 0xA8A4); init_display()
52 write_reg(par, 0x0C, 0x0000); init_display()
53 write_reg(par, 0x0D, 0x080C); init_display()
54 write_reg(par, 0x0E, 0x2B00); init_display()
55 write_reg(par, 0x1E, 0x00B7); init_display()
56 write_reg(par, 0x01, init_display()
58 write_reg(par, 0x02, 0x0600); init_display()
59 write_reg(par, 0x10, 0x0000); init_display()
60 write_reg(par, 0x05, 0x0000); init_display()
61 write_reg(par, 0x06, 0x0000); init_display()
62 write_reg(par, 0x16, 0xEF1C); init_display()
63 write_reg(par, 0x17, 0x0003); init_display()
64 write_reg(par, 0x07, 0x0233); init_display()
65 write_reg(par, 0x0B, 0x0000); init_display()
66 write_reg(par, 0x0F, 0x0000); init_display()
67 write_reg(par, 0x41, 0x0000); init_display()
68 write_reg(par, 0x42, 0x0000); init_display()
69 write_reg(par, 0x48, 0x0000); init_display()
70 write_reg(par, 0x49, 0x013F); init_display()
71 write_reg(par, 0x4A, 0x0000); init_display()
72 write_reg(par, 0x4B, 0x0000); init_display()
73 write_reg(par, 0x44, 0xEF00); init_display()
74 write_reg(par, 0x45, 0x0000); init_display()
75 write_reg(par, 0x46, 0x013F); init_display()
76 write_reg(par, 0x23, 0x0000); init_display()
77 write_reg(par, 0x24, 0x0000); init_display()
78 write_reg(par, 0x25, 0x8000); init_display()
79 write_reg(par, 0x4f, 0x0000); init_display()
80 write_reg(par, 0x4e, 0x0000); init_display()
81 write_reg(par, 0x22); init_display()
94 write_reg(par, 0x4e, xs); set_addr_win()
95 write_reg(par, 0x4f, ys); set_addr_win()
98 write_reg(par, 0x4e, par->info->var.xres - 1 - xs); set_addr_win()
99 write_reg(par, 0x4f, par->info->var.yres - 1 - ys); set_addr_win()
102 write_reg(par, 0x4e, par->info->var.yres - 1 - ys); set_addr_win()
103 write_reg(par, 0x4f, xs); set_addr_win()
106 write_reg(par, 0x4e, ys); set_addr_win()
107 write_reg(par, 0x4f, par->info->var.xres - 1 - xs); set_addr_win()
112 write_reg(par, 0x22); set_addr_win()
129 write_reg(par, 0x11, reg11 | 0x30); set_var()
132 write_reg(par, 0x11, reg11 | 0x28); set_var()
135 write_reg(par, 0x11, reg11 | 0x00); set_var()
138 write_reg(par, 0x11, reg11 | 0x18); set_var()
166 write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4)); set_gamma()
167 write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6)); set_gamma()
168 write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8)); set_gamma()
169 write_reg(par, 0x0033, CURVE(0, 3) << 8 | CURVE(0, 2)); set_gamma()
170 write_reg(par, 0x0034, CURVE(1, 5) << 8 | CURVE(1, 4)); set_gamma()
171 write_reg(par, 0x0035, CURVE(1, 7) << 8 | CURVE(1, 6)); set_gamma()
172 write_reg(par, 0x0036, CURVE(1, 9) << 8 | CURVE(1, 8)); set_gamma()
173 write_reg(par, 0x0037, CURVE(1, 3) << 8 | CURVE(1, 2)); set_gamma()
174 write_reg(par, 0x003A, CURVE(0, 1) << 8 | CURVE(0, 0)); set_gamma()
175 write_reg(par, 0x003B, CURVE(1, 1) << 8 | CURVE(1, 0)); set_gamma()
|
| H A D | fb_ili9341.c | 49 write_reg(par, 0x01); /* software reset */ init_display()
51 write_reg(par, 0x28); /* display off */ init_display()
53 write_reg(par, 0xCF, 0x00, 0x83, 0x30); init_display()
54 write_reg(par, 0xED, 0x64, 0x03, 0x12, 0x81); init_display()
55 write_reg(par, 0xE8, 0x85, 0x01, 0x79); init_display()
56 write_reg(par, 0xCB, 0x39, 0X2C, 0x00, 0x34, 0x02); init_display()
57 write_reg(par, 0xF7, 0x20); init_display()
58 write_reg(par, 0xEA, 0x00, 0x00); init_display()
60 write_reg(par, 0xC0, 0x26); init_display()
61 write_reg(par, 0xC1, 0x11); init_display()
63 write_reg(par, 0xC5, 0x35, 0x3E); init_display()
64 write_reg(par, 0xC7, 0xBE); init_display()
66 write_reg(par, 0x3A, 0x55); /* 16bit pixel */ init_display()
68 write_reg(par, 0xB1, 0x00, 0x1B); init_display()
70 /* write_reg(par, 0xF2, 0x08); */ /* Gamma Function Disable */ init_display()
71 write_reg(par, 0x26, 0x01); init_display()
73 write_reg(par, 0xB7, 0x07); /* entry mode set */ init_display()
74 write_reg(par, 0xB6, 0x0A, 0x82, 0x27, 0x00); init_display()
75 write_reg(par, 0x11); /* sleep out */ init_display()
77 write_reg(par, 0x29); /* display on */ init_display()
89 write_reg(par, 0x2A, set_addr_win()
93 write_reg(par, 0x2B, set_addr_win()
97 write_reg(par, 0x2C); set_addr_win()
112 write_reg(par, 0x36, (1 << MEM_X) | (par->bgr << MEM_BGR)); set_var()
115 write_reg(par, 0x36, set_var()
119 write_reg(par, 0x36, (1 << MEM_Y) | (par->bgr << MEM_BGR)); set_var()
122 write_reg(par, 0x36, (1 << MEM_Y) | (1 << MEM_X) | set_var()
143 write_reg(par, 0xE0 + i, set_gamma()
|
| H A D | fb_ssd1331.c | 30 write_reg(par, 0xae); /* Display Off */ init_display()
31 write_reg(par, 0xa0, 0x70 | (par->bgr << 2)); /* Set Colour Depth */ init_display()
32 write_reg(par, 0x72); /* RGB colour */ init_display()
33 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */ init_display()
34 write_reg(par, 0xa2, 0x00); /* Set Display Offset */ init_display()
35 write_reg(par, 0xa4); /* NORMALDISPLAY */ init_display()
36 write_reg(par, 0xa8, 0x3f); /* Set multiplex */ init_display()
37 write_reg(par, 0xad, 0x8e); /* Set master */ init_display()
38 /* write_reg(par, 0xb0, 0x0b); Set power mode */ init_display()
39 write_reg(par, 0xb1, 0x31); /* Precharge */ init_display()
40 write_reg(par, 0xb3, 0xf0); /* Clock div */ init_display()
41 write_reg(par, 0x8a, 0x64); /* Precharge A */ init_display()
42 write_reg(par, 0x8b, 0x78); /* Precharge B */ init_display()
43 write_reg(par, 0x8c, 0x64); /* Precharge C */ init_display()
44 write_reg(par, 0xbb, 0x3a); /* Precharge level */ init_display()
45 write_reg(par, 0xbe, 0x3e); /* vcomh */ init_display()
46 write_reg(par, 0x87, 0x06); /* Master current */ init_display()
47 write_reg(par, 0x81, 0x91); /* Contrast A */ init_display()
48 write_reg(par, 0x82, 0x50); /* Contrast B */ init_display()
49 write_reg(par, 0x83, 0x7d); /* Contrast C */ init_display()
50 write_reg(par, 0xaf); /* Set Sleep Mode Display On */ init_display()
60 write_reg(par, 0x15, xs, xe); set_addr_win()
61 write_reg(par, 0x75, ys, ye); set_addr_win()
155 write_reg(par, 0xB8, set_gamma()
173 write_reg(par, 0xAE); blank()
175 write_reg(par, 0xAF); blank()
|
| H A D | fb_hx8353d.c | 41 write_reg(par, 0xB9, 0xFF, 0x83, 0x53); init_display()
44 write_reg(par, 0xB0, 0x3C, 0x01); init_display()
47 write_reg(par, 0xB6, 0x94, 0x6C, 0x50); init_display()
50 write_reg(par, 0xB1, 0x00, 0x01, 0x1B, 0x03, 0x01, 0x08, 0x77, 0x89); init_display()
53 write_reg(par, 0x3A, 0x05); init_display()
56 write_reg(par, 0x36, 0xC0); init_display()
59 write_reg(par, 0x11); init_display()
63 write_reg(par, 0x29); init_display()
66 write_reg(par, 0x2D, init_display()
85 write_reg(par, 0x2a, xs >> 8, xs & 0xff, xe >> 8, xe & 0xff); set_addr_win()
88 write_reg(par, 0x2b, ys >> 8, ys & 0xff, ye >> 8, ye & 0xff); set_addr_win()
91 write_reg(par, 0x2c); set_addr_win()
109 write_reg(par, 0x36, mx | my | (par->bgr << 3)); set_var()
112 write_reg(par, 0x36, my | mv | (par->bgr << 3)); set_var()
115 write_reg(par, 0x36, par->bgr << 3); set_var()
118 write_reg(par, 0x36, mx | mv | (par->bgr << 3)); set_var()
132 write_reg(par, 0xE0, set_gamma()
|
| H A D | fb_ili9340.c | 41 write_reg(par, 0xEF, 0x03, 0x80, 0x02); init_display()
42 write_reg(par, 0xCF, 0x00, 0XC1, 0X30); init_display()
43 write_reg(par, 0xED, 0x64, 0x03, 0X12, 0X81); init_display()
44 write_reg(par, 0xE8, 0x85, 0x00, 0x78); init_display()
45 write_reg(par, 0xCB, 0x39, 0x2C, 0x00, 0x34, 0x02); init_display()
46 write_reg(par, 0xF7, 0x20); init_display()
47 write_reg(par, 0xEA, 0x00, 0x00); init_display()
50 write_reg(par, 0xC0, 0x23); init_display()
53 write_reg(par, 0xC1, 0x10); init_display()
56 write_reg(par, 0xC5, 0x3e, 0x28); init_display()
59 write_reg(par, 0xC7, 0x86); init_display()
63 write_reg(par, 0x3A, 0x55); init_display()
67 write_reg(par, 0xB1, 0x00, 0x18); init_display()
70 write_reg(par, 0xB6, 0x08, 0x82, 0x27); init_display()
73 write_reg(par, 0xF2, 0x00); init_display()
76 write_reg(par, 0x26, 0x01); init_display()
79 write_reg(par, 0xE0, init_display()
84 write_reg(par, 0xE1, init_display()
89 write_reg(par, 0x11); init_display()
94 write_reg(par, 0x29); init_display()
105 write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF); set_addr_win()
108 write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF); set_addr_win()
111 write_reg(par, 0x2C); set_addr_win()
138 write_reg(par, 0x36, val | (par->bgr << 3)); set_var()
|
| H A D | fb_ssd1306.c | 35 write_reg() caveat:
38 write_reg(par, val1, val2);
41 write_reg(par, val1);
42 write_reg(par, val2);
62 write_reg(par, 0xAE); init_display()
65 write_reg(par, 0xD5); init_display()
66 write_reg(par, 0x80); init_display()
69 write_reg(par, 0xA8); init_display()
71 write_reg(par, 0x3F); init_display()
73 write_reg(par, 0x1F); init_display()
76 write_reg(par, 0xD3); init_display()
77 write_reg(par, 0x0); init_display()
80 write_reg(par, 0x40 | 0x0); init_display()
83 write_reg(par, 0x8D); init_display()
85 write_reg(par, 0x14); init_display()
88 write_reg(par, 0x20); init_display()
90 write_reg(par, 0x01); init_display()
94 write_reg(par, 0xA0 | 0x1); init_display()
98 write_reg(par, 0xC8); init_display()
101 write_reg(par, 0xDA); init_display()
104 write_reg(par, 0x12); init_display()
107 write_reg(par, 0x02); init_display()
110 write_reg(par, 0xD9); init_display()
111 write_reg(par, 0xF1); init_display()
114 write_reg(par, 0xDB); init_display()
116 write_reg(par, 0x40); init_display()
120 write_reg(par, 0xA4); init_display()
125 write_reg(par, 0xA6); init_display()
128 write_reg(par, 0xAF); init_display()
139 write_reg(par, 0x00 | 0x0); set_addr_win()
141 write_reg(par, 0x10 | 0x0); set_addr_win()
143 write_reg(par, 0x40 | 0x0); set_addr_win()
152 write_reg(par, 0xAE); blank()
154 write_reg(par, 0xAF); blank()
167 write_reg(par, 0x81); set_gamma()
168 write_reg(par, curves[0]); set_gamma()
|
| H A D | fb_uc1701.c | 84 write_reg(par, LCD_RESET_CMD); init_display()
89 write_reg(par, LCD_START_LINE); init_display()
92 write_reg(par, LCD_BOTTOMVIEW | 1); init_display()
94 write_reg(par, LCD_SCAN_DIR | 0x00); init_display()
97 write_reg(par, LCD_ALL_PIXEL | 0); init_display()
100 write_reg(par, LCD_DISPLAY_INVERT | 0); init_display()
103 write_reg(par, LCD_BIAS | 0); init_display()
107 write_reg(par, LCD_POWER_CONTROL | 0x07); init_display()
111 write_reg(par, LCD_VOLTAGE | 0x07); init_display()
115 write_reg(par, LCD_VOLUME_MODE); init_display()
117 write_reg(par, 0x09); init_display()
120 write_reg(par, LCD_NO_OP); init_display()
123 write_reg(par, LCD_ADV_PROG_CTRL); init_display()
124 write_reg(par, LCD_ADV_PROG_CTRL2|LCD_TEMPCOMP_HIGH); init_display()
127 write_reg(par, LCD_DISPLAY_ENABLE | 1); init_display()
140 write_reg(par, LCD_PAGE_ADDRESS); set_addr_win()
144 write_reg(par, 0x00); set_addr_win()
148 write_reg(par, LCD_COL_ADDRESS); set_addr_win()
171 write_reg(par, LCD_PAGE_ADDRESS|(u8)y); write_vmem()
175 write_reg(par, 0x00); write_vmem()
179 write_reg(par, LCD_COL_ADDRESS); write_vmem()
|
| H A D | fb_ssd1351.c | 38 write_reg(par, 0xfd, 0x12); /* Command Lock */ init_display()
39 write_reg(par, 0xfd, 0xb1); /* Command Lock */ init_display()
40 write_reg(par, 0xae); /* Display Off */ init_display()
41 write_reg(par, 0xb3, 0xf1); /* Front Clock Div */ init_display()
42 write_reg(par, 0xca, 0x7f); /* Set Mux Ratio */ init_display()
43 write_reg(par, 0x15, 0x00, 0x7f); /* Set Column Address */ init_display()
44 write_reg(par, 0x75, 0x00, 0x7f); /* Set Row Address */ init_display()
45 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */ init_display()
46 write_reg(par, 0xa2, 0x00); /* Set Display Offset */ init_display()
47 write_reg(par, 0xb5, 0x00); /* Set GPIO */ init_display()
48 write_reg(par, 0xab, 0x01); /* Set Function Selection */ init_display()
49 write_reg(par, 0xb1, 0x32); /* Set Phase Length */ init_display()
50 write_reg(par, 0xb4, 0xa0, 0xb5, 0x55); /* Set Segment Low Voltage */ init_display()
51 write_reg(par, 0xbb, 0x17); /* Set Precharge Voltage */ init_display()
52 write_reg(par, 0xbe, 0x05); /* Set VComH Voltage */ init_display()
53 write_reg(par, 0xc1, 0xc8, 0x80, 0xc8); /* Set Contrast */ init_display()
54 write_reg(par, 0xc7, 0x0f); /* Set Master Contrast */ init_display()
55 write_reg(par, 0xb6, 0x01); /* Set Second Precharge Period */ init_display()
56 write_reg(par, 0xa6); /* Set Display Mode Reset */ init_display()
57 write_reg(par, 0xaf); /* Set Sleep Mode Display On */ init_display()
67 write_reg(par, 0x15, xs, xe); set_addr_win()
68 write_reg(par, 0x75, ys, ye); set_addr_win()
69 write_reg(par, 0x5c); set_addr_win()
90 write_reg(par, 0xA0, remap | 0x00 | 1<<4); set_var()
93 write_reg(par, 0xA0, remap | 0x03 | 1<<4); set_var()
96 write_reg(par, 0xA0, remap | 0x02); set_var()
99 write_reg(par, 0xA0, remap | 0x01); set_var()
152 write_reg(par, 0xB8, set_gamma()
170 write_reg(par, 0xAE); blank()
172 write_reg(par, 0xAF); blank()
206 write_reg(par, 0xB5, on ? 0x03 : 0x02); update_onboard_backlight()
|
| H A D | fb_ili9163.c | 118 write_reg(par, CMD_SWRESET); /* software reset */ init_display()
120 write_reg(par, CMD_SLPOUT); /* exit sleep */ init_display()
122 write_reg(par, CMD_PIXFMT, 0x05); /* Set Color Format 16bit */ init_display()
123 write_reg(par, CMD_GAMMASET, 0x02); /* default gamma curve 3 */ init_display()
125 write_reg(par, CMD_GAMRSEL, 0x01); /* Enable Gamma adj */ init_display()
127 write_reg(par, CMD_NORML); init_display()
128 write_reg(par, CMD_DFUNCTR, 0xff, 0x06); init_display()
130 write_reg(par, CMD_FRMCTR1, 0x08, 0x02); init_display()
131 write_reg(par, CMD_DINVCTR, 0x07); /* display inversion */ init_display()
133 write_reg(par, CMD_PWCTR1, 0x0A, 0x02); init_display()
135 write_reg(par, CMD_PWCTR2, 0x02); init_display()
137 write_reg(par, CMD_VCOMCTR1, 0x50, 0x63); init_display()
138 write_reg(par, CMD_VCOMOFFS, 0); init_display()
140 write_reg(par, CMD_CLMADRS, 0, 0, 0, WIDTH); /* Set Column Address */ init_display()
141 write_reg(par, CMD_PGEADRS, 0, 0, 0, HEIGHT); /* Set Page Address */ init_display()
143 write_reg(par, CMD_DISPON); /* display ON */ init_display()
144 write_reg(par, CMD_RAMWR); /* Memory Write */ init_display()
157 write_reg(par, CMD_CLMADRS, xs >> 8, xs & 0xff, xe >> 8, set_addr_win()
159 write_reg(par, CMD_PGEADRS, set_addr_win()
164 write_reg(par, CMD_CLMADRS, set_addr_win()
167 write_reg(par, CMD_PGEADRS, ys >> 8, ys & 0xff, ye >> 8, set_addr_win()
172 write_reg(par, CMD_CLMADRS, xs >> 8, xs & 0xff, xe >> 8, set_addr_win()
174 write_reg(par, CMD_PGEADRS, ys >> 8, ys & 0xff, ye >> 8, set_addr_win()
180 write_reg(par, CMD_RAMWR); /* Write Data to GRAM mode */ set_addr_win()
227 write_reg(par, CMD_MADCTL, mactrl_data); set_var()
228 write_reg(par, CMD_RAMWR); /* Write Data to GRAM mode */ set_var()
248 write_reg(par, CMD_PGAMMAC, gamma_adj()
266 write_reg(par, CMD_RAMWR); /* Write Data to GRAM mode */ gamma_adj()
|
| H A D | fb_tls8204.c | 51 write_reg(par, 0x21); /* 5:1 1 init_display()
58 write_reg(par, 0x10 | (bs & 0x7)); /* init_display()
67 write_reg(par, 0x04 | (64 >> 6)); init_display()
68 write_reg(par, 0x40 | (64 & 0x3F)); init_display()
71 write_reg(par, 0x20); init_display()
74 write_reg(par, 0x08 | 4); /* init_display()
89 write_reg(par, 0x80); /* 7:1 1 set_addr_win()
94 write_reg(par, 0x40); /* 7:0 0 set_addr_win()
113 write_reg(par, 0x80 | 0); write_vmem()
114 write_reg(par, 0x40 | y); write_vmem()
145 write_reg(par, 0x21); /* turn on extended instruction set */ set_gamma()
146 write_reg(par, 0x80 | curves[0]); set_gamma()
147 write_reg(par, 0x20); /* turn off extended instruction set */ set_gamma()
|
| H A D | fb_hx8340bn.c | 57 write_reg(par, 0xC1, 0xFF, 0x83, 0x40); init_display()
63 write_reg(par, 0x11); init_display()
67 write_reg(par, 0xCA, 0x70, 0x00, 0xD9); init_display()
73 write_reg(par, 0xB0, 0x01, 0x11); init_display()
76 write_reg(par, 0xC9, 0x90, 0x49, 0x10, 0x28, 0x28, 0x10, 0x00, 0x06); init_display()
84 write_reg(par, 0xB5, 0x35, 0x20, 0x45); init_display()
91 write_reg(par, 0xB4, 0x33, 0x25, 0x4C); init_display()
98 write_reg(par, 0x3A, 0x05); init_display()
103 write_reg(par, 0x29); init_display()
111 write_reg(par, FBTFT_CASET, 0x00, xs, 0x00, xe); set_addr_win()
112 write_reg(par, FBTFT_RASET, 0x00, ys, 0x00, ye); set_addr_win()
113 write_reg(par, FBTFT_RAMWR); set_addr_win()
125 write_reg(par, 0x36, par->bgr << 3); set_var()
128 write_reg(par, 0x36, MX | MV | (par->bgr << 3)); set_var()
131 write_reg(par, 0x36, MX | MY | (par->bgr << 3)); set_var()
134 write_reg(par, 0x36, MY | MV | (par->bgr << 3)); set_var()
163 write_reg(par, 0x26, 1 << CURVE(1, 14)); /* Gamma Set (26h) */ set_gamma()
168 write_reg(par, 0xC2, set_gamma()
179 write_reg(par, 0xC3, set_gamma()
|
| H A D | fb_ili9481.c | 64 write_reg(par, 0x2a, xs >> 8, xs & 0xff, xe >> 8, xe & 0xff); set_addr_win()
67 write_reg(par, 0x2b, ys >> 8, ys & 0xff, ye >> 8, ye & 0xff); set_addr_win()
70 write_reg(par, 0x2c); set_addr_win()
82 write_reg(par, 0x36, ROWxCOL | HFLIP | VFLIP | (par->bgr << 3)); set_var()
85 write_reg(par, 0x36, VFLIP | (par->bgr << 3)); set_var()
88 write_reg(par, 0x36, ROWxCOL | (par->bgr << 3)); set_var()
91 write_reg(par, 0x36, HFLIP | (par->bgr << 3)); set_var()
|
| H A D | fb_ili9486.c | 68 write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF); set_addr_win()
71 write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF); set_addr_win()
74 write_reg(par, 0x2C); set_addr_win()
83 write_reg(par, 0x36, 0x80 | (par->bgr << 3)); set_var()
86 write_reg(par, 0x36, 0x20 | (par->bgr << 3)); set_var()
89 write_reg(par, 0x36, 0x40 | (par->bgr << 3)); set_var()
92 write_reg(par, 0x36, 0xE0 | (par->bgr << 3)); set_var()
|
| H A D | fb_pcd8544.c | 61 write_reg(par, 0x21); init_display()
69 write_reg(par, 0x04 | (tc & 0x3)); init_display()
79 write_reg(par, 0x10 | (bs & 0x7)); init_display()
88 write_reg(par, 0x22); init_display()
97 write_reg(par, 0x08 | 4); init_display()
112 write_reg(par, 0x80); set_addr_win()
120 write_reg(par, 0x40); set_addr_win()
158 write_reg(par, 0x23); /* turn on extended instruction set */ set_gamma()
159 write_reg(par, 0x80 | curves[0]); set_gamma()
160 write_reg(par, 0x22); /* turn off extended instruction set */ set_gamma()
|
| H A D | fb_st7735r.c | 103 write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF); set_addr_win()
106 write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF); set_addr_win()
109 write_reg(par, 0x2C); set_addr_win()
127 write_reg(par, 0x36, MX | MY | (par->bgr << 3)); set_var()
130 write_reg(par, 0x36, MY | MV | (par->bgr << 3)); set_var()
133 write_reg(par, 0x36, par->bgr << 3); set_var()
136 write_reg(par, 0x36, MX | MV | (par->bgr << 3)); set_var()
161 write_reg(par, 0xE0 + i, set_gamma()
|
| H A D | fb_s6d02a1.c | 109 write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF); set_addr_win()
112 write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF); set_addr_win()
115 write_reg(par, 0x2C); set_addr_win()
133 write_reg(par, 0x36, MX | MY | (par->bgr << 3)); set_var()
136 write_reg(par, 0x36, MY | MV | (par->bgr << 3)); set_var()
139 write_reg(par, 0x36, par->bgr << 3); set_var()
142 write_reg(par, 0x36, MX | MV | (par->bgr << 3)); set_var()
|
| H A D | flexfb.c | 144 write_reg(par, 0x0020, xs); flexfb_set_addr_win_1()
145 write_reg(par, 0x0021, ys); flexfb_set_addr_win_1()
148 write_reg(par, 0x0020, width - 1 - xs); flexfb_set_addr_win_1()
149 write_reg(par, 0x0021, height - 1 - ys); flexfb_set_addr_win_1()
152 write_reg(par, 0x0020, width - 1 - ys); flexfb_set_addr_win_1()
153 write_reg(par, 0x0021, xs); flexfb_set_addr_win_1()
156 write_reg(par, 0x0020, ys); flexfb_set_addr_win_1()
157 write_reg(par, 0x0021, height - 1 - xs); flexfb_set_addr_win_1()
160 write_reg(par, 0x0022); /* Write Data to GRAM */ flexfb_set_addr_win_1()
172 write_reg(par, 0x4e, xs); flexfb_set_addr_win_2()
173 write_reg(par, 0x4f, ys); flexfb_set_addr_win_2()
176 write_reg(par, 0x4e, par->info->var.xres - 1 - xs); flexfb_set_addr_win_2()
177 write_reg(par, 0x4f, par->info->var.yres - 1 - ys); flexfb_set_addr_win_2()
180 write_reg(par, 0x4e, par->info->var.yres - 1 - ys); flexfb_set_addr_win_2()
181 write_reg(par, 0x4f, xs); flexfb_set_addr_win_2()
184 write_reg(par, 0x4e, ys); flexfb_set_addr_win_2()
185 write_reg(par, 0x4f, par->info->var.xres - 1 - xs); flexfb_set_addr_win_2()
190 write_reg(par, 0x22, 0); flexfb_set_addr_win_2()
198 write_reg(par, 0x15, xs, xe); set_addr_win_3()
199 write_reg(par, 0x75, ys, ye); set_addr_win_3()
200 write_reg(par, 0x5C); set_addr_win_3()
|
| H A D | fb_agm1264k-fl.c | 83 write_reg(par, i, 0x3f); /* display on */ init_display()
84 write_reg(par, i, 0x40); /* set x to 0 */ init_display()
85 write_reg(par, i, 0xb0); /* set page to 0 */ init_display()
86 write_reg(par, i, 0xc0); /* set start line to 0 */ init_display()
374 write_reg(par, 0x00, (1 << 6) | (u8)addr_win.xs); write_vmem()
375 write_reg(par, 0x00, (0x17 << 3) | (u8)y); write_vmem()
396 write_reg(par, 0x01, 1 << 6); write_vmem()
397 write_reg(par, 0x01, (0x17 << 3) | (u8)y); write_vmem()
|
| H A D | fb_watterott.c | 153 write_reg(par, CMD_VERSION); firmware_version()
177 write_reg(par, 0x00); /* make sure mode is set */ init_display()
188 write_reg(par, 0x00); init_display()
224 write_reg(par, CMD_LCD_ORIENTATION, rotate); set_var()
255 write_reg(par, CMD_LCD_LED, brightness); backlight_chip_update_status()
|
| H A D | fbtft.h | 64 * @write_reg: Writes to controller register
261 #define write_reg(par, ...) \ macro
|
| H A D | fbtft-bus.c | 12 * void (*write_reg)(struct fbtft_par *par, int len, ...);
|
| H A D | fbtft_device.c | 1177 write_reg(par, 0x2A, 0, xs + 2, 0, xe + 2); adafruit18_green_tab_set_addr_win()
1178 write_reg(par, 0x2B, 0, ys + 1, 0, ye + 1); adafruit18_green_tab_set_addr_win()
1179 write_reg(par, 0x2C); adafruit18_green_tab_set_addr_win()
|
| H A D | fbtft-core.c | 338 write_reg(par, 0x2A, fbtft_set_addr_win()
342 write_reg(par, 0x2B, fbtft_set_addr_win()
346 write_reg(par, 0x2C); fbtft_set_addr_win()
|
| /linux-4.1.27/arch/sh/boards/mach-kfr2r09/ |
| H A D | lcd_wqvga.c | 68 static void write_reg(void *sohandle, write_reg() function
85 write_reg(sohandle, so, 1, data[i]); write_data()
94 write_reg(sohandle, so, 0, 0xb0); read_device_code()
95 write_reg(sohandle, so, 1, 0x00); read_device_code()
98 write_reg(sohandle, so, 0, 0xb1); read_device_code()
99 write_reg(sohandle, so, 1, 0x00); read_device_code()
102 write_reg(sohandle, so, 0, 0xbf); read_device_code()
120 write_reg(sohandle, so, 0, 0x2c); write_memory_start()
133 write_reg(sohandle, so, 1, 0x00); clear_memory()
140 write_reg(sohandle, so, 0, 0xb0); display_on()
141 write_reg(sohandle, so, 1, 0x00); display_on()
144 write_reg(sohandle, so, 0, 0xb1); display_on()
145 write_reg(sohandle, so, 1, 0x00); display_on()
148 write_reg(sohandle, so, 0, 0xb3); display_on()
152 write_reg(sohandle, so, 0, 0xb4); display_on()
153 write_reg(sohandle, so, 1, 0x00); /* DBI, internal clock */ display_on()
156 write_reg(sohandle, so, 0, 0xc0); display_on()
160 write_reg(sohandle, so, 0, 0xc1); display_on()
164 write_reg(sohandle, so, 0, 0xc2); display_on()
168 write_reg(sohandle, so, 0, 0xc3); display_on()
172 write_reg(sohandle, so, 0, 0xc4); display_on()
176 write_reg(sohandle, so, 0, 0xc8); display_on()
180 write_reg(sohandle, so, 0, 0xc9); display_on()
184 write_reg(sohandle, so, 0, 0xca); display_on()
188 write_reg(sohandle, so, 0, 0xd0); display_on()
192 write_reg(sohandle, so, 0, 0xd1); display_on()
193 write_reg(sohandle, so, 1, 0x00); display_on()
194 write_reg(sohandle, so, 1, 0x0f); display_on()
195 write_reg(sohandle, so, 1, 0x02); display_on()
198 write_reg(sohandle, so, 0, 0xd2); display_on()
199 write_reg(sohandle, so, 1, 0x63); display_on()
200 write_reg(sohandle, so, 1, 0x24); display_on()
203 write_reg(sohandle, so, 0, 0xd3); display_on()
204 write_reg(sohandle, so, 1, 0x63); display_on()
205 write_reg(sohandle, so, 1, 0x24); display_on()
208 write_reg(sohandle, so, 0, 0xd4); display_on()
209 write_reg(sohandle, so, 1, 0x63); display_on()
210 write_reg(sohandle, so, 1, 0x24); display_on()
212 write_reg(sohandle, so, 0, 0xd8); display_on()
213 write_reg(sohandle, so, 1, 0x77); display_on()
214 write_reg(sohandle, so, 1, 0x77); display_on()
217 write_reg(sohandle, so, 0, 0x35); display_on()
218 write_reg(sohandle, so, 1, 0x00); display_on()
221 write_reg(sohandle, so, 0, 0x44); display_on()
222 write_reg(sohandle, so, 1, 0x00); display_on()
223 write_reg(sohandle, so, 1, 0x00); display_on()
226 write_reg(sohandle, so, 0, 0x2a); display_on()
227 write_reg(sohandle, so, 1, 0x00); display_on()
228 write_reg(sohandle, so, 1, 0x00); display_on()
229 write_reg(sohandle, so, 1, 0x00); display_on()
230 write_reg(sohandle, so, 1, 0xef); display_on()
233 write_reg(sohandle, so, 0, 0x2b); display_on()
234 write_reg(sohandle, so, 1, 0x00); display_on()
235 write_reg(sohandle, so, 1, 0x00); display_on()
236 write_reg(sohandle, so, 1, 0x01); display_on()
237 write_reg(sohandle, so, 1, 0x8f); display_on()
240 write_reg(sohandle, so, 0, 0x11); display_on()
248 write_reg(sohandle, so, 0, 0x29); display_on()
|
| /linux-4.1.27/drivers/media/pci/ivtv/ |
| H A D | ivtv-yuv.c | 179 write_reg(read_dec(i), 0x02804); ivtv_yuv_filter()
180 write_reg(read_dec(i), 0x0281c); ivtv_yuv_filter()
182 write_reg(read_dec(i), 0x02808); ivtv_yuv_filter()
183 write_reg(read_dec(i), 0x02820); ivtv_yuv_filter()
185 write_reg(read_dec(i), 0x0280c); ivtv_yuv_filter()
186 write_reg(read_dec(i), 0x02824); ivtv_yuv_filter()
188 write_reg(read_dec(i), 0x02810); ivtv_yuv_filter()
189 write_reg(read_dec(i), 0x02828); ivtv_yuv_filter()
191 write_reg(read_dec(i), 0x02814); ivtv_yuv_filter()
192 write_reg(read_dec(i), 0x0282c); ivtv_yuv_filter()
194 write_reg(0, 0x02818); ivtv_yuv_filter()
195 write_reg(0, 0x02830); ivtv_yuv_filter()
205 write_reg(read_dec(i), 0x02900); ivtv_yuv_filter()
207 write_reg(read_dec(i), 0x02904); ivtv_yuv_filter()
209 write_reg(0, 0x02908); ivtv_yuv_filter()
219 write_reg(read_dec(i), 0x0290c); ivtv_yuv_filter()
221 write_reg(read_dec(i), 0x02910); ivtv_yuv_filter()
223 write_reg(0, 0x02914); ivtv_yuv_filter()
347 write_reg(reg_2834, 0x02834); ivtv_yuv_handle_horizontal()
348 write_reg(reg_2838, 0x02838); ivtv_yuv_handle_horizontal()
352 write_reg(reg_283c, 0x0283c); ivtv_yuv_handle_horizontal()
353 write_reg(reg_2844, 0x02844); ivtv_yuv_handle_horizontal()
358 write_reg(0x00080514, 0x02840); ivtv_yuv_handle_horizontal()
359 write_reg(0x00100514, 0x02848); ivtv_yuv_handle_horizontal()
363 write_reg(reg_2854, 0x02854); ivtv_yuv_handle_horizontal()
367 write_reg(reg_285c, 0x0285c); ivtv_yuv_handle_horizontal()
368 write_reg(reg_2864, 0x02864); ivtv_yuv_handle_horizontal()
372 write_reg(reg_2874, 0x02874); ivtv_yuv_handle_horizontal()
376 write_reg(reg_2870, 0x02870); ivtv_yuv_handle_horizontal()
380 write_reg(reg_2890, 0x02890); ivtv_yuv_handle_horizontal()
591 write_reg(reg_2934, 0x02934); ivtv_yuv_handle_vertical()
592 write_reg(reg_293c, 0x0293c); ivtv_yuv_handle_vertical()
595 write_reg(reg_2944, 0x02944); ivtv_yuv_handle_vertical()
596 write_reg(reg_294c, 0x0294c); ivtv_yuv_handle_vertical()
601 /* write_reg(0,0x02970); */ ivtv_yuv_handle_vertical()
604 write_reg(reg_2930, 0x02938); ivtv_yuv_handle_vertical()
605 write_reg(reg_2930, 0x02930); ivtv_yuv_handle_vertical()
609 write_reg(reg_2928, 0x02928); ivtv_yuv_handle_vertical()
610 write_reg(reg_2928 + 0x514, 0x0292C); ivtv_yuv_handle_vertical()
614 write_reg(reg_2920, 0x02920); ivtv_yuv_handle_vertical()
615 write_reg(reg_2920 + 0x514, 0x02924); ivtv_yuv_handle_vertical()
619 write_reg(reg_2918, 0x02918); ivtv_yuv_handle_vertical()
620 write_reg(reg_291c, 0x0291C); ivtv_yuv_handle_vertical()
624 write_reg(reg_296c, 0x0296c); ivtv_yuv_handle_vertical()
628 write_reg(reg_2940, 0x02948); ivtv_yuv_handle_vertical()
629 write_reg(reg_2940, 0x02940); ivtv_yuv_handle_vertical()
633 write_reg(reg_2950, 0x02950); ivtv_yuv_handle_vertical()
634 write_reg(reg_2954, 0x02954); ivtv_yuv_handle_vertical()
638 write_reg(reg_2958, 0x02958); ivtv_yuv_handle_vertical()
639 write_reg(reg_295c, 0x0295C); ivtv_yuv_handle_vertical()
643 write_reg(reg_2960, 0x02960); ivtv_yuv_handle_vertical()
647 write_reg(reg_2964, 0x02964); ivtv_yuv_handle_vertical()
648 write_reg(reg_2968, 0x02968); ivtv_yuv_handle_vertical()
652 write_reg(reg_289c, 0x0289c); ivtv_yuv_handle_vertical()
844 write_reg(0x01008080, 0x2898); ivtv_yuv_work_handler()
846 write_reg(0x00108080, 0x2898); ivtv_yuv_work_handler()
1204 write_reg(yi->reg_2898 | 0x01000000, 0x2898); ivtv_yuv_close()
1206 write_reg(yi->reg_2834, 0x02834); ivtv_yuv_close()
1207 write_reg(yi->reg_2838, 0x02838); ivtv_yuv_close()
1208 write_reg(yi->reg_283c, 0x0283c); ivtv_yuv_close()
1209 write_reg(yi->reg_2840, 0x02840); ivtv_yuv_close()
1210 write_reg(yi->reg_2844, 0x02844); ivtv_yuv_close()
1211 write_reg(yi->reg_2848, 0x02848); ivtv_yuv_close()
1212 write_reg(yi->reg_2854, 0x02854); ivtv_yuv_close()
1213 write_reg(yi->reg_285c, 0x0285c); ivtv_yuv_close()
1214 write_reg(yi->reg_2864, 0x02864); ivtv_yuv_close()
1215 write_reg(yi->reg_2870, 0x02870); ivtv_yuv_close()
1216 write_reg(yi->reg_2874, 0x02874); ivtv_yuv_close()
1217 write_reg(yi->reg_2890, 0x02890); ivtv_yuv_close()
1218 write_reg(yi->reg_289c, 0x0289c); ivtv_yuv_close()
1220 write_reg(yi->reg_2918, 0x02918); ivtv_yuv_close()
1221 write_reg(yi->reg_291c, 0x0291c); ivtv_yuv_close()
1222 write_reg(yi->reg_2920, 0x02920); ivtv_yuv_close()
1223 write_reg(yi->reg_2924, 0x02924); ivtv_yuv_close()
1224 write_reg(yi->reg_2928, 0x02928); ivtv_yuv_close()
1225 write_reg(yi->reg_292c, 0x0292c); ivtv_yuv_close()
1226 write_reg(yi->reg_2930, 0x02930); ivtv_yuv_close()
1227 write_reg(yi->reg_2934, 0x02934); ivtv_yuv_close()
1228 write_reg(yi->reg_2938, 0x02938); ivtv_yuv_close()
1229 write_reg(yi->reg_293c, 0x0293c); ivtv_yuv_close()
1230 write_reg(yi->reg_2940, 0x02940); ivtv_yuv_close()
1231 write_reg(yi->reg_2944, 0x02944); ivtv_yuv_close()
1232 write_reg(yi->reg_2948, 0x02948); ivtv_yuv_close()
1233 write_reg(yi->reg_294c, 0x0294c); ivtv_yuv_close()
1234 write_reg(yi->reg_2950, 0x02950); ivtv_yuv_close()
1235 write_reg(yi->reg_2954, 0x02954); ivtv_yuv_close()
1236 write_reg(yi->reg_2958, 0x02958); ivtv_yuv_close()
1237 write_reg(yi->reg_295c, 0x0295c); ivtv_yuv_close()
1238 write_reg(yi->reg_2960, 0x02960); ivtv_yuv_close()
1239 write_reg(yi->reg_2964, 0x02964); ivtv_yuv_close()
1240 write_reg(yi->reg_2968, 0x02968); ivtv_yuv_close()
1241 write_reg(yi->reg_296c, 0x0296c); ivtv_yuv_close()
1242 write_reg(yi->reg_2970, 0x02970); ivtv_yuv_close()
1276 write_reg(0, 0x02814); ivtv_yuv_close()
1277 write_reg(0, 0x0282c); ivtv_yuv_close()
1278 write_reg(0, 0x02904); ivtv_yuv_close()
1279 write_reg(0, 0x02910); ivtv_yuv_close()
|
| H A D | ivtv-firmware.c | 100 write_reg(IVTV_CMD_VDM_STOP, IVTV_REG_VDM); ivtv_halt_firmware()
103 write_reg(IVTV_CMD_AO_STOP, IVTV_REG_AO); ivtv_halt_firmware()
106 write_reg(IVTV_CMD_APU_PING, IVTV_REG_APU); ivtv_halt_firmware()
110 write_reg(IVTV_CMD_VPU_STOP16, IVTV_REG_VPU); ivtv_halt_firmware()
112 write_reg(IVTV_CMD_VPU_STOP15, IVTV_REG_VPU); ivtv_halt_firmware()
115 write_reg(IVTV_CMD_HW_BLOCKS_RST, IVTV_REG_HW_BLOCKS); ivtv_halt_firmware()
118 write_reg(IVTV_CMD_SPU_STOP, IVTV_REG_SPU); ivtv_halt_firmware()
123 write_reg(IVTV_CMD_SDRAM_PRECHARGE_INIT, IVTV_REG_ENC_SDRAM_PRECHARGE); ivtv_halt_firmware()
126 write_reg(IVTV_CMD_SDRAM_REFRESH_INIT, IVTV_REG_ENC_SDRAM_REFRESH); ivtv_halt_firmware()
130 write_reg(IVTV_CMD_SDRAM_PRECHARGE_INIT, IVTV_REG_DEC_SDRAM_PRECHARGE); ivtv_halt_firmware()
133 write_reg(IVTV_CMD_SDRAM_REFRESH_INIT, IVTV_REG_DEC_SDRAM_REFRESH); ivtv_halt_firmware()
209 write_reg(read_reg(IVTV_REG_SPU) & IVTV_MASK_SPU_ENABLE, IVTV_REG_SPU); ivtv_firmware_init()
212 write_reg(read_reg(IVTV_REG_VPU) & IVTV_MASK_VPU_ENABLE15, IVTV_REG_VPU); ivtv_firmware_init()
214 write_reg(read_reg(IVTV_REG_VPU) & IVTV_MASK_VPU_ENABLE16, IVTV_REG_VPU); ivtv_firmware_init()
|
| H A D | ivtv-gpio.c | 116 write_reg(curdir, IVTV_REG_GPIO_DIR); ivtv_reset_ir_gpio()
118 write_reg(curout, IVTV_REG_GPIO_OUT); ivtv_reset_ir_gpio()
122 write_reg(curout, IVTV_REG_GPIO_OUT); ivtv_reset_ir_gpio()
124 write_reg(curdir, IVTV_REG_GPIO_DIR); ivtv_reset_ir_gpio()
139 write_reg(curout, IVTV_REG_GPIO_OUT); ivtv_reset_tuner_gpio()
143 write_reg(curout, IVTV_REG_GPIO_OUT); ivtv_reset_tuner_gpio()
177 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); subdev_s_clock_freq()
218 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); subdev_s_tuner()
230 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); subdev_s_radio()
256 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); subdev_s_audio_routing()
271 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | subdev_s_ctrl()
306 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); subdev_s_video_routing()
361 write_reg(itv->card->gpio_init.initial_value | pin, IVTV_REG_GPIO_OUT); ivtv_gpio_init()
362 write_reg(itv->card->gpio_init.direction | pin, IVTV_REG_GPIO_DIR); ivtv_gpio_init()
|
| H A D | ivtv-irq.c | 81 write_reg(IVTV_IRQ_ENC_PIO_COMPLETE, 0x44); ivtv_pio_work_handler()
99 write_reg(IVTV_IRQ_ENC_PIO_COMPLETE, 0x44); ivtv_pio_work_handler()
436 write_reg(s->sg_handle, IVTV_REG_ENCDMAADDR); ivtv_dma_enc_start_xfer()
452 write_reg(s->sg_handle, IVTV_REG_DECDMAADDR); ivtv_dma_dec_start_xfer()
560 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS); ivtv_irq_dma_read()
623 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS); ivtv_irq_enc_dma_complete()
702 write_reg(status, IVTV_REG_DMASTATUS); ivtv_irq_dma_err()
857 write_reg(yuv_offset[next_dma_frame] >> 4, 0x82c); ivtv_irq_vsync()
858 write_reg((yuv_offset[next_dma_frame] + IVTV_YUV_BUFFER_UV_OFFSET) >> 4, 0x830); ivtv_irq_vsync()
859 write_reg(yuv_offset[next_dma_frame] >> 4, 0x834); ivtv_irq_vsync()
860 write_reg((yuv_offset[next_dma_frame] + IVTV_YUV_BUFFER_UV_OFFSET) >> 4, 0x838); ivtv_irq_vsync()
945 if (combo) write_reg(combo, IVTV_REG_IRQSTATUS); ivtv_irq_handler()
1085 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS); ivtv_unfinished_dma()
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| H A D | ivtvfb.c | 270 write_reg((ivtv_window->top << 16) | ivtv_window->left, 0x02a04); ivtvfb_set_display_window()
273 write_reg(((ivtv_window->top+ivtv_window->height) << 16) | (ivtv_window->left+ivtv_window->width), 0x02a08); ivtvfb_set_display_window()
525 write_reg(read_reg(0x02a00) | 0x0002000, 0x02a00); ivtvfb_set_var()
527 write_reg(read_reg(0x02a00) & ~0x0002000, 0x02a00); ivtvfb_set_var()
845 write_reg(osd_pan_index, 0x02A0C); ivtvfb_pan_display()
883 write_reg(regno, 0x02a30); ivtvfb_setcolreg()
884 write_reg(color, 0x02a34); ivtvfb_setcolreg()
966 write_reg(i, 0x02a30); ivtvfb_restore()
967 write_reg(oi->palette_cur[i], 0x02a34); ivtvfb_restore()
969 write_reg(oi->pan_cur, 0x02a0c); ivtvfb_restore()
1230 write_reg(0, 0x02a30); ivtvfb_init_card()
1231 write_reg(0, 0x02a34); ivtvfb_init_card()
|
| H A D | ivtv-i2c.c | 340 write_reg(~state, IVTV_REG_I2C_SETSCL_OFFSET); ivtv_setscl()
348 write_reg(~state & 1, IVTV_REG_I2C_SETSDA_OFFSET); ivtv_setsda()
652 write_reg(~itv->i2c_state, IVTV_REG_I2C_SETSCL_OFFSET); ivtv_setscl_old()
666 write_reg(~itv->i2c_state, IVTV_REG_I2C_SETSDA_OFFSET); ivtv_setsda_old()
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| H A D | ivtv-udma.c | 215 write_reg(itv->udma.SG_handle, IVTV_REG_DECDMAADDR); ivtv_udma_start()
|
| H A D | ivtv-driver.h | 813 #define write_reg(val, reg) writel(val, itv->reg_mem + (reg)) macro
815 do { write_reg(val, reg); read_reg(reg); } while (0)
|
| /linux-4.1.27/drivers/media/radio/ |
| H A D | radio-tea5777.c | 198 tea->write_reg &= ~TEA5777_W_AM_FM_MASK; radio_tea5777_set_freq()
200 tea->write_reg &= ~TEA5777_W_FM_PLL_MASK; radio_tea5777_set_freq()
201 tea->write_reg |= (u64)freq << TEA5777_W_FM_PLL_SHIFT; radio_tea5777_set_freq()
202 tea->write_reg &= ~TEA5777_W_FM_FREF_MASK; radio_tea5777_set_freq()
203 tea->write_reg |= TEA5777_W_FM_FREF_VALUE << radio_tea5777_set_freq()
205 tea->write_reg &= ~TEA5777_W_FM_FORCEMONO_MASK; radio_tea5777_set_freq()
207 tea->write_reg |= 1LL << TEA5777_W_FM_FORCEMONO_SHIFT; radio_tea5777_set_freq()
210 tea->write_reg &= ~TEA5777_W_AM_FM_MASK; radio_tea5777_set_freq()
211 tea->write_reg |= (1LL << TEA5777_W_AM_FM_SHIFT); radio_tea5777_set_freq()
213 tea->write_reg &= ~TEA5777_W_AM_PLL_MASK; radio_tea5777_set_freq()
214 tea->write_reg |= (u64)freq << TEA5777_W_AM_PLL_SHIFT; radio_tea5777_set_freq()
215 tea->write_reg &= ~TEA5777_W_AM_AGCRF_MASK; radio_tea5777_set_freq()
216 tea->write_reg &= ~TEA5777_W_AM_AGCRF_MASK; radio_tea5777_set_freq()
217 tea->write_reg &= ~TEA5777_W_AM_MWLW_MASK; radio_tea5777_set_freq()
218 tea->write_reg |= TEA5777_W_AM_MW << TEA5777_W_AM_MWLW_SHIFT; radio_tea5777_set_freq()
219 tea->write_reg &= ~TEA5777_W_AM_LNA_MASK; radio_tea5777_set_freq()
220 tea->write_reg |= 1LL << TEA5777_W_AM_LNA_SHIFT; radio_tea5777_set_freq()
221 tea->write_reg &= ~TEA5777_W_AM_PEAK_MASK; radio_tea5777_set_freq()
222 tea->write_reg |= 1LL << TEA5777_W_AM_PEAK_SHIFT; radio_tea5777_set_freq()
223 tea->write_reg &= ~TEA5777_W_AM_CALLIGN_MASK; radio_tea5777_set_freq()
227 res = tea->ops->write_reg(tea, tea->write_reg); radio_tea5777_set_freq()
429 tea->write_reg |= TEA5777_W_PROGBLIM_MASK; vidioc_s_hw_freq_seek()
431 tea->write_reg &= ~TEA5777_W_UPDWN_MASK; vidioc_s_hw_freq_seek()
439 tea->write_reg |= TEA5777_W_UPDWN_MASK; vidioc_s_hw_freq_seek()
446 tea->write_reg &= ~TEA5777_W_PROGBLIM_MASK; vidioc_s_hw_freq_seek()
448 tea->write_reg |= TEA5777_W_SEARCH_MASK; vidioc_s_hw_freq_seek()
450 tea->write_reg |= TEA5777_W_UPDWN_MASK; vidioc_s_hw_freq_seek()
453 tea->write_reg &= ~TEA5777_W_UPDWN_MASK; vidioc_s_hw_freq_seek()
480 tea->write_reg &= ~TEA5777_W_SEARCH_MASK; vidioc_s_hw_freq_seek()
493 tea->write_reg &= ~TEA5777_W_PROGBLIM_MASK; vidioc_s_hw_freq_seek()
494 tea->write_reg &= ~TEA5777_W_SEARCH_MASK; vidioc_s_hw_freq_seek()
508 tea->write_reg |= TEA5777_W_MUTE_MASK; tea575x_s_ctrl()
510 tea->write_reg &= ~TEA5777_W_MUTE_MASK; tea575x_s_ctrl()
551 tea->write_reg = (1LL << TEA5777_W_IFCE_SHIFT) | radio_tea5777_init()
|
| H A D | radio-tea5777.h | 50 int (*write_reg)(struct radio_tea5777 *tea, u64 val); member in struct:radio_tea5777_ops
54 * The read value gets returned in val, akin to write_reg, byte 1 from
77 u64 write_reg; member in struct:radio_tea5777
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| H A D | radio-shark2.c | 141 .write_reg = shark_write_reg,
|
| /linux-4.1.27/drivers/staging/media/cxd2099/ |
| H A D | cxd2099.c | 229 static int write_reg(struct cxd *ci, u8 reg, u8 val) write_reg() function
282 /* write_reg(ci, 0x0d, 0x00); */ cam_mode()
283 /* write_reg(ci, 0x0e, 0x01); */ cam_mode()
304 status = write_reg(ci, 0x00, 0x00); init()
307 status = write_reg(ci, 0x01, 0x00); init()
310 status = write_reg(ci, 0x02, 0x10); init()
313 status = write_reg(ci, 0x03, 0x00); init()
316 status = write_reg(ci, 0x05, 0xFF); init()
319 status = write_reg(ci, 0x06, 0x1F); init()
322 status = write_reg(ci, 0x07, 0x1F); init()
325 status = write_reg(ci, 0x08, 0x28); init()
328 status = write_reg(ci, 0x14, 0x20); init()
334 status = write_reg(ci, 0x09, 0x4D); init()
340 status = write_reg(ci, 0x0A, 0xA7); init()
344 status = write_reg(ci, 0x0B, 0x33); init()
347 status = write_reg(ci, 0x0C, 0x33); init()
354 status = write_reg(ci, 0x15, ci->clk_reg_b); init()
360 status = write_reg(ci, 0x17, ci->clk_reg_f); init()
366 status = write_reg(ci, 0x09, 0x6f); init()
370 status = write_reg(ci, 0x09, 0x6d); init()
374 status = write_reg(ci, 0x20, 0x68); init()
377 status = write_reg(ci, 0x21, 0x00); init()
380 status = write_reg(ci, 0x22, 0x02); init()
385 status = write_reg(ci, 0x09, 0x4f); init()
389 status = write_reg(ci, 0x09, 0x4d); init()
394 status = write_reg(ci, 0x20, 0x28); init()
397 status = write_reg(ci, 0x21, 0x00); init()
400 status = write_reg(ci, 0x22, 0x07); init()
411 status = write_reg(ci, 0x01, 0x04); init()
414 status = write_reg(ci, 0x00, 0x31); init()
505 write_reg(ci, 0x00, 0x21); slot_reset()
506 write_reg(ci, 0x06, 0x1F); slot_reset()
507 write_reg(ci, 0x00, 0x31); slot_reset()
510 write_reg(ci, 0x06, 0x1F); slot_reset()
511 write_reg(ci, 0x06, 0x2F); slot_reset()
514 write_reg(ci, 0x00, 0x21); slot_reset()
515 write_reg(ci, 0x06, 0x1F); slot_reset()
516 write_reg(ci, 0x00, 0x31); slot_reset()
518 write_reg(ci, 0x03, 0x02); slot_reset()
582 write_reg(ci, 0x05, istat); campoll()
664 write_reg(ci, 0x0d, ecount>>8); write_data()
665 write_reg(ci, 0x0e, ecount&0xff); write_data()
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| /linux-4.1.27/drivers/media/i2c/ |
| H A D | uda1342.c | 26 static int write_reg(struct i2c_client *client, int reg, int value) write_reg() function
40 write_reg(client, 0x00, 0x1241); /* select input 1 */ uda1342_s_routing()
43 write_reg(client, 0x00, 0x1441); /* select input 2 */ uda1342_s_routing()
78 write_reg(client, 0x00, 0x8000); /* reset registers */ uda1342_probe()
79 write_reg(client, 0x00, 0x1241); /* select input 1 */ uda1342_probe()
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| H A D | tw9906.c | 73 static int write_reg(struct v4l2_subdev *sd, u8 reg, u8 value) write_reg() function
85 if (write_reg(sd, regs[i], regs[i + 1]) < 0) write_regs()
93 write_reg(sd, 0x02, 0x40 | (input << 1)); tw9906_s_video_routing()
128 write_reg(sd, 0x10, ctrl->val); tw9906_s_ctrl()
131 write_reg(sd, 0x11, ctrl->val); tw9906_s_ctrl()
134 write_reg(sd, 0x15, ctrl->val); tw9906_s_ctrl()
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| H A D | tw2804.c | 118 static int write_reg(struct i2c_client *client, u8 reg, u8 value, u8 channel) write_reg() function
218 return write_reg(client, addr, reg, state->channel); tw2804_s_ctrl()
226 return write_reg(client, addr, reg, state->channel); tw2804_s_ctrl()
229 return write_reg(client, TW2804_REG_GAIN, ctrl->val, 0); tw2804_s_ctrl()
232 return write_reg(client, TW2804_REG_CHROMA_GAIN, ctrl->val, 0); tw2804_s_ctrl()
235 return write_reg(client, TW2804_REG_BLUE_BALANCE, ctrl->val, 0); tw2804_s_ctrl()
238 return write_reg(client, TW2804_REG_RED_BALANCE, ctrl->val, 0); tw2804_s_ctrl()
241 return write_reg(client, TW2804_REG_BRIGHTNESS, tw2804_s_ctrl()
245 return write_reg(client, TW2804_REG_CONTRAST, tw2804_s_ctrl()
249 return write_reg(client, TW2804_REG_SATURATION, tw2804_s_ctrl()
253 return write_reg(client, TW2804_REG_HUE, tw2804_s_ctrl()
329 reg = write_reg(client, 0x22, reg, dec->channel); tw2804_s_video_routing()
|
| H A D | tw9903.c | 102 static int write_reg(struct v4l2_subdev *sd, u8 reg, u8 value) write_reg() function
114 if (write_reg(sd, regs[i], regs[i + 1]) < 0) write_regs()
122 write_reg(sd, 0x02, 0x40 | (input << 1)); tw9903_s_video_routing()
158 write_reg(sd, 0x10, ctrl->val); tw9903_s_ctrl()
161 write_reg(sd, 0x11, ctrl->val); tw9903_s_ctrl()
164 write_reg(sd, 0x15, ctrl->val); tw9903_s_ctrl()
|
| /linux-4.1.27/drivers/rtc/ |
| H A D | rtc-r9701.c | 43 static int write_reg(struct device *dev, int address, unsigned char data) write_reg() function
106 ret = write_reg(dev, RHRCNT, bin2bcd(dt->tm_hour)); r9701_set_datetime()
107 ret = ret ? ret : write_reg(dev, RMINCNT, bin2bcd(dt->tm_min)); r9701_set_datetime()
108 ret = ret ? ret : write_reg(dev, RSECCNT, bin2bcd(dt->tm_sec)); r9701_set_datetime()
109 ret = ret ? ret : write_reg(dev, RDAYCNT, bin2bcd(dt->tm_mday)); r9701_set_datetime()
110 ret = ret ? ret : write_reg(dev, RMONCNT, bin2bcd(dt->tm_mon + 1)); r9701_set_datetime()
111 ret = ret ? ret : write_reg(dev, RYRCNT, bin2bcd(dt->tm_year - 100)); r9701_set_datetime()
112 ret = ret ? ret : write_reg(dev, RWKCNT, 1 << dt->tm_wday); r9701_set_datetime()
|
| /linux-4.1.27/drivers/net/can/sja1000/ |
| H A D | sja1000.c | 91 * the write_reg() operation - especially on SMP systems. sja1000_write_cmdreg()
94 priv->write_reg(priv, SJA1000_CMR, val); sja1000_write_cmdreg()
122 priv->write_reg(priv, SJA1000_IER, IRQ_OFF); set_reset_mode()
132 priv->write_reg(priv, SJA1000_MOD, MOD_RM); set_reset_mode()
153 priv->write_reg(priv, SJA1000_IER, IRQ_ALL); set_normal_mode()
155 priv->write_reg(priv, SJA1000_IER, set_normal_mode()
165 priv->write_reg(priv, SJA1000_MOD, mod_reg_val); set_normal_mode()
188 priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN); chipset_init()
191 priv->write_reg(priv, SJA1000_ACCC0, 0x00); chipset_init()
192 priv->write_reg(priv, SJA1000_ACCC1, 0x00); chipset_init()
193 priv->write_reg(priv, SJA1000_ACCC2, 0x00); chipset_init()
194 priv->write_reg(priv, SJA1000_ACCC3, 0x00); chipset_init()
196 priv->write_reg(priv, SJA1000_ACCM0, 0xFF); chipset_init()
197 priv->write_reg(priv, SJA1000_ACCM1, 0xFF); chipset_init()
198 priv->write_reg(priv, SJA1000_ACCM2, 0xFF); chipset_init()
199 priv->write_reg(priv, SJA1000_ACCM3, 0xFF); chipset_init()
201 priv->write_reg(priv, SJA1000_OCR, priv->ocr | OCR_MODE_NORMAL); chipset_init()
217 priv->write_reg(priv, SJA1000_TXERR, 0x0); sja1000_start()
218 priv->write_reg(priv, SJA1000_RXERR, 0x0); sja1000_start()
258 priv->write_reg(priv, SJA1000_BTR0, btr0); sja1000_set_bittiming()
259 priv->write_reg(priv, SJA1000_BTR1, btr1); sja1000_set_bittiming()
307 priv->write_reg(priv, SJA1000_FI, fi); sja1000_start_xmit()
308 priv->write_reg(priv, SJA1000_ID1, (id & 0x1fe00000) >> 21); sja1000_start_xmit()
309 priv->write_reg(priv, SJA1000_ID2, (id & 0x001fe000) >> 13); sja1000_start_xmit()
310 priv->write_reg(priv, SJA1000_ID3, (id & 0x00001fe0) >> 5); sja1000_start_xmit()
311 priv->write_reg(priv, SJA1000_ID4, (id & 0x0000001f) << 3); sja1000_start_xmit()
314 priv->write_reg(priv, SJA1000_FI, fi); sja1000_start_xmit()
315 priv->write_reg(priv, SJA1000_ID1, (id & 0x000007f8) >> 3); sja1000_start_xmit()
316 priv->write_reg(priv, SJA1000_ID2, (id & 0x00000007) << 5); sja1000_start_xmit()
320 priv->write_reg(priv, dreg++, cf->data[i]); sja1000_start_xmit()
|
| H A D | sja1000_platform.c | 85 priv->write_reg = sp_write_reg32; sp_populate()
89 priv->write_reg = sp_write_reg16; sp_populate()
94 priv->write_reg = sp_write_reg8; sp_populate()
111 priv->write_reg = sp_write_reg32; sp_populate_of()
115 priv->write_reg = sp_write_reg16; sp_populate_of()
120 priv->write_reg = sp_write_reg8; sp_populate_of()
|
| H A D | ems_pci.c | 170 priv->write_reg(priv, SJA1000_MOD, 1); ems_pci_check_chan()
172 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); ems_pci_check_chan()
311 priv->write_reg = ems_pci_v1_write_reg; ems_pci_add_card()
315 priv->write_reg = ems_pci_v2_write_reg; ems_pci_add_card()
|
| H A D | sja1000_isa.c | 172 priv->write_reg = sja1000_isa_mem_write_reg; sja1000_isa_probe()
179 priv->write_reg = sja1000_isa_port_write_reg_indirect; sja1000_isa_probe()
183 priv->write_reg = sja1000_isa_port_write_reg; sja1000_isa_probe()
|
| H A D | tscan1.c | 138 priv->write_reg = tscan1_write; tscan1_probe()
|
| H A D | plx_pci.c | 376 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); plx_pci_check_sja1000()
581 priv->write_reg = plx_pci_write_reg; plx_pci_add_card()
|
| H A D | ems_pcmcia.c | 224 priv->write_reg = ems_pcmcia_write_reg; ems_pcmcia_add_card()
|
| H A D | sja1000.h | 159 void (*write_reg) (const struct sja1000_priv *priv, int reg, u8 val); member in struct:sja1000_priv
|
| H A D | peak_pci.c | 489 priv->write_reg = peak_pciec_write_reg; peak_pciec_probe()
630 priv->write_reg = peak_pci_write_reg; peak_pci_probe()
|
| H A D | kvaser_pci.c | 256 priv->write_reg = kvaser_pci_write_reg; kvaser_pci_add_chan()
|
| H A D | peak_pcmcia.c | 567 priv->write_reg = pcan_write_canreg; pcan_add_channels()
|
| /linux-4.1.27/drivers/macintosh/ |
| H A D | therm_windtunnel.c | 120 write_reg( struct i2c_client *cl, int reg, int data, int len ) write_reg() function
157 /* write_reg( x.fan, 0x24, val, 1 ); */ tune_fan()
158 write_reg( x.fan, 0x25, val, 1 ); tune_fan()
159 write_reg( x.fan, 0x20, 0, 1 ); tune_fan()
224 if( write_reg( x.thermostat, 1, val, 1 ) ) setup_hardware()
228 write_reg( x.fan, 0x01, 0x01, 1 ); setup_hardware()
230 write_reg( x.fan, 0x23, 0x91, 1 ); setup_hardware()
232 write_reg( x.fan, 0x00, 0x95, 1 ); setup_hardware()
242 write_reg( x.thermostat, 2, x.overheat_hyst, 2 ); setup_hardware()
243 write_reg( x.thermostat, 3, x.overheat_temp, 2 ); setup_hardware()
268 write_reg( x.fan, 0x01, x.r1, 1 ); restore_regs()
269 write_reg( x.fan, 0x20, x.r20, 1 ); restore_regs()
270 write_reg( x.fan, 0x23, x.r23, 1 ); restore_regs()
271 write_reg( x.fan, 0x25, x.r25, 1 ); restore_regs()
272 write_reg( x.fan, 0x00, x.r0, 1 ); restore_regs()
|
| H A D | therm_adt746x.c | 94 write_reg(struct thermostat* th, int reg, u8 data) write_reg() function
175 write_reg(th, MANUAL_MODE[fan], write_fan_speed()
177 write_reg(th, FAN_SPD_SET[fan], speed); write_fan_speed()
185 write_reg(th, write_fan_speed()
191 write_reg(th, MANUAL_MODE[fan], manual&(~AUTO_MASK)); write_fan_speed()
313 write_reg(th, LIMIT_REG[i], th->limits[i]); set_limit()
521 write_reg(th, CONFIG_REG, 1); probe_thermostat()
583 write_reg(th, LIMIT_REG[i], th->initial_limits[i]); remove_thermostat()
|
| /linux-4.1.27/drivers/gpio/ |
| H A D | gpio-generic.c | 158 bgc->write_reg(bgc->reg_dat, bgc->data); bgpio_set()
170 bgc->write_reg(bgc->reg_set, mask); bgpio_set_with_clear()
172 bgc->write_reg(bgc->reg_clr, mask); bgpio_set_with_clear()
188 bgc->write_reg(bgc->reg_set, bgc->data); bgpio_set_set()
230 bgc->write_reg(reg, bgc->data); bgpio_set_multiple_single_reg()
261 bgc->write_reg(bgc->reg_set, set_mask); bgpio_set_multiple_with_clear()
263 bgc->write_reg(bgc->reg_clr, clear_mask); bgpio_set_multiple_with_clear()
287 bgc->write_reg(bgc->reg_dir, bgc->dir); bgpio_dir_in()
304 bgc->write_reg(bgc->reg_dir, bgc->dir); bgpio_dir_out()
319 bgc->write_reg(bgc->reg_dir, bgc->dir); bgpio_dir_in_inv()
336 bgc->write_reg(bgc->reg_dir, bgc->dir); bgpio_dir_out_inv()
352 bgc->write_reg = bgpio_write8; bgpio_setup_accessors()
357 bgc->write_reg = bgpio_write16be; bgpio_setup_accessors()
360 bgc->write_reg = bgpio_write16; bgpio_setup_accessors()
366 bgc->write_reg = bgpio_write32be; bgpio_setup_accessors()
369 bgc->write_reg = bgpio_write32; bgpio_setup_accessors()
380 bgc->write_reg = bgpio_write64; bgpio_setup_accessors()
|
| H A D | gpio-it8761e.c | 53 static void write_reg(u8 data, u8 addr, u8 port) write_reg() function
75 write_reg(0x2, 0x7, port); enter_gpio_mode()
105 write_reg(curr_dirs & ~(1 << bit), io_reg, port); it8761e_gpio_direction_in()
151 write_reg(curr_dirs | (1 << bit), io_reg, port); it8761e_gpio_direction_out()
|
| H A D | gpio-grgpio.c | 115 bgc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask); grgpio_set_imask()
171 priv->bgc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol); grgpio_irq_set_type()
172 priv->bgc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge); grgpio_irq_set_type()
|
| H A D | gpio-xgene-sb.c | 69 bgc->write_reg(reg, data); xgene_gpio_set_bit()
|
| H A D | gpio-dwapb.c | 106 bgc->write_reg(reg_base + offset, val); dwapb_write()
|
| /linux-4.1.27/drivers/ide/ |
| H A D | opti621.c | 38 static void write_reg(u8 value, int reg) write_reg() function
113 write_reg(drive->dn & 1, MISC_REG); opti621_set_pio_mode()
115 write_reg(tim, READ_REG); opti621_set_pio_mode()
117 write_reg(tim, WRITE_REG); opti621_set_pio_mode()
121 write_reg(0x85, CNTRL_REG); opti621_set_pio_mode()
125 write_reg(misc, MISC_REG); opti621_set_pio_mode()
|
| /linux-4.1.27/drivers/video/fbdev/mbx/ |
| H A D | mbxfb.c | 38 #define write_reg(val, reg) do { writel((val), (reg)); } while(0) macro
448 write_reg(vsctrl, VSCTRL); mbxfb_setupOverlay()
449 write_reg(vscadr, VSCADR); mbxfb_setupOverlay()
450 write_reg(vubase, VUBASE); mbxfb_setupOverlay()
451 write_reg(vvbase, VVBASE); mbxfb_setupOverlay()
452 write_reg(vsadr, VSADR); mbxfb_setupOverlay()
455 write_reg(sssize, SSSIZE); mbxfb_setupOverlay()
456 write_reg(spoctrl, SPOCTRL); mbxfb_setupOverlay()
457 write_reg(shctrl, SHCTRL); mbxfb_setupOverlay()
465 write_reg(vovrclk, VOVRCLK); mbxfb_setupOverlay()
825 write_reg(0xff000100, VSCOEFF0); enable_controller()
826 write_reg(0xfdfcfdfe, VSCOEFF1); enable_controller()
827 write_reg(0x170d0500, VSCOEFF2); enable_controller()
828 write_reg(0x3d372d22, VSCOEFF3); enable_controller()
829 write_reg(0x00000040, VSCOEFF4); enable_controller()
831 write_reg(0xff010100, HSCOEFF0); enable_controller()
832 write_reg(0x00000000, HSCOEFF1); enable_controller()
833 write_reg(0x02010000, HSCOEFF2); enable_controller()
834 write_reg(0x01020302, HSCOEFF3); enable_controller()
835 write_reg(0xf9fbfe00, HSCOEFF4); enable_controller()
836 write_reg(0xfbf7f6f7, HSCOEFF5); enable_controller()
837 write_reg(0x1c110700, HSCOEFF6); enable_controller()
838 write_reg(0x3e393127, HSCOEFF7); enable_controller()
839 write_reg(0x00000040, HSCOEFF8); enable_controller()
|
| /linux-4.1.27/drivers/tty/ |
| H A D | synclinkmp.c | 622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
1543 write_reg(info, CTL, RegValue); set_break()
2086 write_reg(info, IER2, 0); isr_timer()
2098 write_reg(info, (unsigned char)(timer + TMCS), 0); isr_timer()
2116 write_reg(info, SR1, status); isr_rxint()
2119 write_reg(info, SR2, status2); isr_rxint()
2234 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ isr_txeom()
2235 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ isr_txeom()
2236 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ isr_txeom()
2239 write_reg(info, CMD, TXRESET); isr_txeom()
2240 write_reg(info, CMD, TXENABLE); isr_txeom()
2242 write_reg(info, CMD, TXBUFCLR); isr_txeom()
2248 write_reg(info, SR1, (unsigned char)(UDRN + IDLE)); isr_txeom()
2293 write_reg(info, SR1, status); isr_txint()
2340 write_reg(info, IE0, info->ie0_value); isr_txrdy()
2355 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); isr_rxdmaok()
2372 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); isr_rxdmaerror()
2386 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ isr_txdmaok()
2387 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ isr_txdmaok()
2388 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ isr_txdmaok()
2397 write_reg(info, IE0, info->ie0_value); isr_txdmaok()
2408 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1)); isr_txdmaerror()
2446 write_reg(info, IE1, info->ie1_value); isr_io_pin()
2466 write_reg(info, IE1, info->ie1_value); isr_io_pin()
2746 write_reg(info, IE1, info->ie1_value); program_hw()
2996 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ tx_abort()
2997 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ tx_abort()
2999 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ tx_abort()
3000 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ tx_abort()
3002 write_reg(info, CMD, TXABORT); tx_abort()
3078 write_reg(info, IE1, info->ie1_value); wait_mgsl_event()
3143 write_reg(info, IE1, info->ie1_value); wait_mgsl_event()
3946 write_reg(info, LPR, 1); /* set low power mode */ synclinkmp_cleanup()
4035 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); enable_loopback()
4046 write_reg(info, RXS, 0x40); enable_loopback()
4047 write_reg(info, TXS, 0x40); enable_loopback()
4053 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); enable_loopback()
4060 write_reg(info, RXS, 0x00); enable_loopback()
4061 write_reg(info, TXS, 0x00); enable_loopback()
4107 write_reg(info, TXS, set_rate()
4109 write_reg(info, RXS, set_rate()
4111 write_reg(info, TMC, (unsigned char)TMCValue); set_rate()
4114 write_reg(info, TXS,0); set_rate()
4115 write_reg(info, RXS,0); set_rate()
4116 write_reg(info, TMC, 0); set_rate()
4128 write_reg(info, CMD, RXRESET); rx_stop()
4131 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */ rx_stop()
4133 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ rx_stop()
4134 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ rx_stop()
4135 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */ rx_stop()
4151 write_reg(info, CMD, RXRESET); rx_start()
4156 write_reg(info, IE0, info->ie0_value); rx_start()
4159 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ rx_start()
4160 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ rx_start()
4183 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */ rx_start()
4184 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */ rx_start()
4188 write_reg(info, IE0, info->ie0_value); rx_start()
4191 write_reg(info, CMD, RXENABLE); rx_start()
4207 write_reg(info, CMD, TXRESET); tx_start()
4208 write_reg(info, CMD, TXENABLE); tx_start()
4234 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ tx_start()
4235 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ tx_start()
4248 write_reg(info, IE1, info->ie1_value); tx_start()
4249 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); tx_start()
4251 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */ tx_start()
4252 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */ tx_start()
4261 write_reg(info, IE0, info->ie0_value); tx_start()
4278 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ tx_stop()
4279 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ tx_stop()
4281 write_reg(info, CMD, TXRESET); tx_stop()
4284 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ tx_stop()
4285 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ tx_stop()
4288 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */ tx_stop()
4331 write_reg(info, TRB, info->x_char); tx_load_fifo()
4334 write_reg(info, TRB, info->tx_buf[info->tx_get++]); tx_load_fifo()
4360 write_reg(info, IE0, info->ie0_value); reset_port()
4361 write_reg(info, IE1, info->ie1_value); reset_port()
4362 write_reg(info, IE2, info->ie2_value); reset_port()
4364 write_reg(info, CMD, CHRESET); reset_port()
4403 write_reg(info, MD0, RegValue); async_mode()
4425 write_reg(info, MD1, RegValue); async_mode()
4437 write_reg(info, MD2, RegValue); async_mode()
4446 write_reg(info, RXS, RegValue); async_mode()
4455 write_reg(info, TXS, RegValue); async_mode()
4471 write_reg(info, RRC, 0x00); async_mode()
4478 write_reg(info, TRC0, 0x10); async_mode()
4485 write_reg(info, TRC1, 0x1e); async_mode()
4502 write_reg(info, CTL, RegValue); async_mode()
4506 write_reg(info, IE0, info->ie0_value); async_mode()
4510 write_reg(info, IE1, info->ie1_value); async_mode()
4514 write_reg(info, IE2, info->ie2_value); async_mode()
4533 write_reg(info, TXDMA + DIR, 0); hdlc_mode()
4534 write_reg(info, RXDMA + DIR, 0); hdlc_mode()
4554 write_reg(info, MD0, RegValue); hdlc_mode()
4566 write_reg(info, MD1, RegValue); hdlc_mode()
4599 write_reg(info, MD2, RegValue); hdlc_mode()
4613 write_reg(info, RXS, RegValue); hdlc_mode()
4626 write_reg(info, TXS, RegValue); hdlc_mode()
4648 write_reg(info, RRC, rx_active_fifo_level); hdlc_mode()
4655 write_reg(info, TRC0, tx_active_fifo_level); hdlc_mode()
4662 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1)); hdlc_mode()
4675 write_reg(info, TXDMA + DMR, 0x14); hdlc_mode()
4676 write_reg(info, RXDMA + DMR, 0x14); hdlc_mode()
4679 write_reg(info, RXDMA + CPB, hdlc_mode()
4683 write_reg(info, TXDMA + CPB, hdlc_mode()
4690 write_reg(info, IE0, info->ie0_value); hdlc_mode()
4707 write_reg(info, CTL, RegValue); hdlc_mode()
4738 write_reg(info, IDL, RegValue); tx_set_idle()
4782 write_reg(info, CTL, RegValue); set_signals()
5072 write_reg(info, TMC, testval[i]); register_test()
5073 write_reg(info, IDL, testval[(i+1)%count]); register_test()
5074 write_reg(info, SA0, testval[(i+2)%count]); register_test()
5075 write_reg(info, SA1, testval[(i+3)%count]); register_test()
5110 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4)); irq_test()
5112 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */ irq_test()
5126 write_reg(info, (unsigned char)(timer + TMCS), 0x50); irq_test()
5147 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */ sca_init()
5148 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */ sca_init()
5149 write_reg(info, WCRL, 0); /* wait controller low range */ sca_init()
5150 write_reg(info, WCRM, 0); /* wait controller mid range */ sca_init()
5151 write_reg(info, WCRH, 0); /* wait controller high range */ sca_init()
5162 write_reg(info, DPCR, dma_priority); sca_init()
5165 write_reg(info, DMER, 0x80); sca_init()
5168 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */ sca_init()
5169 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */ sca_init()
5170 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */ sca_init()
5178 write_reg(info, ITCR, 0); sca_init()
5560 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value) write_reg() function
|
| /linux-4.1.27/drivers/net/can/ |
| H A D | xilinx_can.c | 125 * @write_reg: For writing data to CAN registers
139 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg, member in struct:xcan_priv
229 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); set_reset_mode()
280 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0); xcan_set_bittiming()
281 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1); xcan_set_bittiming()
317 priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL); xcan_chip_start()
328 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr); xcan_chip_start()
329 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); xcan_chip_start()
444 priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id); xcan_start_xmit()
446 priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc); xcan_start_xmit()
448 priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]); xcan_start_xmit()
452 priv->write_reg(priv, XCAN_TXFIFO_DW2_OFFSET, data[1]); xcan_start_xmit()
551 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status); xcan_err_interrupt()
561 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); xcan_err_interrupt()
602 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); xcan_err_interrupt()
715 priv->write_reg(priv, XCAN_ICR_OFFSET, xcan_rx_poll()
719 priv->write_reg(priv, XCAN_ICR_OFFSET, xcan_rx_poll()
723 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK); xcan_rx_poll()
734 priv->write_reg(priv, XCAN_IER_OFFSET, ier); xcan_rx_poll()
751 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); xcan_tx_interrupt()
786 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK | xcan_interrupt()
798 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_ERROR_MASK | xcan_interrupt()
808 priv->write_reg(priv, XCAN_IER_OFFSET, ier); xcan_interrupt()
829 priv->write_reg(priv, XCAN_IER_OFFSET, ier); xcan_chip_stop()
830 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); xcan_chip_stop()
987 priv->write_reg(priv, XCAN_MSR_OFFSET, XCAN_MSR_SLEEP_MASK); xcan_suspend()
1022 priv->write_reg(priv, XCAN_MSR_OFFSET, 0); xcan_resume()
1023 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); xcan_resume()
1129 priv->write_reg = xcan_write_reg_le; xcan_probe()
1133 priv->write_reg = xcan_write_reg_be; xcan_probe()
|
| /linux-4.1.27/drivers/net/ethernet/intel/igb/ |
| H A D | e1000_phy.c | 113 if (!(hw->phy.ops.write_reg)) igb_phy_reset_dsp()
116 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); igb_phy_reset_dsp()
120 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); igb_phy_reset_dsp()
506 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); igb_copper_link_setup_82580()
531 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); igb_copper_link_setup_82580()
597 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); igb_copper_link_setup_m88()
624 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, igb_copper_link_setup_m88()
704 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); igb_copper_link_setup_m88_gen2()
719 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); igb_copper_link_setup_m88_gen2()
803 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); igb_copper_link_setup_igp()
822 ret_val = phy->ops.write_reg(hw, igb_copper_link_setup_igp()
834 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); igb_copper_link_setup_igp()
863 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); igb_copper_link_setup_igp()
914 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); igb_copper_link_autoneg()
1074 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); igb_phy_setup_autoneg()
1081 ret_val = phy->ops.write_reg(hw, igb_phy_setup_autoneg()
1165 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); igb_phy_force_speed_duplex_igp()
1179 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); igb_phy_force_speed_duplex_igp()
1235 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, igb_phy_force_speed_duplex_m88()
1249 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); igb_phy_force_speed_duplex_m88()
1285 ret_val = phy->ops.write_reg(hw, igb_phy_force_speed_duplex_m88()
1318 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); igb_phy_force_speed_duplex_m88()
1330 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); igb_phy_force_speed_duplex_m88()
1426 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, igb_set_d3_lplu_state()
1443 ret_val = phy->ops.write_reg(hw, igb_set_d3_lplu_state()
1456 ret_val = phy->ops.write_reg(hw, igb_set_d3_lplu_state()
1466 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, igb_set_d3_lplu_state()
1478 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, igb_set_d3_lplu_state()
1753 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); igb_get_cable_length_m88_gen2()
1776 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, igb_get_cable_length_m88_gen2()
1788 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); igb_get_cable_length_m88_gen2()
1811 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, igb_get_cable_length_m88_gen2()
2060 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); igb_phy_sw_reset()
2126 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); igb_phy_init_script_igp3()
2128 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); igb_phy_init_script_igp3()
2130 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); igb_phy_init_script_igp3()
2132 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); igb_phy_init_script_igp3()
2134 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); igb_phy_init_script_igp3()
2136 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); igb_phy_init_script_igp3()
2138 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); igb_phy_init_script_igp3()
2140 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); igb_phy_init_script_igp3()
2142 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); igb_phy_init_script_igp3()
2144 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); igb_phy_init_script_igp3()
2146 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); igb_phy_init_script_igp3()
2148 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); igb_phy_init_script_igp3()
2150 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); igb_phy_init_script_igp3()
2152 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); igb_phy_init_script_igp3()
2154 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); igb_phy_init_script_igp3()
2156 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); igb_phy_init_script_igp3()
2158 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); igb_phy_init_script_igp3()
2160 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); igb_phy_init_script_igp3()
2162 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); igb_phy_init_script_igp3()
2164 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); igb_phy_init_script_igp3()
2166 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); igb_phy_init_script_igp3()
2168 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); igb_phy_init_script_igp3()
2170 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); igb_phy_init_script_igp3()
2172 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); igb_phy_init_script_igp3()
2174 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); igb_phy_init_script_igp3()
2176 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); igb_phy_init_script_igp3()
2180 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); igb_phy_init_script_igp3()
2182 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); igb_phy_init_script_igp3()
2186 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); igb_phy_init_script_igp3()
2188 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); igb_phy_init_script_igp3()
2190 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); igb_phy_init_script_igp3()
2192 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); igb_phy_init_script_igp3()
2211 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); igb_power_up_phy_copper()
2228 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); igb_power_down_phy_copper()
2278 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); igb_phy_force_speed_duplex_82580()
2291 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); igb_phy_force_speed_duplex_82580()
2510 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); igb_set_master_slave_mode()
|
| H A D | e1000_i210.c | 756 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr); __igb_access_xmdio_reg()
760 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address); __igb_access_xmdio_reg()
764 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA | __igb_access_xmdio_reg()
772 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data); __igb_access_xmdio_reg()
777 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0); __igb_access_xmdio_reg()
|
| H A D | e1000_82575.c | 122 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); igb_check_for_link_media_swap()
134 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); igb_check_for_link_media_swap()
143 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); igb_check_for_link_media_swap()
194 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; igb_init_phy_params_82575()
201 phy->ops.write_reg = igb_write_phy_reg_82580; igb_init_phy_params_82575()
206 phy->ops.write_reg = igb_write_phy_reg_gs40g; igb_init_phy_params_82575()
210 phy->ops.write_reg = igb_write_phy_reg_igp; igb_init_phy_params_82575()
242 ret_val = phy->ops.write_reg(hw, igb_init_phy_params_82575()
903 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); igb_phy_hw_reset_sgmii_82575()
938 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, igb_set_d0_lplu_state_82575()
947 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, igb_set_d0_lplu_state_82575()
953 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, igb_set_d0_lplu_state_82575()
967 ret_val = phy->ops.write_reg(hw, igb_set_d0_lplu_state_82575()
978 ret_val = phy->ops.write_reg(hw, igb_set_d0_lplu_state_82575()
2525 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); __igb_access_emi_reg()
2532 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); __igb_access_emi_reg()
2625 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); igb_set_eee_i354()
2635 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, igb_set_eee_i354()
2641 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); igb_set_eee_i354()
|
| H A D | igb.h | 566 if (hw->phy.ops.write_reg) igb_write_phy_reg()
567 return hw->phy.ops.write_reg(hw, offset, data); igb_write_phy_reg()
|
| H A D | e1000_hw.h | 344 s32 (*write_reg)(struct e1000_hw *, u32, u16); member in struct:e1000_phy_operations
|
| /linux-4.1.27/drivers/net/can/c_can/ |
| H A D | c_can.c | 248 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); c_can_irq_control()
288 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); c_can_inval_tx_object()
296 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); c_can_inval_msg_object()
297 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); c_can_inval_msg_object()
333 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); c_can_setup_tx_object()
336 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, c_can_setup_tx_object()
359 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); c_can_handle_lost_msg_obj()
430 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); c_can_setup_receive_object()
511 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); c_can_set_bittiming()
516 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); c_can_set_bittiming()
517 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); c_can_set_bittiming()
518 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); c_can_set_bittiming()
559 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); c_can_chip_config()
564 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); c_can_chip_config()
565 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); c_can_chip_config()
568 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); c_can_chip_config()
569 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); c_can_chip_config()
572 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); c_can_chip_config()
573 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); c_can_chip_config()
580 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); c_can_chip_config()
625 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT); c_can_stop()
1014 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); c_can_poll()
1180 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); c_can_power_down()
1218 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); c_can_power_up()
1221 priv->write_reg(priv, C_CAN_CTRL_REG, val); c_can_power_up()
|
| H A D | c_can_pci.c | 99 priv->write_reg(priv, index + 1, val >> 16); c_can_pci_write_reg32()
100 priv->write_reg(priv, index, val); c_can_pci_write_reg32()
193 priv->write_reg = c_can_pci_write_reg_aligned_to_32bit; c_can_pci_probe()
197 priv->write_reg = c_can_pci_write_reg_aligned_to_16bit; c_can_pci_probe()
201 priv->write_reg = c_can_pci_write_reg_32bit; c_can_pci_probe()
|
| H A D | c_can_platform.c | 155 priv->write_reg(priv, index + 1, val >> 16); c_can_plat_write_reg32()
156 priv->write_reg(priv, index, val); c_can_plat_write_reg32()
308 priv->write_reg = c_can_plat_write_reg_aligned_to_32bit; c_can_plat_probe()
315 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; c_can_plat_probe()
325 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; c_can_plat_probe()
|
| H A D | c_can.h | 204 void (*write_reg) (const struct c_can_priv *priv, enum reg index, u16 val); member in struct:c_can_priv
|
| /linux-4.1.27/drivers/isdn/hardware/mISDN/ |
| H A D | hfcsusb.c | 90 static int write_reg(struct hfcsusb *hw, __u8 reg, __u8 val) write_reg() function
202 write_reg(hw, HFCUSB_P_DATA, hw->led_state); handle_led()
657 write_reg(hw, HFCUSB_STATES, 2 | HFCUSB_NT_G2_G3); ph_state_nt()
736 write_reg(hw, HFCUSB_FIFO, (bch->nr == 1) ? 0 : 2); hfcsusb_setup_bch()
737 write_reg(hw, HFCUSB_CON_HDLC, conhdlc); hfcsusb_setup_bch()
738 write_reg(hw, HFCUSB_INC_RES_F, 2); hfcsusb_setup_bch()
739 write_reg(hw, HFCUSB_FIFO, (bch->nr == 1) ? 1 : 3); hfcsusb_setup_bch()
740 write_reg(hw, HFCUSB_CON_HDLC, conhdlc); hfcsusb_setup_bch()
741 write_reg(hw, HFCUSB_INC_RES_F, 2); hfcsusb_setup_bch()
753 write_reg(hw, HFCUSB_SCTRL, sctrl); hfcsusb_setup_bch()
754 write_reg(hw, HFCUSB_SCTRL_R, sctrl_r); hfcsusb_setup_bch()
776 write_reg(hw, HFCUSB_STATES, 0x14); hfcsusb_ph_command()
778 write_reg(hw, HFCUSB_STATES, 0x04); hfcsusb_ph_command()
782 write_reg(hw, HFCUSB_STATES, 0x10); hfcsusb_ph_command()
783 write_reg(hw, HFCUSB_STATES, 0x03); hfcsusb_ph_command()
791 write_reg(hw, HFCUSB_STATES, HFCUSB_ACTIVATE | hfcsusb_ph_command()
796 write_reg(hw, HFCUSB_STATES, hfcsusb_ph_command()
1536 write_reg(hw, HFCUSB_SCTRL, 0x40); setPortMode()
1537 write_reg(hw, HFCUSB_SCTRL_E, 0x00); setPortMode()
1538 write_reg(hw, HFCUSB_CLKDEL, CLKDEL_TE); setPortMode()
1539 write_reg(hw, HFCUSB_STATES, 3 | 0x10); setPortMode()
1540 write_reg(hw, HFCUSB_STATES, 3); setPortMode()
1542 write_reg(hw, HFCUSB_SCTRL, 0x44); setPortMode()
1543 write_reg(hw, HFCUSB_SCTRL_E, 0x09); setPortMode()
1544 write_reg(hw, HFCUSB_CLKDEL, CLKDEL_NT); setPortMode()
1545 write_reg(hw, HFCUSB_STATES, 1 | 0x10); setPortMode()
1546 write_reg(hw, HFCUSB_STATES, 1); setPortMode()
1560 write_reg(hw, HFCUSB_CIRM, 8); reset_hfcsusb()
1563 write_reg(hw, HFCUSB_CIRM, 0x10); reset_hfcsusb()
1566 write_reg(hw, HFCUSB_USB_SIZE, (hw->packet_size / 8) | reset_hfcsusb()
1570 write_reg(hw, HFCUSB_USB_SIZE_I, hw->iso_packet_size); reset_hfcsusb()
1573 write_reg(hw, HFCUSB_MST_MODE1, 0); /* set default values */ reset_hfcsusb()
1574 write_reg(hw, HFCUSB_MST_MODE0, 1); /* enable master mode */ reset_hfcsusb()
1577 write_reg(hw, HFCUSB_F_THRES, reset_hfcsusb()
1582 write_reg(hw, HFCUSB_FIFO, i); /* select the desired fifo */ reset_hfcsusb()
1588 write_reg(hw, HFCUSB_HDLC_PAR, ((i <= HFCUSB_B2_RX) ? 0 : 2)); reset_hfcsusb()
1592 write_reg(hw, HFCUSB_CON_HDLC, reset_hfcsusb()
1595 write_reg(hw, HFCUSB_CON_HDLC, 0x08); reset_hfcsusb()
1596 write_reg(hw, HFCUSB_INC_RES_F, 2); /* reset the fifo */ reset_hfcsusb()
1599 write_reg(hw, HFCUSB_SCTRL_R, 0); /* disable both B receivers */ reset_hfcsusb()
|
| H A D | mISDNisar.c | 75 isar->write_reg(isar->hw, ISAR_CTRL_H, creg); send_mbox()
76 isar->write_reg(isar->hw, ISAR_CTRL_L, len); send_mbox()
77 isar->write_reg(isar->hw, ISAR_WADR, 0); send_mbox()
94 isar->write_reg(isar->hw, ISAR_HIS, his); send_mbox()
108 isar->write_reg(isar->hw, ISAR_RADR, 0); rcv_mbox()
123 isar->write_reg(isar->hw, ISAR_IIA, 0); rcv_mbox()
167 isar->write_reg(isar->hw, ISAR_IRQBIT, 0); ISARVersion()
214 isar->write_reg(isar->hw, ISAR_IRQBIT, 0); load_firmware()
323 isar->write_reg(isar->hw, ISAR_IRQBIT, ISAR_IRQSTA); load_firmware()
409 isar->write_reg(isar->hw, ISAR_IRQBIT, 0); load_firmware()
429 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
434 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
441 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
450 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
461 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
474 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
496 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
507 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
518 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
533 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
543 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
550 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
570 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
581 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0); isar_rcv_frame()
1064 isar->write_reg(isar->hw, ISAR_IIA, 0); mISDNisar_irq()
1068 isar->write_reg(isar->hw, ISAR_IIA, 0); mISDNisar_irq()
1084 isar->write_reg(isar->hw, ISAR_IIA, 0); mISDNisar_irq()
1115 isar->write_reg(isar->hw, ISAR_IIA, 0); mISDNisar_irq()
1127 isar->write_reg(isar->hw, ISAR_IIA, 0); mISDNisar_irq()
|
| H A D | mISDNinfineon.c | 488 hw->ipac.write_reg(hw, IPAC_POTA2, 0x20); ipac_chip_reset()
490 hw->ipac.write_reg(hw, IPAC_POTA2, 0x00); ipac_chip_reset()
492 hw->ipac.write_reg(hw, IPAC_CONF, hw->ipac.conf); ipac_chip_reset()
493 hw->ipac.write_reg(hw, IPAC_MASK, 0xc0); ipac_chip_reset()
534 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff); reset_inf()
535 hw->ipac.write_reg(hw, IPAC_AOE, 0x00); reset_inf()
536 hw->ipac.write_reg(hw, IPAC_PCFG, 0x12); reset_inf()
541 hw->ipac.write_reg(hw, IPAC_ACFG, 0x00); reset_inf()
542 hw->ipac.write_reg(hw, IPAC_AOE, 0x3c); reset_inf()
543 hw->ipac.write_reg(hw, IPAC_ATX, 0xff); reset_inf()
578 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff); reset_inf()
579 hw->ipac.write_reg(hw, IPAC_AOE, 0x00); reset_inf()
|
| H A D | iohelper.h | 100 dest.write_reg = &Write##name##_##typ; \
|
| H A D | ipac.h | 34 write_reg_func *write_reg; member in struct:isac_hw
77 write_reg_func *write_reg; member in struct:ipac_hw
|
| H A D | isar.h | 51 write_reg_func *write_reg; member in struct:isar_hw
|
| H A D | mISDNipac.c | 40 #define WriteISAC(is, o, v) (is->write_reg(is->dch.hw, o + is->off, v))
42 #define WriteHSCX(h, o, v) (h->ip->write_reg(h->ip->hw, h->off + o, v))
44 #define WriteIPAC(ip, o, v) (ip->write_reg(ip->hw, o, v))
|
| /linux-4.1.27/sound/ppc/ |
| H A D | snd_ps3.c | 73 static inline void write_reg(unsigned int reg, u32 val) write_reg() function
80 write_reg(reg, newval); update_reg()
85 write_reg(reg, newval); update_mask_reg()
271 write_reg(PS3_AUDIO_SOURCE(dma_ch), snd_ps3_program_dma()
277 write_reg(PS3_AUDIO_DEST(dma_ch), snd_ps3_program_dma()
281 write_reg(PS3_AUDIO_DEST(dma_ch), snd_ps3_program_dma()
286 write_reg(PS3_AUDIO_DMASIZE(dma_ch), 0); snd_ps3_program_dma()
295 write_reg(PS3_AUDIO_KICK(dma_ch), snd_ps3_program_dma()
298 write_reg(PS3_AUDIO_KICK(dma_ch), snd_ps3_program_dma()
333 write_reg(PS3_AUDIO_AX_IS, PS3_AUDIO_AX_IE_ASOBEIE(0)); snd_ps3_interrupt()
335 write_reg(PS3_AUDIO_AX_IS, port_intr); snd_ps3_interrupt()
355 write_reg(PS3_AUDIO_AX_IS, PS3_AUDIO_AX_IE_ASOBUIE(0)); snd_ps3_interrupt()
602 write_reg(PS3_AUDIO_AX_IE, snd_ps3_pcm_prepare()
893 write_reg(PS3_AUDIO_INTR_EN_0, 0); snd_ps3_audio_fixup()
|
| /linux-4.1.27/drivers/net/ethernet/realtek/ |
| H A D | atp.c | 273 write_reg(ioaddr, MODSEL, 0x00); atp_probe1()
321 write_reg(ioaddr, CMR2, CMR2_NULL); atp_probe1()
374 write_reg(ioaddr, CMR2, CMR2_EEPROM); /* Point to the EEPROM control registers. */ get_node_ID()
385 write_reg(ioaddr, CMR2, CMR2_NULL); get_node_ID()
475 write_reg(ioaddr, CMR2, CMR2_IRQOUT); hardware_init()
482 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK); hardware_init()
493 write_reg(ioaddr, TxCNT1, length >> 8); trigger_send()
494 write_reg(ioaddr, CMR1, CMR1_Xmit); trigger_send()
568 write_reg(ioaddr, IMR, 0); atp_send_packet()
583 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK); atp_send_packet()
611 write_reg(ioaddr, CMR2, CMR2_NULL); atp_interrupt()
612 write_reg(ioaddr, IMR, 0); atp_interrupt()
621 write_reg(ioaddr, ISR, ISR_RxOK); /* Clear the Rx interrupt. */ atp_interrupt()
647 write_reg(ioaddr, ISR, ISR_TxErr + ISR_TxOK); atp_interrupt()
657 write_reg(ioaddr, CMR1, CMR1_ReXmit + CMR1_Xmit); atp_interrupt()
698 write_reg(ioaddr, CMR2, CMR2_IRQOUT); atp_interrupt()
702 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK); atp_interrupt()
798 write_reg(ioaddr, CMR1, CMR1_NextPkt); net_rx()
|
| H A D | atp.h | 158 write_reg(short port, unsigned char reg, unsigned char value) write_reg() function
|
| /linux-4.1.27/drivers/media/usb/dvb-usb-v2/ |
| H A D | mxl111sf-demod.h | 30 int (*write_reg)(struct mxl111sf_state *state, u8 addr, u8 data); member in struct:mxl111sf_demod_config
|
| H A D | mxl111sf-tuner.h | 54 int (*write_reg)(struct mxl111sf_state *state, u8 addr, u8 data); member in struct:mxl111sf_tuner_config
|
| H A D | mxl111sf-demod.c | 56 return (state->cfg->write_reg) ? mxl111sf_demod_write_reg()
57 state->cfg->write_reg(state->mxl_state, addr, data) : mxl111sf_demod_write_reg()
|
| H A D | mxl111sf-tuner.c | 58 return (state->cfg->write_reg) ? mxl111sf_tuner_write_reg()
59 state->cfg->write_reg(state->mxl_state, addr, data) : mxl111sf_tuner_write_reg()
|
| H A D | mxl111sf.c | 736 .write_reg = mxl111sf_write_reg,
862 .write_reg = mxl111sf_write_reg,
|
| /linux-4.1.27/include/video/ |
| H A D | broadsheetfb.h | 49 void (*write_reg)(struct broadsheetfb_par *, u16 reg, u16 val); member in struct:broadsheetfb_par
|
| /linux-4.1.27/drivers/media/usb/go7007/ |
| H A D | s2250-board.c | 159 static int write_reg(struct i2c_client *client, u8 reg, u8 value) write_reg() function
303 if (write_reg(client, regs[i], regs[i+1]) < 0) { write_regs()
431 write_reg(state->audio, 0x08, 0x02); /* Line In */ s2250_s_audio_routing()
434 write_reg(state->audio, 0x08, 0x04); /* Mic */ s2250_s_audio_routing()
437 write_reg(state->audio, 0x08, 0x05); /* Mic Boost */ s2250_s_audio_routing()
567 write_reg(client, 0x08, 0x02); /* Line In */ s2250_probe()
|
| /linux-4.1.27/drivers/block/paride/ |
| H A D | pt.c | 261 static inline void write_reg(struct pi_adapter *pi, int reg, int val) write_reg() function
301 write_reg(pi, 6, DRIVE(tape)); pt_command()
308 write_reg(pi, 4, dlen % 256); pt_command()
309 write_reg(pi, 5, dlen / 256); pt_command()
310 write_reg(pi, 7, 0xa0); /* ATAPI packet command */ pt_command()
405 write_reg(pi, 6, DRIVE(tape)); pt_poll_dsc()
457 write_reg(pi, 6, DRIVE(tape)); pt_reset()
458 write_reg(pi, 7, 8); pt_reset()
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| H A D | pcd.c | 348 static inline void write_reg(struct pcd_unit *cd, int reg, int val) write_reg() function
381 write_reg(cd, 6, 0xa0 + 0x10 * cd->drive); pcd_command()
388 write_reg(cd, 4, dlen % 256); pcd_command()
389 write_reg(cd, 5, dlen / 256); pcd_command()
390 write_reg(cd, 7, 0xa0); /* ATAPI packet command */ pcd_command()
544 write_reg(cd, 6, 0xa0 + 0x10 * cd->drive); pcd_reset()
545 write_reg(cd, 7, 8); pcd_reset()
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| H A D | pg.c | 272 static inline void write_reg(struct pg *dev, int reg, int val) write_reg() function
325 write_reg(dev, 6, DRIVE(dev)); pg_command()
330 write_reg(dev, 4, dlen % 256); pg_command()
331 write_reg(dev, 5, dlen / 256); pg_command()
332 write_reg(dev, 7, 0xa0); /* ATAPI packet command */ pg_command()
394 write_reg(dev, 6, DRIVE(dev)); pg_reset()
395 write_reg(dev, 7, 8); pg_reset()
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| H A D | pd.c | 265 static inline void write_reg(struct pd_unit *disk, int reg, int val) write_reg() function
320 write_reg(disk, 6, DRIVE(disk) + h); pd_send_command()
321 write_reg(disk, 1, 0); /* the IDE task file */ pd_send_command()
322 write_reg(disk, 2, n); pd_send_command()
323 write_reg(disk, 3, s); pd_send_command()
324 write_reg(disk, 4, c0); pd_send_command()
325 write_reg(disk, 5, c1); pd_send_command()
326 write_reg(disk, 7, func); pd_send_command()
664 write_reg(disk, 6, DRIVE(disk)); pd_identify()
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| H A D | pf.c | 397 static inline void write_reg(struct pf_unit *pf, int reg, int val) write_reg() function
430 write_reg(pf, 6, 0xa0+0x10*pf->drive); pf_command()
437 write_reg(pf, 4, dlen % 256); pf_command()
438 write_reg(pf, 5, dlen / 256); pf_command()
439 write_reg(pf, 7, 0xa0); /* ATAPI packet command */ pf_command()
541 write_reg(pf, 6, 0xa0+0x10*pf->drive); pf_reset()
542 write_reg(pf, 7, 8); pf_reset()
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| /linux-4.1.27/arch/sh/boards/mach-migor/ |
| H A D | lcd_qvga.c | 52 static void write_reg(void *sys_ops_handle, write_reg() function
163 write_reg(sohandle, so, 0x00, 0x22); migor_lcd_qvga_setup()
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| /linux-4.1.27/drivers/char/pcmcia/ |
| H A D | synclink_cs.c | 321 #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg)) macro
328 write_reg(info, (reg), \
331 write_reg(info, (reg), \
358 { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
361 { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
701 write_reg(info, (unsigned char) (channel + CMDR), cmd); issue_command()
1025 write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get)); tx_ready()
1888 write_reg(info, PVR, val); set_interface()
2930 write_reg(info, (unsigned char) (channel + BGR), mgslpc_set_rate()
2934 write_reg(info, (unsigned char) (channel + CCR2), val); mgslpc_set_rate()
2961 write_reg(info, CHB + MODE, val); enable_auxclk()
2973 write_reg(info, CHB + CCR0, 0xc0); enable_auxclk()
2986 write_reg(info, CHB + CCR1, 0x17); enable_auxclk()
3001 write_reg(info, CHB + CCR2, 0x38); enable_auxclk()
3003 write_reg(info, CHB + CCR2, 0x30); enable_auxclk()
3016 write_reg(info, CHB + CCR4, 0x50); enable_auxclk()
3033 write_reg(info, CHA + CCR1, val); loopback_enable()
3037 write_reg(info, CHA + CCR2, val); loopback_enable()
3047 write_reg(info, CHA + MODE, val); loopback_enable()
3104 write_reg(info, CHA + MODE, val); hdlc_mode()
3132 write_reg(info, CHA + CCR0, val); hdlc_mode()
3146 write_reg(info, CHA + CCR1, val); hdlc_mode()
3170 write_reg(info, CHA + CCR2, val); hdlc_mode()
3201 write_reg(info, CHA + CCR3, val); hdlc_mode()
3212 write_reg(info, CHA + PRE, val); hdlc_mode()
3226 write_reg(info, CHA + CCR4, val); hdlc_mode()
3237 write_reg(info, CHA + RLCR, 0); hdlc_mode()
3252 write_reg(info, CHA + XBCH, val); hdlc_mode()
3374 write_reg(info, CHA + CCR0, 0x80); reset_device()
3375 write_reg(info, CHB + CCR0, 0x80); reset_device()
3376 write_reg(info, CHA + MODE, 0); reset_device()
3377 write_reg(info, CHB + MODE, 0); reset_device()
3394 write_reg(info, PCR, 0x06); reset_device()
3406 // write_reg(info, PVR, PVR_DTR); reset_device()
3418 write_reg(info, IPC, 0x05); reset_device()
3450 write_reg(info, CHA + MODE, val); async_mode()
3462 write_reg(info, CHA + CCR0, 0x83); async_mode()
3473 write_reg(info, CHA + CCR1, 0x1f); async_mode()
3487 write_reg(info, CHA + CCR2, 0x10); async_mode()
3496 write_reg(info, CHA + CCR3, 0); async_mode()
3508 write_reg(info, CHA + CCR4, 0x50); async_mode()
3534 write_reg(info, CHA + DAFO, val); async_mode()
3548 write_reg(info, CHA + RFC, 0x5c); async_mode()
3554 write_reg(info, CHA + RLCR, 0); async_mode()
3569 write_reg(info, CHA + XBCH, val); async_mode()
3641 write_reg(info, CHA + MODE, val); set_signals()
3765 write_reg(info, XAD1, patterns[i]); register_test()
3766 write_reg(info, XAD2, patterns[(i + 1) % count]); register_test()
3794 write_reg(info, CHA + TIMR, 0); /* 512 cycles */ irq_test()
|
| /linux-4.1.27/include/linux/ |
| H A D | basic_mmio_gpio.h | 33 void (*write_reg)(void __iomem *reg, unsigned long data); member in struct:bgpio_chip
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| /linux-4.1.27/include/linux/mtd/ |
| H A D | spi-nor.h | 145 * @cmd_buf: used by the write_reg
153 * @write_reg: [DRIVER-SPECIFIC] write data to the register
185 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len, member in struct:spi_nor
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| /linux-4.1.27/drivers/net/irda/ |
| H A D | stir4200.c | 194 static int write_reg(struct stir_cb *stir, __u16 reg, __u8 value) write_reg() function
516 err = write_reg(stir, REG_CTRL1, CTRL1_SRESET); change_speed()
521 err = write_reg(stir, REG_DPLL, 0x15); change_speed()
526 err = write_reg(stir, REG_PDCLK, stir_modes[i].pdclk); change_speed()
539 err = write_reg(stir, REG_MODE, mode); change_speed()
544 err = write_reg(stir, REG_CTRL1, change_speed()
549 err = write_reg(stir, REG_CTRL1, (tx_power & 3) << 1); change_speed()
554 err = write_reg(stir, REG_CTRL2, (rx_sensitivity & 7) << 5); change_speed()
639 err = write_reg(stir, REG_FIFOCTL, FIFOCTL_CLR); fifo_txwait()
642 err = write_reg(stir, REG_FIFOCTL, 0); fifo_txwait()
748 write_reg(stir, REG_CTRL1, CTRL1_TXPWD|CTRL1_RXPWD); stir_transmit_thread()
|
| /linux-4.1.27/drivers/media/platform/ti-vpe/ |
| H A D | vpdma.c | 247 static void write_reg(struct vpdma_data *vpdma, int offset, u32 value) write_reg() function
266 write_reg(vpdma, offset, val); write_field_reg()
440 write_reg(vpdma, VPDMA_LIST_ADDR, (u32) list->buf.dma_addr); vpdma_submit_descs()
442 write_reg(vpdma, VPDMA_LIST_ATTR, vpdma_submit_descs()
762 write_reg(vpdma, VPDMA_INT_LIST0_MASK, val); vpdma_enable_list_complete_irq()
768 write_reg(vpdma, VPDMA_INT_LIST0_STAT, vpdma_clear_list_stat()
831 write_reg(vpdma, VPDMA_LIST_ADDR, (u32) fw_dma_buf.dma_addr); vpdma_firmware_cb()
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| H A D | vpe.c | 430 static void write_reg(struct vpe_dev *dev, int offset, u32 value) write_reg() function
462 write_reg(dev, offset, val); write_field_reg()
602 write_reg(dev, VPE_CLK_ENABLE, val); vpe_set_clock_enable()
1076 write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE); enable_irqs()
1077 write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT | enable_irqs()
1085 write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff); disable_irqs()
1086 write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff); disable_irqs()
1232 write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0); vpe_irq()
1238 write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1); vpe_irq()
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| /linux-4.1.27/drivers/mtd/spi-nor/ |
| H A D | spi-nor.c | 146 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); write_sr()
155 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); write_enable()
163 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0); write_disable()
189 status = nor->write_reg(nor, cmd, NULL, 0, 0); set_4byte()
197 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0); set_4byte()
268 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0); erase_chip()
861 nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); macronix_quad_enable()
886 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0); write_sr_cr()
928 ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0); micron_quad_enable()
984 !nor->read_reg || !nor->write_reg || !nor->erase) { spi_nor_check()
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| H A D | fsl-quadspi.c | 885 nor->write_reg = fsl_qspi_write_reg; fsl_qspi_probe()
|
| /linux-4.1.27/drivers/net/can/cc770/ |
| H A D | cc770_isa.c | 214 priv->write_reg = cc770_isa_mem_write_reg; cc770_isa_probe()
221 priv->write_reg = cc770_isa_port_write_reg_indirect; cc770_isa_probe()
224 priv->write_reg = cc770_isa_port_write_reg; cc770_isa_probe()
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| H A D | cc770.h | 152 priv->write_reg(priv, offsetof(struct cc770_regs, member), value)
181 void (*write_reg)(const struct cc770_priv *priv, int reg, u8 val); member in struct:cc770_priv
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| H A D | cc770_platform.c | 200 priv->write_reg = cc770_platform_write_reg; cc770_platform_probe()
|
| /linux-4.1.27/drivers/net/ethernet/intel/ixgbe/ |
| H A D | ixgbe_phy.c | 396 hw->phy.ops.write_reg(hw, MDIO_CTRL1, ixgbe_reset_phy_generic()
650 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, ixgbe_setup_phy_link_generic()
666 hw->phy.ops.write_reg(hw, ixgbe_setup_phy_link_generic()
683 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, ixgbe_setup_phy_link_generic()
698 hw->phy.ops.write_reg(hw, MDIO_CTRL1, ixgbe_setup_phy_link_generic()
847 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, ixgbe_setup_phy_link_tnx()
862 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, ixgbe_setup_phy_link_tnx()
878 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, ixgbe_setup_phy_link_tnx()
893 hw->phy.ops.write_reg(hw, MDIO_CTRL1, ixgbe_setup_phy_link_tnx()
952 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, ixgbe_reset_phy_nl()
1004 hw->phy.ops.write_reg(hw, phy_offset, ixgbe_reset_phy_nl()
|
| H A D | ixgbe_x550.c | 1129 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; ixgbe_init_phy_ops_X550em()
1134 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; ixgbe_init_phy_ops_X550em()
1220 status = hw->phy.ops.write_reg(hw, ixgbe_init_ext_t_x550em()
1237 status = hw->phy.ops.write_reg(hw, ixgbe_init_ext_t_x550em()
1501 .write_reg = &ixgbe_write_phy_reg_generic,
1512 .write_reg = NULL, /* defined later */
|
| H A D | ixgbe_x540.c | 844 .write_reg = &ixgbe_write_phy_reg_generic,
|
| H A D | ixgbe_82598.c | 1221 .write_reg = &ixgbe_write_phy_reg_generic,
|
| H A D | ixgbe_82599.c | 2363 .write_reg = &ixgbe_write_phy_reg_generic,
|
| H A D | ixgbe_common.c | 251 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, ixgbe_setup_fc()
|
| H A D | ixgbe_type.h | 3099 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); member in struct:ixgbe_phy_operations
|
| H A D | ixgbe_main.c | 7489 return hw->phy.ops.write_reg(hw, addr, devad, value); ixgbe_mdio_write()
|
| /linux-4.1.27/drivers/mtd/onenand/ |
| H A D | omap2.c | 87 static inline void write_reg(struct omap2_onenand *c, unsigned short value, write_reg() function
155 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1); omap2_onenand_wait()
205 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1); omap2_onenand_wait()
|
| /linux-4.1.27/drivers/mtd/devices/ |
| H A D | m25p80.c | 200 nor->write_reg = m25p80_write_reg; m25p_probe()
|
| /linux-4.1.27/drivers/power/ |
| H A D | ltc2941-battery-gauge.c | 126 dev_err(&client->dev, "ltc2941 write_reg failed!\n"); ltc294x_write_regs()
|
| /linux-4.1.27/drivers/net/ethernet/intel/e1000e/ |
| H A D | e1000.h | 530 return hw->phy.ops.write_reg(hw, offset, data); e1e_wphy()
|
| H A D | hw.h | 515 s32 (*write_reg)(struct e1000_hw *, u32, u16); member in struct:e1000_phy_operations
|
| H A D | 82571.c | 1912 .write_reg = e1000e_write_phy_reg_igp,
1930 .write_reg = e1000e_write_phy_reg_m88,
1948 .write_reg = e1000e_write_phy_reg_bm2,
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| H A D | 80003es2lan.c | 1385 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
|
| H A D | ich8lan.c | 450 phy->ops.write_reg = e1000_write_phy_reg_hv; e1000_init_phy_params_pchlan()
536 phy->ops.write_reg = e1000e_write_phy_reg_bm; e1000_init_phy_params_ich8lan()
578 phy->ops.write_reg = e1000e_write_phy_reg_bm; e1000_init_phy_params_ich8lan()
5650 .write_reg = e1000e_write_phy_reg_igp,
|
| /linux-4.1.27/drivers/media/dvb-frontends/ |
| H A D | l64781.c | 59 dprintk ("%s: write_reg error (reg == %02x) = %02x!\n", l64781_writereg()
|
| /linux-4.1.27/drivers/pinctrl/sh-pfc/ |
| H A D | core.c | 211 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, " sh_pfc_write_config_reg()
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| /linux-4.1.27/drivers/staging/rtl8188eu/os_dep/ |
| H A D | os_intfs.c | 225 entry = create_proc_read_entry("write_reg", S_IFREG | S_IRUGO,
459 remove_proc_entry("write_reg", dir_dev);
|
| /linux-4.1.27/drivers/net/ethernet/qlogic/qlcnic/ |
| H A D | qlcnic.h | 1558 adapter->ahw->hw_ops->write_reg(adapter, off, val)
1774 int (*write_reg) (struct qlcnic_adapter *, ulong, u32); member in struct:qlcnic_hardware_ops
1867 return adapter->ahw->hw_ops->write_reg(adapter, off, data); qlcnic_hw_write_wx_2M()
|
| H A D | qlcnic_sriov_common.c | 49 .write_reg = qlcnic_83xx_wrt_reg_indirect,
|
| H A D | qlcnic_83xx_hw.c | 199 .write_reg = qlcnic_83xx_wrt_reg_indirect,
|
| H A D | qlcnic_main.c | 578 .write_reg = qlcnic_82xx_hw_write_wx_2M,
|
| /linux-4.1.27/drivers/staging/rtl8188eu/core/ |
| H A D | rtw_debug.c | 62 DBG_88E("invalid write_reg parameter!\n"); proc_set_write_reg()
|
| /linux-4.1.27/drivers/video/fbdev/ |
| H A D | broadsheetfb.c | 1126 par->write_reg = broadsheet_write_reg; broadsheetfb_probe()
|
| /linux-4.1.27/drivers/net/ethernet/tehuti/ |
| H A D | tehuti.c | 681 DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]); bdx_ioctl_priv()
|