1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38#include <linux/pinctrl/consumer.h> 39 40#include <linux/can.h> 41#include <linux/can/dev.h> 42#include <linux/can/error.h> 43#include <linux/can/led.h> 44 45#include "c_can.h" 46 47/* Number of interface registers */ 48#define IF_ENUM_REG_LEN 11 49#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 50 51/* control extension register D_CAN specific */ 52#define CONTROL_EX_PDR BIT(8) 53 54/* control register */ 55#define CONTROL_TEST BIT(7) 56#define CONTROL_CCE BIT(6) 57#define CONTROL_DISABLE_AR BIT(5) 58#define CONTROL_ENABLE_AR (0 << 5) 59#define CONTROL_EIE BIT(3) 60#define CONTROL_SIE BIT(2) 61#define CONTROL_IE BIT(1) 62#define CONTROL_INIT BIT(0) 63 64#define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE) 65 66/* test register */ 67#define TEST_RX BIT(7) 68#define TEST_TX1 BIT(6) 69#define TEST_TX2 BIT(5) 70#define TEST_LBACK BIT(4) 71#define TEST_SILENT BIT(3) 72#define TEST_BASIC BIT(2) 73 74/* status register */ 75#define STATUS_PDA BIT(10) 76#define STATUS_BOFF BIT(7) 77#define STATUS_EWARN BIT(6) 78#define STATUS_EPASS BIT(5) 79#define STATUS_RXOK BIT(4) 80#define STATUS_TXOK BIT(3) 81 82/* error counter register */ 83#define ERR_CNT_TEC_MASK 0xff 84#define ERR_CNT_TEC_SHIFT 0 85#define ERR_CNT_REC_SHIFT 8 86#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 87#define ERR_CNT_RP_SHIFT 15 88#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 89 90/* bit-timing register */ 91#define BTR_BRP_MASK 0x3f 92#define BTR_BRP_SHIFT 0 93#define BTR_SJW_SHIFT 6 94#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 95#define BTR_TSEG1_SHIFT 8 96#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 97#define BTR_TSEG2_SHIFT 12 98#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 99 100/* brp extension register */ 101#define BRP_EXT_BRPE_MASK 0x0f 102#define BRP_EXT_BRPE_SHIFT 0 103 104/* IFx command request */ 105#define IF_COMR_BUSY BIT(15) 106 107/* IFx command mask */ 108#define IF_COMM_WR BIT(7) 109#define IF_COMM_MASK BIT(6) 110#define IF_COMM_ARB BIT(5) 111#define IF_COMM_CONTROL BIT(4) 112#define IF_COMM_CLR_INT_PND BIT(3) 113#define IF_COMM_TXRQST BIT(2) 114#define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST 115#define IF_COMM_DATAA BIT(1) 116#define IF_COMM_DATAB BIT(0) 117 118/* TX buffer setup */ 119#define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \ 120 IF_COMM_TXRQST | \ 121 IF_COMM_DATAA | IF_COMM_DATAB) 122 123/* For the low buffers we clear the interrupt bit, but keep newdat */ 124#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 125 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 126 IF_COMM_DATAA | IF_COMM_DATAB) 127 128/* For the high buffers we clear the interrupt bit and newdat */ 129#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT) 130 131 132/* Receive setup of message objects */ 133#define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL) 134 135/* Invalidation of message objects */ 136#define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL) 137 138/* IFx arbitration */ 139#define IF_ARB_MSGVAL BIT(31) 140#define IF_ARB_MSGXTD BIT(30) 141#define IF_ARB_TRANSMIT BIT(29) 142 143/* IFx message control */ 144#define IF_MCONT_NEWDAT BIT(15) 145#define IF_MCONT_MSGLST BIT(14) 146#define IF_MCONT_INTPND BIT(13) 147#define IF_MCONT_UMASK BIT(12) 148#define IF_MCONT_TXIE BIT(11) 149#define IF_MCONT_RXIE BIT(10) 150#define IF_MCONT_RMTEN BIT(9) 151#define IF_MCONT_TXRQST BIT(8) 152#define IF_MCONT_EOB BIT(7) 153#define IF_MCONT_DLC_MASK 0xf 154 155#define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK) 156#define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB) 157 158#define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB) 159 160/* 161 * Use IF1 for RX and IF2 for TX 162 */ 163#define IF_RX 0 164#define IF_TX 1 165 166/* minimum timeout for checking BUSY status */ 167#define MIN_TIMEOUT_VALUE 6 168 169/* Wait for ~1 sec for INIT bit */ 170#define INIT_WAIT_MS 1000 171 172/* napi related */ 173#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 174 175/* c_can lec values */ 176enum c_can_lec_type { 177 LEC_NO_ERROR = 0, 178 LEC_STUFF_ERROR, 179 LEC_FORM_ERROR, 180 LEC_ACK_ERROR, 181 LEC_BIT1_ERROR, 182 LEC_BIT0_ERROR, 183 LEC_CRC_ERROR, 184 LEC_UNUSED, 185 LEC_MASK = LEC_UNUSED, 186}; 187 188/* 189 * c_can error types: 190 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 191 */ 192enum c_can_bus_error_types { 193 C_CAN_NO_ERROR = 0, 194 C_CAN_BUS_OFF, 195 C_CAN_ERROR_WARNING, 196 C_CAN_ERROR_PASSIVE, 197}; 198 199static const struct can_bittiming_const c_can_bittiming_const = { 200 .name = KBUILD_MODNAME, 201 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 202 .tseg1_max = 16, 203 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 204 .tseg2_max = 8, 205 .sjw_max = 4, 206 .brp_min = 1, 207 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 208 .brp_inc = 1, 209}; 210 211static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 212{ 213 if (priv->device) 214 pm_runtime_enable(priv->device); 215} 216 217static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 218{ 219 if (priv->device) 220 pm_runtime_disable(priv->device); 221} 222 223static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 224{ 225 if (priv->device) 226 pm_runtime_get_sync(priv->device); 227} 228 229static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 230{ 231 if (priv->device) 232 pm_runtime_put_sync(priv->device); 233} 234 235static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 236{ 237 if (priv->raminit) 238 priv->raminit(priv, enable); 239} 240 241static void c_can_irq_control(struct c_can_priv *priv, bool enable) 242{ 243 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK; 244 245 if (enable) 246 ctrl |= CONTROL_IRQMSK; 247 248 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); 249} 250 251static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj) 252{ 253 struct c_can_priv *priv = netdev_priv(dev); 254 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface); 255 256 priv->write_reg32(priv, reg, (cmd << 16) | obj); 257 258 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) { 259 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) 260 return; 261 udelay(1); 262 } 263 netdev_err(dev, "Updating object timed out\n"); 264 265} 266 267static inline void c_can_object_get(struct net_device *dev, int iface, 268 u32 obj, u32 cmd) 269{ 270 c_can_obj_update(dev, iface, cmd, obj); 271} 272 273static inline void c_can_object_put(struct net_device *dev, int iface, 274 u32 obj, u32 cmd) 275{ 276 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj); 277} 278 279/* 280 * Note: According to documentation clearing TXIE while MSGVAL is set 281 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O 282 * load significantly. 283 */ 284static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj) 285{ 286 struct c_can_priv *priv = netdev_priv(dev); 287 288 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 289 c_can_object_put(dev, iface, obj, IF_COMM_INVAL); 290} 291 292static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj) 293{ 294 struct c_can_priv *priv = netdev_priv(dev); 295 296 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 297 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 298 c_can_inval_tx_object(dev, iface, obj); 299} 300 301static void c_can_setup_tx_object(struct net_device *dev, int iface, 302 struct can_frame *frame, int idx) 303{ 304 struct c_can_priv *priv = netdev_priv(dev); 305 u16 ctrl = IF_MCONT_TX | frame->can_dlc; 306 bool rtr = frame->can_id & CAN_RTR_FLAG; 307 u32 arb = IF_ARB_MSGVAL; 308 int i; 309 310 if (frame->can_id & CAN_EFF_FLAG) { 311 arb |= frame->can_id & CAN_EFF_MASK; 312 arb |= IF_ARB_MSGXTD; 313 } else { 314 arb |= (frame->can_id & CAN_SFF_MASK) << 18; 315 } 316 317 if (!rtr) 318 arb |= IF_ARB_TRANSMIT; 319 320 /* 321 * If we change the DIR bit, we need to invalidate the buffer 322 * first, i.e. clear the MSGVAL flag in the arbiter. 323 */ 324 if (rtr != (bool)test_bit(idx, &priv->tx_dir)) { 325 u32 obj = idx + C_CAN_MSG_OBJ_TX_FIRST; 326 327 c_can_inval_msg_object(dev, iface, obj); 328 change_bit(idx, &priv->tx_dir); 329 } 330 331 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb); 332 333 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 334 335 for (i = 0; i < frame->can_dlc; i += 2) { 336 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 337 frame->data[i] | (frame->data[i + 1] << 8)); 338 } 339} 340 341static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 342 int iface) 343{ 344 int i; 345 346 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) 347 c_can_object_get(dev, iface, i, IF_COMM_CLR_NEWDAT); 348} 349 350static int c_can_handle_lost_msg_obj(struct net_device *dev, 351 int iface, int objno, u32 ctrl) 352{ 353 struct net_device_stats *stats = &dev->stats; 354 struct c_can_priv *priv = netdev_priv(dev); 355 struct can_frame *frame; 356 struct sk_buff *skb; 357 358 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 359 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 360 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 361 362 stats->rx_errors++; 363 stats->rx_over_errors++; 364 365 /* create an error msg */ 366 skb = alloc_can_err_skb(dev, &frame); 367 if (unlikely(!skb)) 368 return 0; 369 370 frame->can_id |= CAN_ERR_CRTL; 371 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 372 373 netif_receive_skb(skb); 374 return 1; 375} 376 377static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl) 378{ 379 struct net_device_stats *stats = &dev->stats; 380 struct c_can_priv *priv = netdev_priv(dev); 381 struct can_frame *frame; 382 struct sk_buff *skb; 383 u32 arb, data; 384 385 skb = alloc_can_skb(dev, &frame); 386 if (!skb) { 387 stats->rx_dropped++; 388 return -ENOMEM; 389 } 390 391 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 392 393 arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface)); 394 395 if (arb & IF_ARB_MSGXTD) 396 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG; 397 else 398 frame->can_id = (arb >> 18) & CAN_SFF_MASK; 399 400 if (arb & IF_ARB_TRANSMIT) { 401 frame->can_id |= CAN_RTR_FLAG; 402 } else { 403 int i, dreg = C_CAN_IFACE(DATA1_REG, iface); 404 405 for (i = 0; i < frame->can_dlc; i += 2, dreg ++) { 406 data = priv->read_reg(priv, dreg); 407 frame->data[i] = data; 408 frame->data[i + 1] = data >> 8; 409 } 410 } 411 412 stats->rx_packets++; 413 stats->rx_bytes += frame->can_dlc; 414 415 netif_receive_skb(skb); 416 return 0; 417} 418 419static void c_can_setup_receive_object(struct net_device *dev, int iface, 420 u32 obj, u32 mask, u32 id, u32 mcont) 421{ 422 struct c_can_priv *priv = netdev_priv(dev); 423 424 mask |= BIT(29); 425 priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask); 426 427 id |= IF_ARB_MSGVAL; 428 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id); 429 430 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 431 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP); 432} 433 434static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 435 struct net_device *dev) 436{ 437 struct can_frame *frame = (struct can_frame *)skb->data; 438 struct c_can_priv *priv = netdev_priv(dev); 439 u32 idx, obj; 440 441 if (can_dropped_invalid_skb(dev, skb)) 442 return NETDEV_TX_OK; 443 /* 444 * This is not a FIFO. C/D_CAN sends out the buffers 445 * prioritized. The lowest buffer number wins. 446 */ 447 idx = fls(atomic_read(&priv->tx_active)); 448 obj = idx + C_CAN_MSG_OBJ_TX_FIRST; 449 450 /* If this is the last buffer, stop the xmit queue */ 451 if (idx == C_CAN_MSG_OBJ_TX_NUM - 1) 452 netif_stop_queue(dev); 453 /* 454 * Store the message in the interface so we can call 455 * can_put_echo_skb(). We must do this before we enable 456 * transmit as we might race against do_tx(). 457 */ 458 c_can_setup_tx_object(dev, IF_TX, frame, idx); 459 priv->dlc[idx] = frame->can_dlc; 460 can_put_echo_skb(skb, dev, idx); 461 462 /* Update the active bits */ 463 atomic_add((1 << idx), &priv->tx_active); 464 /* Start transmission */ 465 c_can_object_put(dev, IF_TX, obj, IF_COMM_TX); 466 467 return NETDEV_TX_OK; 468} 469 470static int c_can_wait_for_ctrl_init(struct net_device *dev, 471 struct c_can_priv *priv, u32 init) 472{ 473 int retry = 0; 474 475 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 476 udelay(10); 477 if (retry++ > 1000) { 478 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 479 return -EIO; 480 } 481 } 482 return 0; 483} 484 485static int c_can_set_bittiming(struct net_device *dev) 486{ 487 unsigned int reg_btr, reg_brpe, ctrl_save; 488 u8 brp, brpe, sjw, tseg1, tseg2; 489 u32 ten_bit_brp; 490 struct c_can_priv *priv = netdev_priv(dev); 491 const struct can_bittiming *bt = &priv->can.bittiming; 492 int res; 493 494 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 495 ten_bit_brp = bt->brp - 1; 496 brp = ten_bit_brp & BTR_BRP_MASK; 497 brpe = ten_bit_brp >> 6; 498 499 sjw = bt->sjw - 1; 500 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 501 tseg2 = bt->phase_seg2 - 1; 502 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 503 (tseg2 << BTR_TSEG2_SHIFT); 504 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 505 506 netdev_info(dev, 507 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 508 509 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 510 ctrl_save &= ~CONTROL_INIT; 511 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 512 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 513 if (res) 514 return res; 515 516 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 517 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 518 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 519 520 return c_can_wait_for_ctrl_init(dev, priv, 0); 521} 522 523/* 524 * Configure C_CAN message objects for Tx and Rx purposes: 525 * C_CAN provides a total of 32 message objects that can be configured 526 * either for Tx or Rx purposes. Here the first 16 message objects are used as 527 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 528 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 529 * See user guide document for further details on configuring message 530 * objects. 531 */ 532static void c_can_configure_msg_objects(struct net_device *dev) 533{ 534 int i; 535 536 /* first invalidate all message objects */ 537 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 538 c_can_inval_msg_object(dev, IF_RX, i); 539 540 /* setup receive message objects */ 541 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 542 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV); 543 544 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 545 IF_MCONT_RCV_EOB); 546} 547 548/* 549 * Configure C_CAN chip: 550 * - enable/disable auto-retransmission 551 * - set operating mode 552 * - configure message objects 553 */ 554static int c_can_chip_config(struct net_device *dev) 555{ 556 struct c_can_priv *priv = netdev_priv(dev); 557 558 /* enable automatic retransmission */ 559 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); 560 561 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 562 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 563 /* loopback + silent mode : useful for hot self-test */ 564 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 565 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); 566 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 567 /* loopback mode : useful for self-test function */ 568 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 569 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 570 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 571 /* silent mode : bus-monitoring mode */ 572 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 573 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 574 } 575 576 /* configure message objects */ 577 c_can_configure_msg_objects(dev); 578 579 /* set a `lec` value so that we can check for updates later */ 580 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 581 582 /* Clear all internal status */ 583 atomic_set(&priv->tx_active, 0); 584 priv->rxmasked = 0; 585 priv->tx_dir = 0; 586 587 /* set bittiming params */ 588 return c_can_set_bittiming(dev); 589} 590 591static int c_can_start(struct net_device *dev) 592{ 593 struct c_can_priv *priv = netdev_priv(dev); 594 int err; 595 struct pinctrl *p; 596 597 /* basic c_can configuration */ 598 err = c_can_chip_config(dev); 599 if (err) 600 return err; 601 602 /* Setup the command for new messages */ 603 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ? 604 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 605 606 priv->can.state = CAN_STATE_ERROR_ACTIVE; 607 608 /* Attempt to use "active" if available else use "default" */ 609 p = pinctrl_get_select(priv->device, "active"); 610 if (!IS_ERR(p)) 611 pinctrl_put(p); 612 else 613 pinctrl_pm_select_default_state(priv->device); 614 615 return 0; 616} 617 618static void c_can_stop(struct net_device *dev) 619{ 620 struct c_can_priv *priv = netdev_priv(dev); 621 622 c_can_irq_control(priv, false); 623 624 /* put ctrl to init on stop to end ongoing transmission */ 625 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT); 626 627 /* deactivate pins */ 628 pinctrl_pm_select_sleep_state(dev->dev.parent); 629 priv->can.state = CAN_STATE_STOPPED; 630} 631 632static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 633{ 634 struct c_can_priv *priv = netdev_priv(dev); 635 int err; 636 637 switch (mode) { 638 case CAN_MODE_START: 639 err = c_can_start(dev); 640 if (err) 641 return err; 642 netif_wake_queue(dev); 643 c_can_irq_control(priv, true); 644 break; 645 default: 646 return -EOPNOTSUPP; 647 } 648 649 return 0; 650} 651 652static int __c_can_get_berr_counter(const struct net_device *dev, 653 struct can_berr_counter *bec) 654{ 655 unsigned int reg_err_counter; 656 struct c_can_priv *priv = netdev_priv(dev); 657 658 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 659 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 660 ERR_CNT_REC_SHIFT; 661 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 662 663 return 0; 664} 665 666static int c_can_get_berr_counter(const struct net_device *dev, 667 struct can_berr_counter *bec) 668{ 669 struct c_can_priv *priv = netdev_priv(dev); 670 int err; 671 672 c_can_pm_runtime_get_sync(priv); 673 err = __c_can_get_berr_counter(dev, bec); 674 c_can_pm_runtime_put_sync(priv); 675 676 return err; 677} 678 679static void c_can_do_tx(struct net_device *dev) 680{ 681 struct c_can_priv *priv = netdev_priv(dev); 682 struct net_device_stats *stats = &dev->stats; 683 u32 idx, obj, pkts = 0, bytes = 0, pend, clr; 684 685 clr = pend = priv->read_reg(priv, C_CAN_INTPND2_REG); 686 687 while ((idx = ffs(pend))) { 688 idx--; 689 pend &= ~(1 << idx); 690 obj = idx + C_CAN_MSG_OBJ_TX_FIRST; 691 c_can_inval_tx_object(dev, IF_RX, obj); 692 can_get_echo_skb(dev, idx); 693 bytes += priv->dlc[idx]; 694 pkts++; 695 } 696 697 /* Clear the bits in the tx_active mask */ 698 atomic_sub(clr, &priv->tx_active); 699 700 if (clr & (1 << (C_CAN_MSG_OBJ_TX_NUM - 1))) 701 netif_wake_queue(dev); 702 703 if (pkts) { 704 stats->tx_bytes += bytes; 705 stats->tx_packets += pkts; 706 can_led_event(dev, CAN_LED_EVENT_TX); 707 } 708} 709 710/* 711 * If we have a gap in the pending bits, that means we either 712 * raced with the hardware or failed to readout all upper 713 * objects in the last run due to quota limit. 714 */ 715static u32 c_can_adjust_pending(u32 pend) 716{ 717 u32 weight, lasts; 718 719 if (pend == RECEIVE_OBJECT_BITS) 720 return pend; 721 722 /* 723 * If the last set bit is larger than the number of pending 724 * bits we have a gap. 725 */ 726 weight = hweight32(pend); 727 lasts = fls(pend); 728 729 /* If the bits are linear, nothing to do */ 730 if (lasts == weight) 731 return pend; 732 733 /* 734 * Find the first set bit after the gap. We walk backwards 735 * from the last set bit. 736 */ 737 for (lasts--; pend & (1 << (lasts - 1)); lasts--); 738 739 return pend & ~((1 << lasts) - 1); 740} 741 742static inline void c_can_rx_object_get(struct net_device *dev, 743 struct c_can_priv *priv, u32 obj) 744{ 745 c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high); 746} 747 748static inline void c_can_rx_finalize(struct net_device *dev, 749 struct c_can_priv *priv, u32 obj) 750{ 751 if (priv->type != BOSCH_D_CAN) 752 c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT); 753} 754 755static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 756 u32 pend, int quota) 757{ 758 u32 pkts = 0, ctrl, obj; 759 760 while ((obj = ffs(pend)) && quota > 0) { 761 pend &= ~BIT(obj - 1); 762 763 c_can_rx_object_get(dev, priv, obj); 764 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 765 766 if (ctrl & IF_MCONT_MSGLST) { 767 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); 768 769 pkts += n; 770 quota -= n; 771 continue; 772 } 773 774 /* 775 * This really should not happen, but this covers some 776 * odd HW behaviour. Do not remove that unless you 777 * want to brick your machine. 778 */ 779 if (!(ctrl & IF_MCONT_NEWDAT)) 780 continue; 781 782 /* read the data from the message object */ 783 c_can_read_msg_object(dev, IF_RX, ctrl); 784 785 c_can_rx_finalize(dev, priv, obj); 786 787 pkts++; 788 quota--; 789 } 790 791 return pkts; 792} 793 794static inline u32 c_can_get_pending(struct c_can_priv *priv) 795{ 796 u32 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG); 797 798 return pend; 799} 800 801/* 802 * theory of operation: 803 * 804 * c_can core saves a received CAN message into the first free message 805 * object it finds free (starting with the lowest). Bits NEWDAT and 806 * INTPND are set for this message object indicating that a new message 807 * has arrived. To work-around this issue, we keep two groups of message 808 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 809 * 810 * We clear the newdat bit right away. 811 * 812 * This can result in packet reordering when the readout is slow. 813 */ 814static int c_can_do_rx_poll(struct net_device *dev, int quota) 815{ 816 struct c_can_priv *priv = netdev_priv(dev); 817 u32 pkts = 0, pend = 0, toread, n; 818 819 /* 820 * It is faster to read only one 16bit register. This is only possible 821 * for a maximum number of 16 objects. 822 */ 823 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, 824 "Implementation does not support more message objects than 16"); 825 826 while (quota > 0) { 827 if (!pend) { 828 pend = c_can_get_pending(priv); 829 if (!pend) 830 break; 831 /* 832 * If the pending field has a gap, handle the 833 * bits above the gap first. 834 */ 835 toread = c_can_adjust_pending(pend); 836 } else { 837 toread = pend; 838 } 839 /* Remove the bits from pend */ 840 pend &= ~toread; 841 /* Read the objects */ 842 n = c_can_read_objects(dev, priv, toread, quota); 843 pkts += n; 844 quota -= n; 845 } 846 847 if (pkts) 848 can_led_event(dev, CAN_LED_EVENT_RX); 849 850 return pkts; 851} 852 853static int c_can_handle_state_change(struct net_device *dev, 854 enum c_can_bus_error_types error_type) 855{ 856 unsigned int reg_err_counter; 857 unsigned int rx_err_passive; 858 struct c_can_priv *priv = netdev_priv(dev); 859 struct net_device_stats *stats = &dev->stats; 860 struct can_frame *cf; 861 struct sk_buff *skb; 862 struct can_berr_counter bec; 863 864 switch (error_type) { 865 case C_CAN_ERROR_WARNING: 866 /* error warning state */ 867 priv->can.can_stats.error_warning++; 868 priv->can.state = CAN_STATE_ERROR_WARNING; 869 break; 870 case C_CAN_ERROR_PASSIVE: 871 /* error passive state */ 872 priv->can.can_stats.error_passive++; 873 priv->can.state = CAN_STATE_ERROR_PASSIVE; 874 break; 875 case C_CAN_BUS_OFF: 876 /* bus-off state */ 877 priv->can.state = CAN_STATE_BUS_OFF; 878 priv->can.can_stats.bus_off++; 879 break; 880 default: 881 break; 882 } 883 884 /* propagate the error condition to the CAN stack */ 885 skb = alloc_can_err_skb(dev, &cf); 886 if (unlikely(!skb)) 887 return 0; 888 889 __c_can_get_berr_counter(dev, &bec); 890 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 891 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 892 ERR_CNT_RP_SHIFT; 893 894 switch (error_type) { 895 case C_CAN_ERROR_WARNING: 896 /* error warning state */ 897 cf->can_id |= CAN_ERR_CRTL; 898 cf->data[1] = (bec.txerr > bec.rxerr) ? 899 CAN_ERR_CRTL_TX_WARNING : 900 CAN_ERR_CRTL_RX_WARNING; 901 cf->data[6] = bec.txerr; 902 cf->data[7] = bec.rxerr; 903 904 break; 905 case C_CAN_ERROR_PASSIVE: 906 /* error passive state */ 907 cf->can_id |= CAN_ERR_CRTL; 908 if (rx_err_passive) 909 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 910 if (bec.txerr > 127) 911 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 912 913 cf->data[6] = bec.txerr; 914 cf->data[7] = bec.rxerr; 915 break; 916 case C_CAN_BUS_OFF: 917 /* bus-off state */ 918 cf->can_id |= CAN_ERR_BUSOFF; 919 can_bus_off(dev); 920 break; 921 default: 922 break; 923 } 924 925 stats->rx_packets++; 926 stats->rx_bytes += cf->can_dlc; 927 netif_receive_skb(skb); 928 929 return 1; 930} 931 932static int c_can_handle_bus_err(struct net_device *dev, 933 enum c_can_lec_type lec_type) 934{ 935 struct c_can_priv *priv = netdev_priv(dev); 936 struct net_device_stats *stats = &dev->stats; 937 struct can_frame *cf; 938 struct sk_buff *skb; 939 940 /* 941 * early exit if no lec update or no error. 942 * no lec update means that no CAN bus event has been detected 943 * since CPU wrote 0x7 value to status reg. 944 */ 945 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 946 return 0; 947 948 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 949 return 0; 950 951 /* common for all type of bus errors */ 952 priv->can.can_stats.bus_error++; 953 stats->rx_errors++; 954 955 /* propagate the error condition to the CAN stack */ 956 skb = alloc_can_err_skb(dev, &cf); 957 if (unlikely(!skb)) 958 return 0; 959 960 /* 961 * check for 'last error code' which tells us the 962 * type of the last error to occur on the CAN bus 963 */ 964 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 965 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 966 967 switch (lec_type) { 968 case LEC_STUFF_ERROR: 969 netdev_dbg(dev, "stuff error\n"); 970 cf->data[2] |= CAN_ERR_PROT_STUFF; 971 break; 972 case LEC_FORM_ERROR: 973 netdev_dbg(dev, "form error\n"); 974 cf->data[2] |= CAN_ERR_PROT_FORM; 975 break; 976 case LEC_ACK_ERROR: 977 netdev_dbg(dev, "ack error\n"); 978 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 979 CAN_ERR_PROT_LOC_ACK_DEL); 980 break; 981 case LEC_BIT1_ERROR: 982 netdev_dbg(dev, "bit1 error\n"); 983 cf->data[2] |= CAN_ERR_PROT_BIT1; 984 break; 985 case LEC_BIT0_ERROR: 986 netdev_dbg(dev, "bit0 error\n"); 987 cf->data[2] |= CAN_ERR_PROT_BIT0; 988 break; 989 case LEC_CRC_ERROR: 990 netdev_dbg(dev, "CRC error\n"); 991 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 992 CAN_ERR_PROT_LOC_CRC_DEL); 993 break; 994 default: 995 break; 996 } 997 998 stats->rx_packets++; 999 stats->rx_bytes += cf->can_dlc; 1000 netif_receive_skb(skb); 1001 return 1; 1002} 1003 1004static int c_can_poll(struct napi_struct *napi, int quota) 1005{ 1006 struct net_device *dev = napi->dev; 1007 struct c_can_priv *priv = netdev_priv(dev); 1008 u16 curr, last = priv->last_status; 1009 int work_done = 0; 1010 1011 priv->last_status = curr = priv->read_reg(priv, C_CAN_STS_REG); 1012 /* Ack status on C_CAN. D_CAN is self clearing */ 1013 if (priv->type != BOSCH_D_CAN) 1014 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1015 1016 /* handle state changes */ 1017 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) { 1018 netdev_dbg(dev, "entered error warning state\n"); 1019 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); 1020 } 1021 1022 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) { 1023 netdev_dbg(dev, "entered error passive state\n"); 1024 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); 1025 } 1026 1027 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) { 1028 netdev_dbg(dev, "entered bus off state\n"); 1029 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF); 1030 goto end; 1031 } 1032 1033 /* handle bus recovery events */ 1034 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) { 1035 netdev_dbg(dev, "left bus off state\n"); 1036 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1037 } 1038 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) { 1039 netdev_dbg(dev, "left error passive state\n"); 1040 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1041 } 1042 1043 /* handle lec errors on the bus */ 1044 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK); 1045 1046 /* Handle Tx/Rx events. We do this unconditionally */ 1047 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1048 c_can_do_tx(dev); 1049 1050end: 1051 if (work_done < quota) { 1052 napi_complete(napi); 1053 /* enable all IRQs if we are not in bus off state */ 1054 if (priv->can.state != CAN_STATE_BUS_OFF) 1055 c_can_irq_control(priv, true); 1056 } 1057 1058 return work_done; 1059} 1060 1061static irqreturn_t c_can_isr(int irq, void *dev_id) 1062{ 1063 struct net_device *dev = (struct net_device *)dev_id; 1064 struct c_can_priv *priv = netdev_priv(dev); 1065 1066 if (!priv->read_reg(priv, C_CAN_INT_REG)) 1067 return IRQ_NONE; 1068 1069 /* disable all interrupts and schedule the NAPI */ 1070 c_can_irq_control(priv, false); 1071 napi_schedule(&priv->napi); 1072 1073 return IRQ_HANDLED; 1074} 1075 1076static int c_can_open(struct net_device *dev) 1077{ 1078 int err; 1079 struct c_can_priv *priv = netdev_priv(dev); 1080 1081 c_can_pm_runtime_get_sync(priv); 1082 c_can_reset_ram(priv, true); 1083 1084 /* open the can device */ 1085 err = open_candev(dev); 1086 if (err) { 1087 netdev_err(dev, "failed to open can device\n"); 1088 goto exit_open_fail; 1089 } 1090 1091 /* register interrupt handler */ 1092 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1093 dev); 1094 if (err < 0) { 1095 netdev_err(dev, "failed to request interrupt\n"); 1096 goto exit_irq_fail; 1097 } 1098 1099 /* start the c_can controller */ 1100 err = c_can_start(dev); 1101 if (err) 1102 goto exit_start_fail; 1103 1104 can_led_event(dev, CAN_LED_EVENT_OPEN); 1105 1106 napi_enable(&priv->napi); 1107 /* enable status change, error and module interrupts */ 1108 c_can_irq_control(priv, true); 1109 netif_start_queue(dev); 1110 1111 return 0; 1112 1113exit_start_fail: 1114 free_irq(dev->irq, dev); 1115exit_irq_fail: 1116 close_candev(dev); 1117exit_open_fail: 1118 c_can_reset_ram(priv, false); 1119 c_can_pm_runtime_put_sync(priv); 1120 return err; 1121} 1122 1123static int c_can_close(struct net_device *dev) 1124{ 1125 struct c_can_priv *priv = netdev_priv(dev); 1126 1127 netif_stop_queue(dev); 1128 napi_disable(&priv->napi); 1129 c_can_stop(dev); 1130 free_irq(dev->irq, dev); 1131 close_candev(dev); 1132 1133 c_can_reset_ram(priv, false); 1134 c_can_pm_runtime_put_sync(priv); 1135 1136 can_led_event(dev, CAN_LED_EVENT_STOP); 1137 1138 return 0; 1139} 1140 1141struct net_device *alloc_c_can_dev(void) 1142{ 1143 struct net_device *dev; 1144 struct c_can_priv *priv; 1145 1146 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1147 if (!dev) 1148 return NULL; 1149 1150 priv = netdev_priv(dev); 1151 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1152 1153 priv->dev = dev; 1154 priv->can.bittiming_const = &c_can_bittiming_const; 1155 priv->can.do_set_mode = c_can_set_mode; 1156 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1157 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1158 CAN_CTRLMODE_LISTENONLY | 1159 CAN_CTRLMODE_BERR_REPORTING; 1160 1161 return dev; 1162} 1163EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1164 1165#ifdef CONFIG_PM 1166int c_can_power_down(struct net_device *dev) 1167{ 1168 u32 val; 1169 unsigned long time_out; 1170 struct c_can_priv *priv = netdev_priv(dev); 1171 1172 if (!(dev->flags & IFF_UP)) 1173 return 0; 1174 1175 WARN_ON(priv->type != BOSCH_D_CAN); 1176 1177 /* set PDR value so the device goes to power down mode */ 1178 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1179 val |= CONTROL_EX_PDR; 1180 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1181 1182 /* Wait for the PDA bit to get set */ 1183 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1184 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1185 time_after(time_out, jiffies)) 1186 cpu_relax(); 1187 1188 if (time_after(jiffies, time_out)) 1189 return -ETIMEDOUT; 1190 1191 c_can_stop(dev); 1192 1193 c_can_reset_ram(priv, false); 1194 c_can_pm_runtime_put_sync(priv); 1195 1196 return 0; 1197} 1198EXPORT_SYMBOL_GPL(c_can_power_down); 1199 1200int c_can_power_up(struct net_device *dev) 1201{ 1202 u32 val; 1203 unsigned long time_out; 1204 struct c_can_priv *priv = netdev_priv(dev); 1205 int ret; 1206 1207 if (!(dev->flags & IFF_UP)) 1208 return 0; 1209 1210 WARN_ON(priv->type != BOSCH_D_CAN); 1211 1212 c_can_pm_runtime_get_sync(priv); 1213 c_can_reset_ram(priv, true); 1214 1215 /* Clear PDR and INIT bits */ 1216 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1217 val &= ~CONTROL_EX_PDR; 1218 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1219 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1220 val &= ~CONTROL_INIT; 1221 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1222 1223 /* Wait for the PDA bit to get clear */ 1224 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1225 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1226 time_after(time_out, jiffies)) 1227 cpu_relax(); 1228 1229 if (time_after(jiffies, time_out)) 1230 return -ETIMEDOUT; 1231 1232 ret = c_can_start(dev); 1233 if (!ret) 1234 c_can_irq_control(priv, true); 1235 1236 return ret; 1237} 1238EXPORT_SYMBOL_GPL(c_can_power_up); 1239#endif 1240 1241void free_c_can_dev(struct net_device *dev) 1242{ 1243 struct c_can_priv *priv = netdev_priv(dev); 1244 1245 netif_napi_del(&priv->napi); 1246 free_candev(dev); 1247} 1248EXPORT_SYMBOL_GPL(free_c_can_dev); 1249 1250static const struct net_device_ops c_can_netdev_ops = { 1251 .ndo_open = c_can_open, 1252 .ndo_stop = c_can_close, 1253 .ndo_start_xmit = c_can_start_xmit, 1254 .ndo_change_mtu = can_change_mtu, 1255}; 1256 1257int register_c_can_dev(struct net_device *dev) 1258{ 1259 struct c_can_priv *priv = netdev_priv(dev); 1260 int err; 1261 1262 /* Deactivate pins to prevent DRA7 DCAN IP from being 1263 * stuck in transition when module is disabled. 1264 * Pins are activated in c_can_start() and deactivated 1265 * in c_can_stop() 1266 */ 1267 pinctrl_pm_select_sleep_state(dev->dev.parent); 1268 1269 c_can_pm_runtime_enable(priv); 1270 1271 dev->flags |= IFF_ECHO; /* we support local echo */ 1272 dev->netdev_ops = &c_can_netdev_ops; 1273 1274 err = register_candev(dev); 1275 if (err) 1276 c_can_pm_runtime_disable(priv); 1277 else 1278 devm_can_led_init(dev); 1279 1280 return err; 1281} 1282EXPORT_SYMBOL_GPL(register_c_can_dev); 1283 1284void unregister_c_can_dev(struct net_device *dev) 1285{ 1286 struct c_can_priv *priv = netdev_priv(dev); 1287 1288 unregister_candev(dev); 1289 1290 c_can_pm_runtime_disable(priv); 1291} 1292EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1293 1294MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1295MODULE_LICENSE("GPL v2"); 1296MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1297