1/* 2 * FB driver for the uPD161704 LCD Controller 3 * 4 * Copyright (C) 2014 Seong-Woo Kim 5 * 6 * Based on fb_ili9325.c by Noralf Tronnes 7 * Based on ili9325.c by Jeroen Domburg 8 * Init code from UTFT library by Henning Karlsen 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25#include <linux/module.h> 26#include <linux/kernel.h> 27#include <linux/init.h> 28#include <linux/gpio.h> 29#include <linux/delay.h> 30 31#include "fbtft.h" 32 33#define DRVNAME "fb_bd663474" 34#define WIDTH 240 35#define HEIGHT 320 36#define BPP 16 37 38static int init_display(struct fbtft_par *par) 39{ 40 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__); 41 42 if (par->gpio.cs != -1) 43 gpio_set_value(par->gpio.cs, 0); /* Activate chip */ 44 45 par->fbtftops.reset(par); 46 47 /* Initialization sequence from Lib_UTFT */ 48 49 /* oscillator start */ 50 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */ 51 mdelay(10); 52 53 /* Power settings */ 54 write_reg(par, 0x100, 0x0000); /* power supply setup */ 55 write_reg(par, 0x101, 0x0000); 56 write_reg(par, 0x102, 0x3110); 57 write_reg(par, 0x103, 0xe200); 58 write_reg(par, 0x110, 0x009d); 59 write_reg(par, 0x111, 0x0022); 60 write_reg(par, 0x100, 0x0120); 61 mdelay(20); 62 63 write_reg(par, 0x100, 0x3120); 64 mdelay(80); 65 /* Display control */ 66 write_reg(par, 0x001, 0x0100); 67 write_reg(par, 0x002, 0x0000); 68 write_reg(par, 0x003, 0x1230); 69 write_reg(par, 0x006, 0x0000); 70 write_reg(par, 0x007, 0x0101); 71 write_reg(par, 0x008, 0x0808); 72 write_reg(par, 0x009, 0x0000); 73 write_reg(par, 0x00b, 0x0000); 74 write_reg(par, 0x00c, 0x0000); 75 write_reg(par, 0x00d, 0x0018); 76 /* LTPS control settings */ 77 write_reg(par, 0x012, 0x0000); 78 write_reg(par, 0x013, 0x0000); 79 write_reg(par, 0x018, 0x0000); 80 write_reg(par, 0x019, 0x0000); 81 82 write_reg(par, 0x203, 0x0000); 83 write_reg(par, 0x204, 0x0000); 84 85 write_reg(par, 0x210, 0x0000); 86 write_reg(par, 0x211, 0x00ef); 87 write_reg(par, 0x212, 0x0000); 88 write_reg(par, 0x213, 0x013f); 89 write_reg(par, 0x214, 0x0000); 90 write_reg(par, 0x215, 0x0000); 91 write_reg(par, 0x216, 0x0000); 92 write_reg(par, 0x217, 0x0000); 93 94 /* Gray scale settings */ 95 write_reg(par, 0x300, 0x5343); 96 write_reg(par, 0x301, 0x1021); 97 write_reg(par, 0x302, 0x0003); 98 write_reg(par, 0x303, 0x0011); 99 write_reg(par, 0x304, 0x050a); 100 write_reg(par, 0x305, 0x4342); 101 write_reg(par, 0x306, 0x1100); 102 write_reg(par, 0x307, 0x0003); 103 write_reg(par, 0x308, 0x1201); 104 write_reg(par, 0x309, 0x050a); 105 106 /* RAM access settings */ 107 write_reg(par, 0x400, 0x4027); 108 write_reg(par, 0x401, 0x0000); 109 write_reg(par, 0x402, 0x0000); /* First screen drive position (1) */ 110 write_reg(par, 0x403, 0x013f); /* First screen drive position (2) */ 111 write_reg(par, 0x404, 0x0000); 112 113 write_reg(par, 0x200, 0x0000); 114 write_reg(par, 0x201, 0x0000); 115 write_reg(par, 0x100, 0x7120); 116 write_reg(par, 0x007, 0x0103); 117 mdelay(10); 118 write_reg(par, 0x007, 0x0113); 119 120 return 0; 121} 122 123static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) 124{ 125 fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par, 126 "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye); 127 switch (par->info->var.rotate) { 128 /* R200h = Horizontal GRAM Start Address */ 129 /* R201h = Vertical GRAM Start Address */ 130 case 0: 131 write_reg(par, 0x0200, xs); 132 write_reg(par, 0x0201, ys); 133 break; 134 case 180: 135 write_reg(par, 0x0200, WIDTH - 1 - xs); 136 write_reg(par, 0x0201, HEIGHT - 1 - ys); 137 break; 138 case 270: 139 write_reg(par, 0x0200, WIDTH - 1 - ys); 140 write_reg(par, 0x0201, xs); 141 break; 142 case 90: 143 write_reg(par, 0x0200, ys); 144 write_reg(par, 0x0201, HEIGHT - 1 - xs); 145 break; 146 } 147 write_reg(par, 0x202); /* Write Data to GRAM */ 148} 149 150static int set_var(struct fbtft_par *par) 151{ 152 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__); 153 154 switch (par->info->var.rotate) { 155 /* AM: GRAM update direction */ 156 case 0: 157 write_reg(par, 0x003, 0x1230); 158 break; 159 case 180: 160 write_reg(par, 0x003, 0x1200); 161 break; 162 case 270: 163 write_reg(par, 0x003, 0x1228); 164 break; 165 case 90: 166 write_reg(par, 0x003, 0x1218); 167 break; 168 } 169 170 return 0; 171} 172 173static struct fbtft_display display = { 174 .regwidth = 16, 175 .width = WIDTH, 176 .height = HEIGHT, 177 .bpp = BPP, 178 .fbtftops = { 179 .init_display = init_display, 180 .set_addr_win = set_addr_win, 181 .set_var = set_var, 182 }, 183}; 184FBTFT_REGISTER_DRIVER(DRVNAME, "hitachi,bd663474", &display); 185 186MODULE_ALIAS("spi:" DRVNAME); 187MODULE_ALIAS("platform:" DRVNAME); 188MODULE_ALIAS("spi:bd663474"); 189MODULE_ALIAS("platform:bd663474"); 190 191MODULE_DESCRIPTION("FB driver for the uPD161704 LCD Controller"); 192MODULE_AUTHOR("Seong-Woo Kim"); 193MODULE_LICENSE("GPL"); 194