1/******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29#include <linux/pci.h> 30#include <linux/delay.h> 31#include <linux/sched.h> 32 33#include "ixgbe.h" 34#include "ixgbe_phy.h" 35 36static void ixgbe_i2c_start(struct ixgbe_hw *hw); 37static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 38static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 39static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 40static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 41static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 42static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 43static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 44static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 45static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 46static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 47static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 48static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 49static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 50static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw); 51 52/** 53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 54 * @hw: pointer to the hardware structure 55 * @byte: byte to send 56 * 57 * Returns an error code on error. 58 **/ 59static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 60{ 61 s32 status; 62 63 status = ixgbe_clock_out_i2c_byte(hw, byte); 64 if (status) 65 return status; 66 return ixgbe_get_i2c_ack(hw); 67} 68 69/** 70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 71 * @hw: pointer to the hardware structure 72 * @byte: pointer to a u8 to receive the byte 73 * 74 * Returns an error code on error. 75 **/ 76static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 77{ 78 s32 status; 79 80 status = ixgbe_clock_in_i2c_byte(hw, byte); 81 if (status) 82 return status; 83 /* ACK */ 84 return ixgbe_clock_out_i2c_bit(hw, false); 85} 86 87/** 88 * ixgbe_ones_comp_byte_add - Perform one's complement addition 89 * @add1: addend 1 90 * @add2: addend 2 91 * 92 * Returns one's complement 8-bit sum. 93 **/ 94static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 95{ 96 u16 sum = add1 + add2; 97 98 sum = (sum & 0xFF) + (sum >> 8); 99 return sum & 0xFF; 100} 101 102/** 103 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 104 * @hw: pointer to the hardware structure 105 * @addr: I2C bus address to read from 106 * @reg: I2C device register to read from 107 * @val: pointer to location to receive read value 108 * 109 * Returns an error code on error. 110 **/ 111s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 112 u16 reg, u16 *val) 113{ 114 u32 swfw_mask = hw->phy.phy_semaphore_mask; 115 int max_retry = 10; 116 int retry = 0; 117 u8 csum_byte; 118 u8 high_bits; 119 u8 low_bits; 120 u8 reg_high; 121 u8 csum; 122 123 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 124 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 125 csum = ~csum; 126 do { 127 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 128 return IXGBE_ERR_SWFW_SYNC; 129 ixgbe_i2c_start(hw); 130 /* Device Address and write indication */ 131 if (ixgbe_out_i2c_byte_ack(hw, addr)) 132 goto fail; 133 /* Write bits 14:8 */ 134 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 135 goto fail; 136 /* Write bits 7:0 */ 137 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 138 goto fail; 139 /* Write csum */ 140 if (ixgbe_out_i2c_byte_ack(hw, csum)) 141 goto fail; 142 /* Re-start condition */ 143 ixgbe_i2c_start(hw); 144 /* Device Address and read indication */ 145 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 146 goto fail; 147 /* Get upper bits */ 148 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 149 goto fail; 150 /* Get low bits */ 151 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 152 goto fail; 153 /* Get csum */ 154 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 155 goto fail; 156 /* NACK */ 157 if (ixgbe_clock_out_i2c_bit(hw, false)) 158 goto fail; 159 ixgbe_i2c_stop(hw); 160 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 161 *val = (high_bits << 8) | low_bits; 162 return 0; 163 164fail: 165 ixgbe_i2c_bus_clear(hw); 166 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 167 retry++; 168 if (retry < max_retry) 169 hw_dbg(hw, "I2C byte read combined error - Retry.\n"); 170 else 171 hw_dbg(hw, "I2C byte read combined error.\n"); 172 } while (retry < max_retry); 173 174 return IXGBE_ERR_I2C; 175} 176 177/** 178 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 179 * @hw: pointer to the hardware structure 180 * @addr: I2C bus address to write to 181 * @reg: I2C device register to write to 182 * @val: value to write 183 * 184 * Returns an error code on error. 185 **/ 186s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 187 u8 addr, u16 reg, u16 val) 188{ 189 int max_retry = 1; 190 int retry = 0; 191 u8 reg_high; 192 u8 csum; 193 194 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 195 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 196 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 197 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 198 csum = ~csum; 199 do { 200 ixgbe_i2c_start(hw); 201 /* Device Address and write indication */ 202 if (ixgbe_out_i2c_byte_ack(hw, addr)) 203 goto fail; 204 /* Write bits 14:8 */ 205 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 206 goto fail; 207 /* Write bits 7:0 */ 208 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 209 goto fail; 210 /* Write data 15:8 */ 211 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 212 goto fail; 213 /* Write data 7:0 */ 214 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 215 goto fail; 216 /* Write csum */ 217 if (ixgbe_out_i2c_byte_ack(hw, csum)) 218 goto fail; 219 ixgbe_i2c_stop(hw); 220 return 0; 221 222fail: 223 ixgbe_i2c_bus_clear(hw); 224 retry++; 225 if (retry < max_retry) 226 hw_dbg(hw, "I2C byte write combined error - Retry.\n"); 227 else 228 hw_dbg(hw, "I2C byte write combined error.\n"); 229 } while (retry < max_retry); 230 231 return IXGBE_ERR_I2C; 232} 233 234/** 235 * ixgbe_identify_phy_generic - Get physical layer module 236 * @hw: pointer to hardware structure 237 * 238 * Determines the physical layer module found on the current adapter. 239 **/ 240s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 241{ 242 u32 phy_addr; 243 u16 ext_ability = 0; 244 245 if (!hw->phy.phy_semaphore_mask) { 246 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) & 247 IXGBE_STATUS_LAN_ID_1; 248 if (hw->phy.lan_id) 249 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 250 else 251 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 252 } 253 254 if (hw->phy.type == ixgbe_phy_unknown) { 255 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 256 hw->phy.mdio.prtad = phy_addr; 257 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) { 258 ixgbe_get_phy_id(hw); 259 hw->phy.type = 260 ixgbe_get_phy_type_from_id(hw->phy.id); 261 262 if (hw->phy.type == ixgbe_phy_unknown) { 263 hw->phy.ops.read_reg(hw, 264 MDIO_PMA_EXTABLE, 265 MDIO_MMD_PMAPMD, 266 &ext_ability); 267 if (ext_ability & 268 (MDIO_PMA_EXTABLE_10GBT | 269 MDIO_PMA_EXTABLE_1000BT)) 270 hw->phy.type = 271 ixgbe_phy_cu_unknown; 272 else 273 hw->phy.type = 274 ixgbe_phy_generic; 275 } 276 277 return 0; 278 } 279 } 280 /* clear value if nothing found */ 281 hw->phy.mdio.prtad = 0; 282 return IXGBE_ERR_PHY_ADDR_INVALID; 283 } 284 return 0; 285} 286 287/** 288 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 289 * @hw: pointer to the hardware structure 290 * 291 * This function checks the MMNGC.MNG_VETO bit to see if there are 292 * any constraints on link from manageability. For MAC's that don't 293 * have this bit just return false since the link can not be blocked 294 * via this method. 295 **/ 296bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 297{ 298 u32 mmngc; 299 300 /* If we don't have this bit, it can't be blocking */ 301 if (hw->mac.type == ixgbe_mac_82598EB) 302 return false; 303 304 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 305 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 306 hw_dbg(hw, "MNG_VETO bit detected.\n"); 307 return true; 308 } 309 310 return false; 311} 312 313/** 314 * ixgbe_get_phy_id - Get the phy type 315 * @hw: pointer to hardware structure 316 * 317 **/ 318static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 319{ 320 u32 status; 321 u16 phy_id_high = 0; 322 u16 phy_id_low = 0; 323 324 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD, 325 &phy_id_high); 326 327 if (status == 0) { 328 hw->phy.id = (u32)(phy_id_high << 16); 329 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD, 330 &phy_id_low); 331 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 332 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 333 } 334 return status; 335} 336 337/** 338 * ixgbe_get_phy_type_from_id - Get the phy type 339 * @hw: pointer to hardware structure 340 * 341 **/ 342static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 343{ 344 enum ixgbe_phy_type phy_type; 345 346 switch (phy_id) { 347 case TN1010_PHY_ID: 348 phy_type = ixgbe_phy_tn; 349 break; 350 case X540_PHY_ID: 351 phy_type = ixgbe_phy_aq; 352 break; 353 case QT2022_PHY_ID: 354 phy_type = ixgbe_phy_qt; 355 break; 356 case ATH_PHY_ID: 357 phy_type = ixgbe_phy_nl; 358 break; 359 default: 360 phy_type = ixgbe_phy_unknown; 361 break; 362 } 363 364 return phy_type; 365} 366 367/** 368 * ixgbe_reset_phy_generic - Performs a PHY reset 369 * @hw: pointer to hardware structure 370 **/ 371s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 372{ 373 u32 i; 374 u16 ctrl = 0; 375 s32 status = 0; 376 377 if (hw->phy.type == ixgbe_phy_unknown) 378 status = ixgbe_identify_phy_generic(hw); 379 380 if (status != 0 || hw->phy.type == ixgbe_phy_none) 381 return status; 382 383 /* Don't reset PHY if it's shut down due to overtemp. */ 384 if (!hw->phy.reset_if_overtemp && 385 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 386 return 0; 387 388 /* Blocked by MNG FW so bail */ 389 if (ixgbe_check_reset_blocked(hw)) 390 return 0; 391 392 /* 393 * Perform soft PHY reset to the PHY_XS. 394 * This will cause a soft reset to the PHY 395 */ 396 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 397 MDIO_MMD_PHYXS, 398 MDIO_CTRL1_RESET); 399 400 /* 401 * Poll for reset bit to self-clear indicating reset is complete. 402 * Some PHYs could take up to 3 seconds to complete and need about 403 * 1.7 usec delay after the reset is complete. 404 */ 405 for (i = 0; i < 30; i++) { 406 msleep(100); 407 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 408 MDIO_MMD_PHYXS, &ctrl); 409 if (!(ctrl & MDIO_CTRL1_RESET)) { 410 udelay(2); 411 break; 412 } 413 } 414 415 if (ctrl & MDIO_CTRL1_RESET) { 416 hw_dbg(hw, "PHY reset polling failed to complete.\n"); 417 return IXGBE_ERR_RESET_FAILED; 418 } 419 420 return 0; 421} 422 423/** 424 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 425 * the SWFW lock 426 * @hw: pointer to hardware structure 427 * @reg_addr: 32 bit address of PHY register to read 428 * @phy_data: Pointer to read data from PHY register 429 **/ 430s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 431 u16 *phy_data) 432{ 433 u32 i, data, command; 434 435 /* Setup and write the address cycle command */ 436 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 437 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 438 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 439 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 440 441 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 442 443 /* Check every 10 usec to see if the address cycle completed. 444 * The MDI Command bit will clear when the operation is 445 * complete 446 */ 447 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 448 udelay(10); 449 450 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 451 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 452 break; 453 } 454 455 456 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 457 hw_dbg(hw, "PHY address command did not complete.\n"); 458 return IXGBE_ERR_PHY; 459 } 460 461 /* Address cycle complete, setup and write the read 462 * command 463 */ 464 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 465 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 466 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 467 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 468 469 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 470 471 /* Check every 10 usec to see if the address cycle 472 * completed. The MDI Command bit will clear when the 473 * operation is complete 474 */ 475 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 476 udelay(10); 477 478 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 479 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 480 break; 481 } 482 483 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 484 hw_dbg(hw, "PHY read command didn't complete\n"); 485 return IXGBE_ERR_PHY; 486 } 487 488 /* Read operation is complete. Get the data 489 * from MSRWD 490 */ 491 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 492 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 493 *phy_data = (u16)(data); 494 495 return 0; 496} 497 498/** 499 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 500 * using the SWFW lock - this function is needed in most cases 501 * @hw: pointer to hardware structure 502 * @reg_addr: 32 bit address of PHY register to read 503 * @phy_data: Pointer to read data from PHY register 504 **/ 505s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 506 u32 device_type, u16 *phy_data) 507{ 508 s32 status; 509 u32 gssr = hw->phy.phy_semaphore_mask; 510 511 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 512 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 513 phy_data); 514 hw->mac.ops.release_swfw_sync(hw, gssr); 515 } else { 516 return IXGBE_ERR_SWFW_SYNC; 517 } 518 519 return status; 520} 521 522/** 523 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 524 * without SWFW lock 525 * @hw: pointer to hardware structure 526 * @reg_addr: 32 bit PHY register to write 527 * @device_type: 5 bit device type 528 * @phy_data: Data to write to the PHY register 529 **/ 530s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 531 u32 device_type, u16 phy_data) 532{ 533 u32 i, command; 534 535 /* Put the data in the MDI single read and write data register*/ 536 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 537 538 /* Setup and write the address cycle command */ 539 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 540 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 541 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 542 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 543 544 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 545 546 /* 547 * Check every 10 usec to see if the address cycle completed. 548 * The MDI Command bit will clear when the operation is 549 * complete 550 */ 551 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 552 udelay(10); 553 554 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 555 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 556 break; 557 } 558 559 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 560 hw_dbg(hw, "PHY address cmd didn't complete\n"); 561 return IXGBE_ERR_PHY; 562 } 563 564 /* 565 * Address cycle complete, setup and write the write 566 * command 567 */ 568 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 569 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 570 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 571 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 572 573 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 574 575 /* Check every 10 usec to see if the address cycle 576 * completed. The MDI Command bit will clear when the 577 * operation is complete 578 */ 579 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 580 udelay(10); 581 582 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 583 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 584 break; 585 } 586 587 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 588 hw_dbg(hw, "PHY write cmd didn't complete\n"); 589 return IXGBE_ERR_PHY; 590 } 591 592 return 0; 593} 594 595/** 596 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 597 * using SWFW lock- this function is needed in most cases 598 * @hw: pointer to hardware structure 599 * @reg_addr: 32 bit PHY register to write 600 * @device_type: 5 bit device type 601 * @phy_data: Data to write to the PHY register 602 **/ 603s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 604 u32 device_type, u16 phy_data) 605{ 606 s32 status; 607 u32 gssr; 608 609 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 610 gssr = IXGBE_GSSR_PHY1_SM; 611 else 612 gssr = IXGBE_GSSR_PHY0_SM; 613 614 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 615 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 616 phy_data); 617 hw->mac.ops.release_swfw_sync(hw, gssr); 618 } else { 619 return IXGBE_ERR_SWFW_SYNC; 620 } 621 622 return status; 623} 624 625/** 626 * ixgbe_setup_phy_link_generic - Set and restart autoneg 627 * @hw: pointer to hardware structure 628 * 629 * Restart autonegotiation and PHY and waits for completion. 630 **/ 631s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 632{ 633 s32 status = 0; 634 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 635 bool autoneg = false; 636 ixgbe_link_speed speed; 637 638 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 639 640 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 641 /* Set or unset auto-negotiation 10G advertisement */ 642 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 643 MDIO_MMD_AN, 644 &autoneg_reg); 645 646 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 647 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 648 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 649 650 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 651 MDIO_MMD_AN, 652 autoneg_reg); 653 } 654 655 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 656 /* Set or unset auto-negotiation 1G advertisement */ 657 hw->phy.ops.read_reg(hw, 658 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 659 MDIO_MMD_AN, 660 &autoneg_reg); 661 662 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 663 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 664 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 665 666 hw->phy.ops.write_reg(hw, 667 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 668 MDIO_MMD_AN, 669 autoneg_reg); 670 } 671 672 if (speed & IXGBE_LINK_SPEED_100_FULL) { 673 /* Set or unset auto-negotiation 100M advertisement */ 674 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 675 MDIO_MMD_AN, 676 &autoneg_reg); 677 678 autoneg_reg &= ~(ADVERTISE_100FULL | 679 ADVERTISE_100HALF); 680 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 681 autoneg_reg |= ADVERTISE_100FULL; 682 683 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 684 MDIO_MMD_AN, 685 autoneg_reg); 686 } 687 688 /* Blocked by MNG FW so don't reset PHY */ 689 if (ixgbe_check_reset_blocked(hw)) 690 return 0; 691 692 /* Restart PHY autonegotiation and wait for completion */ 693 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 694 MDIO_MMD_AN, &autoneg_reg); 695 696 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 697 698 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 699 MDIO_MMD_AN, autoneg_reg); 700 701 return status; 702} 703 704/** 705 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 706 * @hw: pointer to hardware structure 707 * @speed: new link speed 708 **/ 709s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 710 ixgbe_link_speed speed, 711 bool autoneg_wait_to_complete) 712{ 713 714 /* 715 * Clear autoneg_advertised and set new values based on input link 716 * speed. 717 */ 718 hw->phy.autoneg_advertised = 0; 719 720 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 721 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 722 723 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 724 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 725 726 if (speed & IXGBE_LINK_SPEED_100_FULL) 727 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 728 729 /* Setup link based on the new speed settings */ 730 hw->phy.ops.setup_link(hw); 731 732 return 0; 733} 734 735/** 736 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 737 * @hw: pointer to hardware structure 738 * @speed: pointer to link speed 739 * @autoneg: boolean auto-negotiation value 740 * 741 * Determines the link capabilities by reading the AUTOC register. 742 */ 743s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 744 ixgbe_link_speed *speed, 745 bool *autoneg) 746{ 747 s32 status; 748 u16 speed_ability; 749 750 *speed = 0; 751 *autoneg = true; 752 753 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, 754 &speed_ability); 755 756 if (status == 0) { 757 if (speed_ability & MDIO_SPEED_10G) 758 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 759 if (speed_ability & MDIO_PMA_SPEED_1000) 760 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 761 if (speed_ability & MDIO_PMA_SPEED_100) 762 *speed |= IXGBE_LINK_SPEED_100_FULL; 763 } 764 765 /* Internal PHY does not support 100 Mbps */ 766 if (hw->mac.type == ixgbe_mac_X550EM_x) 767 *speed &= ~IXGBE_LINK_SPEED_100_FULL; 768 769 return status; 770} 771 772/** 773 * ixgbe_check_phy_link_tnx - Determine link and speed status 774 * @hw: pointer to hardware structure 775 * 776 * Reads the VS1 register to determine if link is up and the current speed for 777 * the PHY. 778 **/ 779s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 780 bool *link_up) 781{ 782 s32 status; 783 u32 time_out; 784 u32 max_time_out = 10; 785 u16 phy_link = 0; 786 u16 phy_speed = 0; 787 u16 phy_data = 0; 788 789 /* Initialize speed and link to default case */ 790 *link_up = false; 791 *speed = IXGBE_LINK_SPEED_10GB_FULL; 792 793 /* 794 * Check current speed and link status of the PHY register. 795 * This is a vendor specific register and may have to 796 * be changed for other copper PHYs. 797 */ 798 for (time_out = 0; time_out < max_time_out; time_out++) { 799 udelay(10); 800 status = hw->phy.ops.read_reg(hw, 801 MDIO_STAT1, 802 MDIO_MMD_VEND1, 803 &phy_data); 804 phy_link = phy_data & 805 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 806 phy_speed = phy_data & 807 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 808 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 809 *link_up = true; 810 if (phy_speed == 811 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 812 *speed = IXGBE_LINK_SPEED_1GB_FULL; 813 break; 814 } 815 } 816 817 return status; 818} 819 820/** 821 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 822 * @hw: pointer to hardware structure 823 * 824 * Restart autonegotiation and PHY and waits for completion. 825 * This function always returns success, this is nessary since 826 * it is called via a function pointer that could call other 827 * functions that could return an error. 828 **/ 829s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 830{ 831 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 832 bool autoneg = false; 833 ixgbe_link_speed speed; 834 835 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 836 837 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 838 /* Set or unset auto-negotiation 10G advertisement */ 839 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 840 MDIO_MMD_AN, 841 &autoneg_reg); 842 843 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 844 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 845 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 846 847 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 848 MDIO_MMD_AN, 849 autoneg_reg); 850 } 851 852 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 853 /* Set or unset auto-negotiation 1G advertisement */ 854 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 855 MDIO_MMD_AN, 856 &autoneg_reg); 857 858 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 859 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 860 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 861 862 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 863 MDIO_MMD_AN, 864 autoneg_reg); 865 } 866 867 if (speed & IXGBE_LINK_SPEED_100_FULL) { 868 /* Set or unset auto-negotiation 100M advertisement */ 869 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 870 MDIO_MMD_AN, 871 &autoneg_reg); 872 873 autoneg_reg &= ~(ADVERTISE_100FULL | 874 ADVERTISE_100HALF); 875 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 876 autoneg_reg |= ADVERTISE_100FULL; 877 878 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 879 MDIO_MMD_AN, 880 autoneg_reg); 881 } 882 883 /* Blocked by MNG FW so don't reset PHY */ 884 if (ixgbe_check_reset_blocked(hw)) 885 return 0; 886 887 /* Restart PHY autonegotiation and wait for completion */ 888 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 889 MDIO_MMD_AN, &autoneg_reg); 890 891 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 892 893 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 894 MDIO_MMD_AN, autoneg_reg); 895 return 0; 896} 897 898/** 899 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 900 * @hw: pointer to hardware structure 901 * @firmware_version: pointer to the PHY Firmware Version 902 **/ 903s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 904 u16 *firmware_version) 905{ 906 s32 status; 907 908 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 909 MDIO_MMD_VEND1, 910 firmware_version); 911 912 return status; 913} 914 915/** 916 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 917 * @hw: pointer to hardware structure 918 * @firmware_version: pointer to the PHY Firmware Version 919 **/ 920s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 921 u16 *firmware_version) 922{ 923 s32 status; 924 925 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 926 MDIO_MMD_VEND1, 927 firmware_version); 928 929 return status; 930} 931 932/** 933 * ixgbe_reset_phy_nl - Performs a PHY reset 934 * @hw: pointer to hardware structure 935 **/ 936s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 937{ 938 u16 phy_offset, control, eword, edata, block_crc; 939 bool end_data = false; 940 u16 list_offset, data_offset; 941 u16 phy_data = 0; 942 s32 ret_val; 943 u32 i; 944 945 /* Blocked by MNG FW so bail */ 946 if (ixgbe_check_reset_blocked(hw)) 947 return 0; 948 949 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); 950 951 /* reset the PHY and poll for completion */ 952 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 953 (phy_data | MDIO_CTRL1_RESET)); 954 955 for (i = 0; i < 100; i++) { 956 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 957 &phy_data); 958 if ((phy_data & MDIO_CTRL1_RESET) == 0) 959 break; 960 usleep_range(10000, 20000); 961 } 962 963 if ((phy_data & MDIO_CTRL1_RESET) != 0) { 964 hw_dbg(hw, "PHY reset did not complete.\n"); 965 return IXGBE_ERR_PHY; 966 } 967 968 /* Get init offsets */ 969 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 970 &data_offset); 971 if (ret_val) 972 return ret_val; 973 974 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 975 data_offset++; 976 while (!end_data) { 977 /* 978 * Read control word from PHY init contents offset 979 */ 980 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 981 if (ret_val) 982 goto err_eeprom; 983 control = (eword & IXGBE_CONTROL_MASK_NL) >> 984 IXGBE_CONTROL_SHIFT_NL; 985 edata = eword & IXGBE_DATA_MASK_NL; 986 switch (control) { 987 case IXGBE_DELAY_NL: 988 data_offset++; 989 hw_dbg(hw, "DELAY: %d MS\n", edata); 990 usleep_range(edata * 1000, edata * 2000); 991 break; 992 case IXGBE_DATA_NL: 993 hw_dbg(hw, "DATA:\n"); 994 data_offset++; 995 ret_val = hw->eeprom.ops.read(hw, data_offset++, 996 &phy_offset); 997 if (ret_val) 998 goto err_eeprom; 999 for (i = 0; i < edata; i++) { 1000 ret_val = hw->eeprom.ops.read(hw, data_offset, 1001 &eword); 1002 if (ret_val) 1003 goto err_eeprom; 1004 hw->phy.ops.write_reg(hw, phy_offset, 1005 MDIO_MMD_PMAPMD, eword); 1006 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, 1007 phy_offset); 1008 data_offset++; 1009 phy_offset++; 1010 } 1011 break; 1012 case IXGBE_CONTROL_NL: 1013 data_offset++; 1014 hw_dbg(hw, "CONTROL:\n"); 1015 if (edata == IXGBE_CONTROL_EOL_NL) { 1016 hw_dbg(hw, "EOL\n"); 1017 end_data = true; 1018 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1019 hw_dbg(hw, "SOL\n"); 1020 } else { 1021 hw_dbg(hw, "Bad control value\n"); 1022 return IXGBE_ERR_PHY; 1023 } 1024 break; 1025 default: 1026 hw_dbg(hw, "Bad control type\n"); 1027 return IXGBE_ERR_PHY; 1028 } 1029 } 1030 1031 return ret_val; 1032 1033err_eeprom: 1034 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); 1035 return IXGBE_ERR_PHY; 1036} 1037 1038/** 1039 * ixgbe_identify_module_generic - Identifies module type 1040 * @hw: pointer to hardware structure 1041 * 1042 * Determines HW type and calls appropriate function. 1043 **/ 1044s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1045{ 1046 switch (hw->mac.ops.get_media_type(hw)) { 1047 case ixgbe_media_type_fiber: 1048 return ixgbe_identify_sfp_module_generic(hw); 1049 case ixgbe_media_type_fiber_qsfp: 1050 return ixgbe_identify_qsfp_module_generic(hw); 1051 default: 1052 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1053 return IXGBE_ERR_SFP_NOT_PRESENT; 1054 } 1055 1056 return IXGBE_ERR_SFP_NOT_PRESENT; 1057} 1058 1059/** 1060 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1061 * @hw: pointer to hardware structure 1062 * 1063 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1064 **/ 1065s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1066{ 1067 struct ixgbe_adapter *adapter = hw->back; 1068 s32 status; 1069 u32 vendor_oui = 0; 1070 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1071 u8 identifier = 0; 1072 u8 comp_codes_1g = 0; 1073 u8 comp_codes_10g = 0; 1074 u8 oui_bytes[3] = {0, 0, 0}; 1075 u8 cable_tech = 0; 1076 u8 cable_spec = 0; 1077 u16 enforce_sfp = 0; 1078 1079 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1080 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1081 return IXGBE_ERR_SFP_NOT_PRESENT; 1082 } 1083 1084 status = hw->phy.ops.read_i2c_eeprom(hw, 1085 IXGBE_SFF_IDENTIFIER, 1086 &identifier); 1087 1088 if (status) 1089 goto err_read_i2c_eeprom; 1090 1091 /* LAN ID is needed for sfp_type determination */ 1092 hw->mac.ops.set_lan_id(hw); 1093 1094 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1095 hw->phy.type = ixgbe_phy_sfp_unsupported; 1096 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1097 } 1098 status = hw->phy.ops.read_i2c_eeprom(hw, 1099 IXGBE_SFF_1GBE_COMP_CODES, 1100 &comp_codes_1g); 1101 1102 if (status) 1103 goto err_read_i2c_eeprom; 1104 1105 status = hw->phy.ops.read_i2c_eeprom(hw, 1106 IXGBE_SFF_10GBE_COMP_CODES, 1107 &comp_codes_10g); 1108 1109 if (status) 1110 goto err_read_i2c_eeprom; 1111 status = hw->phy.ops.read_i2c_eeprom(hw, 1112 IXGBE_SFF_CABLE_TECHNOLOGY, 1113 &cable_tech); 1114 1115 if (status) 1116 goto err_read_i2c_eeprom; 1117 1118 /* ID Module 1119 * ========= 1120 * 0 SFP_DA_CU 1121 * 1 SFP_SR 1122 * 2 SFP_LR 1123 * 3 SFP_DA_CORE0 - 82599-specific 1124 * 4 SFP_DA_CORE1 - 82599-specific 1125 * 5 SFP_SR/LR_CORE0 - 82599-specific 1126 * 6 SFP_SR/LR_CORE1 - 82599-specific 1127 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1128 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1129 * 9 SFP_1g_cu_CORE0 - 82599-specific 1130 * 10 SFP_1g_cu_CORE1 - 82599-specific 1131 * 11 SFP_1g_sx_CORE0 - 82599-specific 1132 * 12 SFP_1g_sx_CORE1 - 82599-specific 1133 */ 1134 if (hw->mac.type == ixgbe_mac_82598EB) { 1135 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1136 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1137 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1138 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1139 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1140 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1141 else 1142 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1143 } else if (hw->mac.type == ixgbe_mac_82599EB) { 1144 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1145 if (hw->bus.lan_id == 0) 1146 hw->phy.sfp_type = 1147 ixgbe_sfp_type_da_cu_core0; 1148 else 1149 hw->phy.sfp_type = 1150 ixgbe_sfp_type_da_cu_core1; 1151 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1152 hw->phy.ops.read_i2c_eeprom( 1153 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1154 &cable_spec); 1155 if (cable_spec & 1156 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1157 if (hw->bus.lan_id == 0) 1158 hw->phy.sfp_type = 1159 ixgbe_sfp_type_da_act_lmt_core0; 1160 else 1161 hw->phy.sfp_type = 1162 ixgbe_sfp_type_da_act_lmt_core1; 1163 } else { 1164 hw->phy.sfp_type = 1165 ixgbe_sfp_type_unknown; 1166 } 1167 } else if (comp_codes_10g & 1168 (IXGBE_SFF_10GBASESR_CAPABLE | 1169 IXGBE_SFF_10GBASELR_CAPABLE)) { 1170 if (hw->bus.lan_id == 0) 1171 hw->phy.sfp_type = 1172 ixgbe_sfp_type_srlr_core0; 1173 else 1174 hw->phy.sfp_type = 1175 ixgbe_sfp_type_srlr_core1; 1176 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1177 if (hw->bus.lan_id == 0) 1178 hw->phy.sfp_type = 1179 ixgbe_sfp_type_1g_cu_core0; 1180 else 1181 hw->phy.sfp_type = 1182 ixgbe_sfp_type_1g_cu_core1; 1183 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1184 if (hw->bus.lan_id == 0) 1185 hw->phy.sfp_type = 1186 ixgbe_sfp_type_1g_sx_core0; 1187 else 1188 hw->phy.sfp_type = 1189 ixgbe_sfp_type_1g_sx_core1; 1190 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1191 if (hw->bus.lan_id == 0) 1192 hw->phy.sfp_type = 1193 ixgbe_sfp_type_1g_lx_core0; 1194 else 1195 hw->phy.sfp_type = 1196 ixgbe_sfp_type_1g_lx_core1; 1197 } else { 1198 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1199 } 1200 } 1201 1202 if (hw->phy.sfp_type != stored_sfp_type) 1203 hw->phy.sfp_setup_needed = true; 1204 1205 /* Determine if the SFP+ PHY is dual speed or not. */ 1206 hw->phy.multispeed_fiber = false; 1207 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1208 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1209 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1210 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1211 hw->phy.multispeed_fiber = true; 1212 1213 /* Determine PHY vendor */ 1214 if (hw->phy.type != ixgbe_phy_nl) { 1215 hw->phy.id = identifier; 1216 status = hw->phy.ops.read_i2c_eeprom(hw, 1217 IXGBE_SFF_VENDOR_OUI_BYTE0, 1218 &oui_bytes[0]); 1219 1220 if (status != 0) 1221 goto err_read_i2c_eeprom; 1222 1223 status = hw->phy.ops.read_i2c_eeprom(hw, 1224 IXGBE_SFF_VENDOR_OUI_BYTE1, 1225 &oui_bytes[1]); 1226 1227 if (status != 0) 1228 goto err_read_i2c_eeprom; 1229 1230 status = hw->phy.ops.read_i2c_eeprom(hw, 1231 IXGBE_SFF_VENDOR_OUI_BYTE2, 1232 &oui_bytes[2]); 1233 1234 if (status != 0) 1235 goto err_read_i2c_eeprom; 1236 1237 vendor_oui = 1238 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1239 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1240 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1241 1242 switch (vendor_oui) { 1243 case IXGBE_SFF_VENDOR_OUI_TYCO: 1244 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1245 hw->phy.type = 1246 ixgbe_phy_sfp_passive_tyco; 1247 break; 1248 case IXGBE_SFF_VENDOR_OUI_FTL: 1249 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1250 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1251 else 1252 hw->phy.type = ixgbe_phy_sfp_ftl; 1253 break; 1254 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1255 hw->phy.type = ixgbe_phy_sfp_avago; 1256 break; 1257 case IXGBE_SFF_VENDOR_OUI_INTEL: 1258 hw->phy.type = ixgbe_phy_sfp_intel; 1259 break; 1260 default: 1261 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1262 hw->phy.type = 1263 ixgbe_phy_sfp_passive_unknown; 1264 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1265 hw->phy.type = 1266 ixgbe_phy_sfp_active_unknown; 1267 else 1268 hw->phy.type = ixgbe_phy_sfp_unknown; 1269 break; 1270 } 1271 } 1272 1273 /* Allow any DA cable vendor */ 1274 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1275 IXGBE_SFF_DA_ACTIVE_CABLE)) 1276 return 0; 1277 1278 /* Verify supported 1G SFP modules */ 1279 if (comp_codes_10g == 0 && 1280 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1281 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1282 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1283 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1284 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1285 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1286 hw->phy.type = ixgbe_phy_sfp_unsupported; 1287 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1288 } 1289 1290 /* Anything else 82598-based is supported */ 1291 if (hw->mac.type == ixgbe_mac_82598EB) 1292 return 0; 1293 1294 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1295 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1296 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1297 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1298 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1299 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1300 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1301 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1302 /* Make sure we're a supported PHY type */ 1303 if (hw->phy.type == ixgbe_phy_sfp_intel) 1304 return 0; 1305 if (hw->allow_unsupported_sfp) { 1306 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1307 return 0; 1308 } 1309 hw_dbg(hw, "SFP+ module not supported\n"); 1310 hw->phy.type = ixgbe_phy_sfp_unsupported; 1311 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1312 } 1313 return 0; 1314 1315err_read_i2c_eeprom: 1316 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1317 if (hw->phy.type != ixgbe_phy_nl) { 1318 hw->phy.id = 0; 1319 hw->phy.type = ixgbe_phy_unknown; 1320 } 1321 return IXGBE_ERR_SFP_NOT_PRESENT; 1322} 1323 1324/** 1325 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1326 * @hw: pointer to hardware structure 1327 * 1328 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1329 **/ 1330static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1331{ 1332 struct ixgbe_adapter *adapter = hw->back; 1333 s32 status; 1334 u32 vendor_oui = 0; 1335 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1336 u8 identifier = 0; 1337 u8 comp_codes_1g = 0; 1338 u8 comp_codes_10g = 0; 1339 u8 oui_bytes[3] = {0, 0, 0}; 1340 u16 enforce_sfp = 0; 1341 u8 connector = 0; 1342 u8 cable_length = 0; 1343 u8 device_tech = 0; 1344 bool active_cable = false; 1345 1346 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1347 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1348 return IXGBE_ERR_SFP_NOT_PRESENT; 1349 } 1350 1351 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1352 &identifier); 1353 1354 if (status != 0) 1355 goto err_read_i2c_eeprom; 1356 1357 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1358 hw->phy.type = ixgbe_phy_sfp_unsupported; 1359 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1360 } 1361 1362 hw->phy.id = identifier; 1363 1364 /* LAN ID is needed for sfp_type determination */ 1365 hw->mac.ops.set_lan_id(hw); 1366 1367 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1368 &comp_codes_10g); 1369 1370 if (status != 0) 1371 goto err_read_i2c_eeprom; 1372 1373 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1374 &comp_codes_1g); 1375 1376 if (status != 0) 1377 goto err_read_i2c_eeprom; 1378 1379 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1380 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1381 if (hw->bus.lan_id == 0) 1382 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1383 else 1384 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1385 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1386 IXGBE_SFF_10GBASELR_CAPABLE)) { 1387 if (hw->bus.lan_id == 0) 1388 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1389 else 1390 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1391 } else { 1392 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1393 active_cable = true; 1394 1395 if (!active_cable) { 1396 /* check for active DA cables that pre-date 1397 * SFF-8436 v3.6 1398 */ 1399 hw->phy.ops.read_i2c_eeprom(hw, 1400 IXGBE_SFF_QSFP_CONNECTOR, 1401 &connector); 1402 1403 hw->phy.ops.read_i2c_eeprom(hw, 1404 IXGBE_SFF_QSFP_CABLE_LENGTH, 1405 &cable_length); 1406 1407 hw->phy.ops.read_i2c_eeprom(hw, 1408 IXGBE_SFF_QSFP_DEVICE_TECH, 1409 &device_tech); 1410 1411 if ((connector == 1412 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1413 (cable_length > 0) && 1414 ((device_tech >> 4) == 1415 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1416 active_cable = true; 1417 } 1418 1419 if (active_cable) { 1420 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1421 if (hw->bus.lan_id == 0) 1422 hw->phy.sfp_type = 1423 ixgbe_sfp_type_da_act_lmt_core0; 1424 else 1425 hw->phy.sfp_type = 1426 ixgbe_sfp_type_da_act_lmt_core1; 1427 } else { 1428 /* unsupported module type */ 1429 hw->phy.type = ixgbe_phy_sfp_unsupported; 1430 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1431 } 1432 } 1433 1434 if (hw->phy.sfp_type != stored_sfp_type) 1435 hw->phy.sfp_setup_needed = true; 1436 1437 /* Determine if the QSFP+ PHY is dual speed or not. */ 1438 hw->phy.multispeed_fiber = false; 1439 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1440 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1441 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1442 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1443 hw->phy.multispeed_fiber = true; 1444 1445 /* Determine PHY vendor for optical modules */ 1446 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1447 IXGBE_SFF_10GBASELR_CAPABLE)) { 1448 status = hw->phy.ops.read_i2c_eeprom(hw, 1449 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1450 &oui_bytes[0]); 1451 1452 if (status != 0) 1453 goto err_read_i2c_eeprom; 1454 1455 status = hw->phy.ops.read_i2c_eeprom(hw, 1456 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1457 &oui_bytes[1]); 1458 1459 if (status != 0) 1460 goto err_read_i2c_eeprom; 1461 1462 status = hw->phy.ops.read_i2c_eeprom(hw, 1463 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1464 &oui_bytes[2]); 1465 1466 if (status != 0) 1467 goto err_read_i2c_eeprom; 1468 1469 vendor_oui = 1470 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1471 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1472 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1473 1474 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1475 hw->phy.type = ixgbe_phy_qsfp_intel; 1476 else 1477 hw->phy.type = ixgbe_phy_qsfp_unknown; 1478 1479 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1480 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1481 /* Make sure we're a supported PHY type */ 1482 if (hw->phy.type == ixgbe_phy_qsfp_intel) 1483 return 0; 1484 if (hw->allow_unsupported_sfp) { 1485 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1486 return 0; 1487 } 1488 hw_dbg(hw, "QSFP module not supported\n"); 1489 hw->phy.type = ixgbe_phy_sfp_unsupported; 1490 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1491 } 1492 return 0; 1493 } 1494 return 0; 1495 1496err_read_i2c_eeprom: 1497 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1498 hw->phy.id = 0; 1499 hw->phy.type = ixgbe_phy_unknown; 1500 1501 return IXGBE_ERR_SFP_NOT_PRESENT; 1502} 1503 1504/** 1505 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1506 * @hw: pointer to hardware structure 1507 * @list_offset: offset to the SFP ID list 1508 * @data_offset: offset to the SFP data block 1509 * 1510 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1511 * so it returns the offsets to the phy init sequence block. 1512 **/ 1513s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1514 u16 *list_offset, 1515 u16 *data_offset) 1516{ 1517 u16 sfp_id; 1518 u16 sfp_type = hw->phy.sfp_type; 1519 1520 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1521 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1522 1523 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1524 return IXGBE_ERR_SFP_NOT_PRESENT; 1525 1526 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1527 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1528 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1529 1530 /* 1531 * Limiting active cables and 1G Phys must be initialized as 1532 * SR modules 1533 */ 1534 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1535 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1536 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1537 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1538 sfp_type = ixgbe_sfp_type_srlr_core0; 1539 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1540 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1541 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1542 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1543 sfp_type = ixgbe_sfp_type_srlr_core1; 1544 1545 /* Read offset to PHY init contents */ 1546 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1547 hw_err(hw, "eeprom read at %d failed\n", 1548 IXGBE_PHY_INIT_OFFSET_NL); 1549 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1550 } 1551 1552 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1553 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1554 1555 /* Shift offset to first ID word */ 1556 (*list_offset)++; 1557 1558 /* 1559 * Find the matching SFP ID in the EEPROM 1560 * and program the init sequence 1561 */ 1562 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1563 goto err_phy; 1564 1565 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1566 if (sfp_id == sfp_type) { 1567 (*list_offset)++; 1568 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1569 goto err_phy; 1570 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1571 hw_dbg(hw, "SFP+ module not supported\n"); 1572 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1573 } else { 1574 break; 1575 } 1576 } else { 1577 (*list_offset) += 2; 1578 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1579 goto err_phy; 1580 } 1581 } 1582 1583 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1584 hw_dbg(hw, "No matching SFP+ module found\n"); 1585 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1586 } 1587 1588 return 0; 1589 1590err_phy: 1591 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset); 1592 return IXGBE_ERR_PHY; 1593} 1594 1595/** 1596 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1597 * @hw: pointer to hardware structure 1598 * @byte_offset: EEPROM byte offset to read 1599 * @eeprom_data: value read 1600 * 1601 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1602 **/ 1603s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1604 u8 *eeprom_data) 1605{ 1606 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1607 IXGBE_I2C_EEPROM_DEV_ADDR, 1608 eeprom_data); 1609} 1610 1611/** 1612 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1613 * @hw: pointer to hardware structure 1614 * @byte_offset: byte offset at address 0xA2 1615 * @eeprom_data: value read 1616 * 1617 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1618 **/ 1619s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1620 u8 *sff8472_data) 1621{ 1622 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1623 IXGBE_I2C_EEPROM_DEV_ADDR2, 1624 sff8472_data); 1625} 1626 1627/** 1628 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1629 * @hw: pointer to hardware structure 1630 * @byte_offset: EEPROM byte offset to write 1631 * @eeprom_data: value to write 1632 * 1633 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1634 **/ 1635s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1636 u8 eeprom_data) 1637{ 1638 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1639 IXGBE_I2C_EEPROM_DEV_ADDR, 1640 eeprom_data); 1641} 1642 1643/** 1644 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1645 * @hw: pointer to hardware structure 1646 * @byte_offset: byte offset to read 1647 * @data: value read 1648 * 1649 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1650 * a specified device address. 1651 **/ 1652s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1653 u8 dev_addr, u8 *data) 1654{ 1655 s32 status; 1656 u32 max_retry = 10; 1657 u32 retry = 0; 1658 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1659 bool nack = true; 1660 *data = 0; 1661 1662 do { 1663 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 1664 return IXGBE_ERR_SWFW_SYNC; 1665 1666 ixgbe_i2c_start(hw); 1667 1668 /* Device Address and write indication */ 1669 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1670 if (status != 0) 1671 goto fail; 1672 1673 status = ixgbe_get_i2c_ack(hw); 1674 if (status != 0) 1675 goto fail; 1676 1677 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1678 if (status != 0) 1679 goto fail; 1680 1681 status = ixgbe_get_i2c_ack(hw); 1682 if (status != 0) 1683 goto fail; 1684 1685 ixgbe_i2c_start(hw); 1686 1687 /* Device Address and read indication */ 1688 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1689 if (status != 0) 1690 goto fail; 1691 1692 status = ixgbe_get_i2c_ack(hw); 1693 if (status != 0) 1694 goto fail; 1695 1696 status = ixgbe_clock_in_i2c_byte(hw, data); 1697 if (status != 0) 1698 goto fail; 1699 1700 status = ixgbe_clock_out_i2c_bit(hw, nack); 1701 if (status != 0) 1702 goto fail; 1703 1704 ixgbe_i2c_stop(hw); 1705 break; 1706 1707fail: 1708 ixgbe_i2c_bus_clear(hw); 1709 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1710 msleep(100); 1711 retry++; 1712 if (retry < max_retry) 1713 hw_dbg(hw, "I2C byte read error - Retrying.\n"); 1714 else 1715 hw_dbg(hw, "I2C byte read error.\n"); 1716 1717 } while (retry < max_retry); 1718 1719 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1720 1721 return status; 1722} 1723 1724/** 1725 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1726 * @hw: pointer to hardware structure 1727 * @byte_offset: byte offset to write 1728 * @data: value to write 1729 * 1730 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1731 * a specified device address. 1732 **/ 1733s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1734 u8 dev_addr, u8 data) 1735{ 1736 s32 status; 1737 u32 max_retry = 1; 1738 u32 retry = 0; 1739 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1740 1741 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 1742 return IXGBE_ERR_SWFW_SYNC; 1743 1744 do { 1745 ixgbe_i2c_start(hw); 1746 1747 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1748 if (status != 0) 1749 goto fail; 1750 1751 status = ixgbe_get_i2c_ack(hw); 1752 if (status != 0) 1753 goto fail; 1754 1755 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1756 if (status != 0) 1757 goto fail; 1758 1759 status = ixgbe_get_i2c_ack(hw); 1760 if (status != 0) 1761 goto fail; 1762 1763 status = ixgbe_clock_out_i2c_byte(hw, data); 1764 if (status != 0) 1765 goto fail; 1766 1767 status = ixgbe_get_i2c_ack(hw); 1768 if (status != 0) 1769 goto fail; 1770 1771 ixgbe_i2c_stop(hw); 1772 break; 1773 1774fail: 1775 ixgbe_i2c_bus_clear(hw); 1776 retry++; 1777 if (retry < max_retry) 1778 hw_dbg(hw, "I2C byte write error - Retrying.\n"); 1779 else 1780 hw_dbg(hw, "I2C byte write error.\n"); 1781 } while (retry < max_retry); 1782 1783 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1784 1785 return status; 1786} 1787 1788/** 1789 * ixgbe_i2c_start - Sets I2C start condition 1790 * @hw: pointer to hardware structure 1791 * 1792 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1793 **/ 1794static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1795{ 1796 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 1797 1798 /* Start condition must begin with data and clock high */ 1799 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1800 ixgbe_raise_i2c_clk(hw, &i2cctl); 1801 1802 /* Setup time for start condition (4.7us) */ 1803 udelay(IXGBE_I2C_T_SU_STA); 1804 1805 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1806 1807 /* Hold time for start condition (4us) */ 1808 udelay(IXGBE_I2C_T_HD_STA); 1809 1810 ixgbe_lower_i2c_clk(hw, &i2cctl); 1811 1812 /* Minimum low period of clock is 4.7 us */ 1813 udelay(IXGBE_I2C_T_LOW); 1814 1815} 1816 1817/** 1818 * ixgbe_i2c_stop - Sets I2C stop condition 1819 * @hw: pointer to hardware structure 1820 * 1821 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1822 **/ 1823static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1824{ 1825 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 1826 1827 /* Stop condition must begin with data low and clock high */ 1828 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1829 ixgbe_raise_i2c_clk(hw, &i2cctl); 1830 1831 /* Setup time for stop condition (4us) */ 1832 udelay(IXGBE_I2C_T_SU_STO); 1833 1834 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1835 1836 /* bus free time between stop and start (4.7us)*/ 1837 udelay(IXGBE_I2C_T_BUF); 1838} 1839 1840/** 1841 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1842 * @hw: pointer to hardware structure 1843 * @data: data byte to clock in 1844 * 1845 * Clocks in one byte data via I2C data/clock 1846 **/ 1847static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1848{ 1849 s32 i; 1850 bool bit = false; 1851 1852 for (i = 7; i >= 0; i--) { 1853 ixgbe_clock_in_i2c_bit(hw, &bit); 1854 *data |= bit << i; 1855 } 1856 1857 return 0; 1858} 1859 1860/** 1861 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1862 * @hw: pointer to hardware structure 1863 * @data: data byte clocked out 1864 * 1865 * Clocks out one byte data via I2C data/clock 1866 **/ 1867static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1868{ 1869 s32 status; 1870 s32 i; 1871 u32 i2cctl; 1872 bool bit = false; 1873 1874 for (i = 7; i >= 0; i--) { 1875 bit = (data >> i) & 0x1; 1876 status = ixgbe_clock_out_i2c_bit(hw, bit); 1877 1878 if (status != 0) 1879 break; 1880 } 1881 1882 /* Release SDA line (set high) */ 1883 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 1884 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 1885 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 1886 IXGBE_WRITE_FLUSH(hw); 1887 1888 return status; 1889} 1890 1891/** 1892 * ixgbe_get_i2c_ack - Polls for I2C ACK 1893 * @hw: pointer to hardware structure 1894 * 1895 * Clocks in/out one bit via I2C data/clock 1896 **/ 1897static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1898{ 1899 s32 status = 0; 1900 u32 i = 0; 1901 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 1902 u32 timeout = 10; 1903 bool ack = true; 1904 1905 ixgbe_raise_i2c_clk(hw, &i2cctl); 1906 1907 1908 /* Minimum high period of clock is 4us */ 1909 udelay(IXGBE_I2C_T_HIGH); 1910 1911 /* Poll for ACK. Note that ACK in I2C spec is 1912 * transition from 1 to 0 */ 1913 for (i = 0; i < timeout; i++) { 1914 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 1915 ack = ixgbe_get_i2c_data(hw, &i2cctl); 1916 1917 udelay(1); 1918 if (ack == 0) 1919 break; 1920 } 1921 1922 if (ack == 1) { 1923 hw_dbg(hw, "I2C ack was not received.\n"); 1924 status = IXGBE_ERR_I2C; 1925 } 1926 1927 ixgbe_lower_i2c_clk(hw, &i2cctl); 1928 1929 /* Minimum low period of clock is 4.7 us */ 1930 udelay(IXGBE_I2C_T_LOW); 1931 1932 return status; 1933} 1934 1935/** 1936 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1937 * @hw: pointer to hardware structure 1938 * @data: read data value 1939 * 1940 * Clocks in one bit via I2C data/clock 1941 **/ 1942static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1943{ 1944 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 1945 1946 ixgbe_raise_i2c_clk(hw, &i2cctl); 1947 1948 /* Minimum high period of clock is 4us */ 1949 udelay(IXGBE_I2C_T_HIGH); 1950 1951 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 1952 *data = ixgbe_get_i2c_data(hw, &i2cctl); 1953 1954 ixgbe_lower_i2c_clk(hw, &i2cctl); 1955 1956 /* Minimum low period of clock is 4.7 us */ 1957 udelay(IXGBE_I2C_T_LOW); 1958 1959 return 0; 1960} 1961 1962/** 1963 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1964 * @hw: pointer to hardware structure 1965 * @data: data value to write 1966 * 1967 * Clocks out one bit via I2C data/clock 1968 **/ 1969static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1970{ 1971 s32 status; 1972 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 1973 1974 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1975 if (status == 0) { 1976 ixgbe_raise_i2c_clk(hw, &i2cctl); 1977 1978 /* Minimum high period of clock is 4us */ 1979 udelay(IXGBE_I2C_T_HIGH); 1980 1981 ixgbe_lower_i2c_clk(hw, &i2cctl); 1982 1983 /* Minimum low period of clock is 4.7 us. 1984 * This also takes care of the data hold time. 1985 */ 1986 udelay(IXGBE_I2C_T_LOW); 1987 } else { 1988 hw_dbg(hw, "I2C data was not set to %X\n", data); 1989 return IXGBE_ERR_I2C; 1990 } 1991 1992 return 0; 1993} 1994/** 1995 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1996 * @hw: pointer to hardware structure 1997 * @i2cctl: Current value of I2CCTL register 1998 * 1999 * Raises the I2C clock line '0'->'1' 2000 **/ 2001static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2002{ 2003 u32 i = 0; 2004 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2005 u32 i2cctl_r = 0; 2006 2007 for (i = 0; i < timeout; i++) { 2008 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2009 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2010 IXGBE_WRITE_FLUSH(hw); 2011 /* SCL rise time (1000ns) */ 2012 udelay(IXGBE_I2C_T_RISE); 2013 2014 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2015 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2016 break; 2017 } 2018} 2019 2020/** 2021 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2022 * @hw: pointer to hardware structure 2023 * @i2cctl: Current value of I2CCTL register 2024 * 2025 * Lowers the I2C clock line '1'->'0' 2026 **/ 2027static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2028{ 2029 2030 *i2cctl &= ~IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2031 2032 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2033 IXGBE_WRITE_FLUSH(hw); 2034 2035 /* SCL fall time (300ns) */ 2036 udelay(IXGBE_I2C_T_FALL); 2037} 2038 2039/** 2040 * ixgbe_set_i2c_data - Sets the I2C data bit 2041 * @hw: pointer to hardware structure 2042 * @i2cctl: Current value of I2CCTL register 2043 * @data: I2C data value (0 or 1) to set 2044 * 2045 * Sets the I2C data bit 2046 **/ 2047static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2048{ 2049 if (data) 2050 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2051 else 2052 *i2cctl &= ~IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2053 2054 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2055 IXGBE_WRITE_FLUSH(hw); 2056 2057 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2058 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2059 2060 /* Verify data was set correctly */ 2061 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2062 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2063 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); 2064 return IXGBE_ERR_I2C; 2065 } 2066 2067 return 0; 2068} 2069 2070/** 2071 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2072 * @hw: pointer to hardware structure 2073 * @i2cctl: Current value of I2CCTL register 2074 * 2075 * Returns the I2C data bit value 2076 **/ 2077static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2078{ 2079 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2080 return true; 2081 return false; 2082} 2083 2084/** 2085 * ixgbe_i2c_bus_clear - Clears the I2C bus 2086 * @hw: pointer to hardware structure 2087 * 2088 * Clears the I2C bus by sending nine clock pulses. 2089 * Used when data line is stuck low. 2090 **/ 2091static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2092{ 2093 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2094 u32 i; 2095 2096 ixgbe_i2c_start(hw); 2097 2098 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2099 2100 for (i = 0; i < 9; i++) { 2101 ixgbe_raise_i2c_clk(hw, &i2cctl); 2102 2103 /* Min high period of clock is 4us */ 2104 udelay(IXGBE_I2C_T_HIGH); 2105 2106 ixgbe_lower_i2c_clk(hw, &i2cctl); 2107 2108 /* Min low period of clock is 4.7us*/ 2109 udelay(IXGBE_I2C_T_LOW); 2110 } 2111 2112 ixgbe_i2c_start(hw); 2113 2114 /* Put the i2c bus back to default state */ 2115 ixgbe_i2c_stop(hw); 2116} 2117 2118/** 2119 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2120 * @hw: pointer to hardware structure 2121 * 2122 * Checks if the LASI temp alarm status was triggered due to overtemp 2123 **/ 2124s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2125{ 2126 u16 phy_data = 0; 2127 2128 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2129 return 0; 2130 2131 /* Check that the LASI temp alarm status was triggered */ 2132 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2133 MDIO_MMD_PMAPMD, &phy_data); 2134 2135 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2136 return 0; 2137 2138 return IXGBE_ERR_OVERTEMP; 2139} 2140