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Searched refs:CLK_SET_RATE_PARENT (Results 1 – 104 of 104) sorted by relevance

/linux-4.1.27/drivers/clk/hisilicon/
Dclk-hi3620.c102 …{ HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0,…
103 …{ HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0,…
104 …{ HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0,…
105 …{ HI3620_TIMER3_MUX, "timer3_mux", timer3_mux_p, ARRAY_SIZE(timer3_mux_p), CLK_SET_RATE_PARENT, 0,…
106 …{ HI3620_TIMER4_MUX, "timer4_mux", timer4_mux_p, ARRAY_SIZE(timer4_mux_p), CLK_SET_RATE_PARENT, 0x…
107 …{ HI3620_TIMER5_MUX, "timer5_mux", timer5_mux_p, ARRAY_SIZE(timer5_mux_p), CLK_SET_RATE_PARENT, 0x…
108 …{ HI3620_TIMER6_MUX, "timer6_mux", timer6_mux_p, ARRAY_SIZE(timer6_mux_p), CLK_SET_RATE_PARENT, 0x…
109 …{ HI3620_TIMER7_MUX, "timer7_mux", timer7_mux_p, ARRAY_SIZE(timer7_mux_p), CLK_SET_RATE_PARENT, 0x…
110 …{ HI3620_TIMER8_MUX, "timer8_mux", timer8_mux_p, ARRAY_SIZE(timer8_mux_p), CLK_SET_RATE_PARENT, 0x…
111 …{ HI3620_TIMER9_MUX, "timer9_mux", timer9_mux_p, ARRAY_SIZE(timer9_mux_p), CLK_SET_RATE_PARENT, 0x…
[all …]
Dclk-hix5hd2.c63 CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
65 CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio_mux_table, },
67 CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, },
70 CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
76 CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
78 CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
81 CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
83 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
85 CLK_SET_RATE_PARENT, 0x9c, 4, CLK_GATE_SET_TO_DISABLE, },
88 CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
[all …]
/linux-4.1.27/drivers/clk/mmp/
Dclk-of-mmp2.c119 CLK_SET_RATE_PARENT, in mmp2_pll_init()
140 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
141 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
142 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
143 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3…
144 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
145 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
146 …{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4,…
147 …{0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4,…
151 …{MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_…
[all …]
Dclk-of-pxa168.c103 CLK_SET_RATE_PARENT, in pxa168_pll_init()
125 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
126 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
127 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
128 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
129 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
130 …{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4,…
131 …{0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4,…
132 …{0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4,…
136 …{PXA168_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, …
[all …]
Dclk-of-pxa910.c102 CLK_SET_RATE_PARENT, in pxa910_pll_init()
121 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
122 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
123 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
124 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
128 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART…
132 …{PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, …
133 …{PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_l…
134 …{PXA910_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NE…
135 …{PXA910_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_…
[all …]
Dclk-mmp2.c124 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
128 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
132 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
136 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
140 CLK_SET_RATE_PARENT, 1, 5); in mmp2_clk_init()
144 CLK_SET_RATE_PARENT, 1, 3); in mmp2_clk_init()
148 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
152 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
156 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
160 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
[all …]
Dclk-pxa168.c107 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
111 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
115 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
119 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
123 CLK_SET_RATE_PARENT, 1, 3); in pxa168_clk_init()
127 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
131 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
135 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
139 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
143 CLK_SET_RATE_PARENT, 1, 13); in pxa168_clk_init()
[all …]
Dclk-pxa910.c112 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
116 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
120 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
124 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
128 CLK_SET_RATE_PARENT, 1, 3); in pxa910_clk_init()
132 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
136 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
140 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
144 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
148 CLK_SET_RATE_PARENT, 1, 13); in pxa910_clk_init()
[all …]
Dclk-apmu.c82 init.flags = CLK_SET_RATE_PARENT; in mmp_clk_register_apmu()
Dclk-apbc.c137 init.flags = CLK_SET_RATE_PARENT; in mmp_clk_register_apbc()
/linux-4.1.27/drivers/clk/samsung/
Dclk-exynos4415.c405 CLK_SET_RATE_PARENT, 0),
482 CLK_SET_RATE_PARENT, 0),
489 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
492 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
502 CLK_SET_RATE_PARENT, 0),
507 CLK_SET_RATE_PARENT, 0),
510 CLK_SET_RATE_PARENT, 0),
515 CLK_SET_RATE_PARENT, 0),
517 CLK_SET_RATE_PARENT, 0),
527 CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos5250.c294 CLK_SET_RATE_PARENT, 0, "mout_apll"),
409 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
423 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
426 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
430 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
433 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
442 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
445 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
449 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
482 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos4.c538 CLK_SET_RATE_PARENT, 0, "mout_apll"),
543 CLK_SET_RATE_PARENT, 0),
545 CLK_SET_RATE_PARENT, 0),
594 CLK_SET_RATE_PARENT, 0),
671 CLK_SET_RATE_PARENT, 0),
758 CLK_SET_RATE_PARENT, 0),
774 CLK_SET_RATE_PARENT, 0),
776 CLK_SET_RATE_PARENT, 0),
778 CLK_SET_RATE_PARENT, 0),
780 CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos3250.c365 CLK_SET_RATE_PARENT, 0),
372 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
375 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
380 CLK_SET_RATE_PARENT, 0),
385 CLK_SET_RATE_PARENT, 0),
388 CLK_SET_RATE_PARENT, 0),
397 CLK_SET_RATE_PARENT, 0),
400 CLK_SET_RATE_PARENT, 0),
500 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
502 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-s5pv210.c632 CLK_SET_RATE_PARENT, 0),
634 CLK_SET_RATE_PARENT, 0),
636 CLK_SET_RATE_PARENT, 0),
638 CLK_SET_RATE_PARENT, 0),
640 CLK_SET_RATE_PARENT, 0),
642 CLK_SET_RATE_PARENT, 0),
644 CLK_SET_RATE_PARENT, 0),
646 CLK_SET_RATE_PARENT, 0),
648 CLK_SET_RATE_PARENT, 0),
650 CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos5410.c131 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
133 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
135 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
150 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
152 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
154 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
165 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
167 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
169 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
Dclk-exynos7.c308 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
310 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
312 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
315 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
317 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
320 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
322 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
332 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
457 ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
462 ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos5420.c890 CLK_SET_RATE_PARENT, 0),
892 CLK_SET_RATE_PARENT, 0),
951 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
953 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
955 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
957 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
959 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
961 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
963 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
965 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos5433.c505 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
507 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
579 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
582 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
585 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
588 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
591 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
594 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
597 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
600 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
[all …]
Dclk-exynos-audss.c190 "dout_srp", CLK_SET_RATE_PARENT, in exynos_audss_clk_probe()
194 "dout_aud_bus", CLK_SET_RATE_PARENT, in exynos_audss_clk_probe()
198 "dout_i2s", CLK_SET_RATE_PARENT, in exynos_audss_clk_probe()
202 "sclk_pcm", CLK_SET_RATE_PARENT, in exynos_audss_clk_probe()
209 sclk_pcm_p, CLK_SET_RATE_PARENT, in exynos_audss_clk_probe()
214 "dout_srp", CLK_SET_RATE_PARENT, in exynos_audss_clk_probe()
Dclk-exynos5260.c120 EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),
122 EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0),
124 EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0),
291 EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),
294 EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0),
722 EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0),
724 EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0),
889 EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0),
891 EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
893 EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos-clkout.c106 &clk_gate_ops, CLK_SET_RATE_PARENT in exynos_clkout_init()
Dclk-s3c2410-dclk.c290 "div_dclk0", CLK_SET_RATE_PARENT, in s3c24xx_dclk_probe()
294 "div_dclk1", CLK_SET_RATE_PARENT, in s3c24xx_dclk_probe()
Dclk-s5pv210-audss.c143 "dout_i2s_audss", CLK_SET_RATE_PARENT, in s5pv210_audss_clk_probe()
Dclk-s3c2412.c116 FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT),
Dclk-s3c2410.c281 FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
Dclk-s3c64xx.c56 GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0)
/linux-4.1.27/drivers/clk/qcom/
Dmmcc-apq8084.c590 .flags = CLK_SET_RATE_PARENT,
605 .flags = CLK_SET_RATE_PARENT,
862 .flags = CLK_SET_RATE_PARENT,
876 .flags = CLK_SET_RATE_PARENT,
914 .flags = CLK_SET_RATE_PARENT,
983 .flags = CLK_SET_RATE_PARENT,
1132 .flags = CLK_SET_RATE_PARENT,
1149 .flags = CLK_SET_RATE_PARENT,
1166 .flags = CLK_SET_RATE_PARENT,
1183 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-msm8916.c924 .flags = CLK_SET_RATE_PARENT,
987 .flags = CLK_SET_RATE_PARENT,
1164 .flags = CLK_SET_RATE_PARENT,
1181 .flags = CLK_SET_RATE_PARENT,
1198 .flags = CLK_SET_RATE_PARENT,
1215 .flags = CLK_SET_RATE_PARENT,
1232 .flags = CLK_SET_RATE_PARENT,
1249 .flags = CLK_SET_RATE_PARENT,
1266 .flags = CLK_SET_RATE_PARENT,
1283 .flags = CLK_SET_RATE_PARENT,
[all …]
Dmmcc-msm8974.c541 .flags = CLK_SET_RATE_PARENT,
556 .flags = CLK_SET_RATE_PARENT,
789 .flags = CLK_SET_RATE_PARENT,
803 .flags = CLK_SET_RATE_PARENT,
841 .flags = CLK_SET_RATE_PARENT,
910 .flags = CLK_SET_RATE_PARENT,
977 .flags = CLK_SET_RATE_PARENT,
1010 .flags = CLK_SET_RATE_PARENT,
1027 .flags = CLK_SET_RATE_PARENT,
1044 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-apq8084.c297 .flags = CLK_SET_RATE_PARENT,
314 .flags = CLK_SET_RATE_PARENT,
1340 .flags = CLK_SET_RATE_PARENT,
1427 .flags = CLK_SET_RATE_PARENT,
1444 .flags = CLK_SET_RATE_PARENT,
1461 .flags = CLK_SET_RATE_PARENT,
1478 .flags = CLK_SET_RATE_PARENT,
1495 .flags = CLK_SET_RATE_PARENT,
1512 .flags = CLK_SET_RATE_PARENT,
1529 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-msm8974.c1105 .flags = CLK_SET_RATE_PARENT,
1122 .flags = CLK_SET_RATE_PARENT,
1139 .flags = CLK_SET_RATE_PARENT,
1156 .flags = CLK_SET_RATE_PARENT,
1173 .flags = CLK_SET_RATE_PARENT,
1190 .flags = CLK_SET_RATE_PARENT,
1207 .flags = CLK_SET_RATE_PARENT,
1224 .flags = CLK_SET_RATE_PARENT,
1241 .flags = CLK_SET_RATE_PARENT,
1258 .flags = CLK_SET_RATE_PARENT,
[all …]
Dlcc-msm8960.c146 .flags = CLK_SET_RATE_PARENT,
179 .flags = CLK_SET_RATE_PARENT,
197 .flags = CLK_SET_RATE_PARENT,
252 .flags = CLK_SET_RATE_PARENT, \
285 .flags = CLK_SET_RATE_PARENT, \
303 .flags = CLK_SET_RATE_PARENT, \
392 .flags = CLK_SET_RATE_PARENT,
410 .flags = CLK_SET_RATE_PARENT,
464 .flags = CLK_SET_RATE_PARENT,
481 .flags = CLK_SET_RATE_PARENT,
Dgcc-msm8660.c154 .flags = CLK_SET_RATE_PARENT,
205 .flags = CLK_SET_RATE_PARENT,
256 .flags = CLK_SET_RATE_PARENT,
307 .flags = CLK_SET_RATE_PARENT,
358 .flags = CLK_SET_RATE_PARENT,
409 .flags = CLK_SET_RATE_PARENT,
460 .flags = CLK_SET_RATE_PARENT,
509 .flags = CLK_SET_RATE_PARENT,
558 .flags = CLK_SET_RATE_PARENT,
607 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-msm8960.c221 .flags = CLK_SET_RATE_PARENT,
272 .flags = CLK_SET_RATE_PARENT,
323 .flags = CLK_SET_RATE_PARENT,
374 .flags = CLK_SET_RATE_PARENT,
425 .flags = CLK_SET_RATE_PARENT,
476 .flags = CLK_SET_RATE_PARENT,
527 .flags = CLK_SET_RATE_PARENT,
576 .flags = CLK_SET_RATE_PARENT,
625 .flags = CLK_SET_RATE_PARENT,
674 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-ipq806x.c264 .flags = CLK_SET_RATE_PARENT,
315 .flags = CLK_SET_RATE_PARENT,
366 .flags = CLK_SET_RATE_PARENT,
417 .flags = CLK_SET_RATE_PARENT,
468 .flags = CLK_SET_RATE_PARENT,
519 .flags = CLK_SET_RATE_PARENT,
581 .flags = CLK_SET_RATE_PARENT,
630 .flags = CLK_SET_RATE_PARENT,
679 .flags = CLK_SET_RATE_PARENT,
728 .flags = CLK_SET_RATE_PARENT,
[all …]
Dmmcc-msm8960.c345 .flags = CLK_SET_RATE_PARENT,
361 .flags = CLK_SET_RATE_PARENT,
409 .flags = CLK_SET_RATE_PARENT,
425 .flags = CLK_SET_RATE_PARENT,
473 .flags = CLK_SET_RATE_PARENT,
489 .flags = CLK_SET_RATE_PARENT,
725 .flags = CLK_SET_RATE_PARENT,
741 .flags = CLK_SET_RATE_PARENT,
757 .flags = CLK_SET_RATE_PARENT,
833 .flags = CLK_SET_RATE_PARENT,
[all …]
Dlcc-ipq806x.c165 .flags = CLK_SET_RATE_PARENT,
196 .flags = CLK_SET_RATE_PARENT,
215 .flags = CLK_SET_RATE_PARENT,
275 .flags = CLK_SET_RATE_PARENT,
293 .flags = CLK_SET_RATE_PARENT,
359 .flags = CLK_SET_RATE_PARENT,
Dclk-rcg2.c198 if (clk_flags & CLK_SET_RATE_PARENT) { in _freq_tbl_determine_rate()
Dclk-rcg.c427 if (clk_flags & CLK_SET_RATE_PARENT) { in _freq_tbl_determine_rate()
/linux-4.1.27/drivers/clk/spear/
Dspear3xx_clock.c299 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
305 CLK_SET_RATE_PARENT, 1, in spear320_clk_init()
319 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
326 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
342 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
351 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
360 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
367 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
374 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
381 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
[all …]
Dspear1340_clock.c645 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1340_clk_init()
651 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, in spear1340_clk_init()
679 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, in spear1340_clk_init()
690 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, in spear1340_clk_init()
703 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1340_clk_init()
708 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT, in spear1340_clk_init()
748 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1340_clk_init()
766 CLK_SET_RATE_PARENT, SPEAR1340_I2S_CLK_CFG, in spear1340_clk_init()
773 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1340_clk_init()
862 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, in spear1340_clk_init()
[all …]
Dspear1310_clock.c497 CLK_SET_RATE_PARENT, 1, 2); in spear1310_clk_init()
566 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
572 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, in spear1310_clk_init()
583 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, in spear1310_clk_init()
594 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, in spear1310_clk_init()
607 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
652 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
676 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
777 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, in spear1310_clk_init()
Dspear6xx_clock.c157 CLK_SET_RATE_PARENT, 1, 1); in spear6xx_clk_init()
161 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, in spear6xx_clk_init()
288 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, in spear6xx_clk_init()
Dclk-aux-synth.c183 CLK_SET_RATE_PARENT, reg, in clk_register_aux()
Dclk-vco-pll.c338 pll_init.flags = CLK_SET_RATE_PARENT; in clk_register_vco_pll()
/linux-4.1.27/drivers/clk/tegra/
Dclk-tegra-super-gen4.c64 CLK_SET_RATE_PARENT, in tegra_sclk_init()
77 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, in tegra_sclk_init()
91 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | in tegra_sclk_init()
110 CLK_SET_RATE_PARENT, in tegra_super_clk_gen4_init()
121 CLK_SET_RATE_PARENT, in tegra_super_clk_gen4_init()
145 CLK_SET_RATE_PARENT, 1, 2); in tegra_super_clk_gen4_init()
Dclk-tegra-fixed.c101 CLK_SET_RATE_PARENT, 1, 2); in tegra_fixed_clk_init()
109 CLK_SET_RATE_PARENT, 1, 4); in tegra_fixed_clk_init()
Dclk-tegra-audio.c151 CLK_SET_RATE_PARENT, 0, NULL); in tegra_audio_clk_init()
203 data->parent, CLK_SET_RATE_PARENT, 2, 1); in tegra_audio_clk_init()
210 clk_base, CLK_SET_RATE_PARENT, data->clk_num, in tegra_audio_clk_init()
Dclk-tegra20.c650 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra20_pll_init()
666 CLK_SET_RATE_PARENT, 0, NULL); in tegra20_pll_init()
686 CLK_SET_RATE_PARENT, 1, 2); in tegra20_pll_init()
700 CLK_SET_RATE_PARENT, 0, NULL); in tegra20_pll_init()
722 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, in tegra20_super_clk_init()
728 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT, in tegra20_super_clk_init()
757 CLK_SET_RATE_PARENT, 2, 1); in tegra20_audio_clk_init()
760 CLK_SET_RATE_PARENT, 89, in tegra20_audio_clk_init()
894 CLK_SET_RATE_PARENT, 1, pll_ref_div); in tegra20_osc_clk_init()
Dclk-tegra114.c954 CLK_SET_RATE_PARENT, 1, 2); in tegra114_fixed_clk_init()
959 CLK_SET_RATE_PARENT, 1, 4); in tegra114_fixed_clk_init()
1063 CLK_SET_RATE_PARENT, 0, NULL); in tegra114_pll_init()
1088 CLK_SET_RATE_PARENT, 0, NULL); in tegra114_pll_init()
1093 CLK_SET_RATE_PARENT, 1, 1); in tegra114_pll_init()
1108 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra114_pll_init()
1114 CLK_SET_RATE_PARENT, 1, 8); in tegra114_pll_init()
1119 CLK_SET_RATE_PARENT, 1, 10); in tegra114_pll_init()
1124 CLK_SET_RATE_PARENT, 1, 40); in tegra114_pll_init()
1134 CLK_SET_RATE_PARENT, 1, 2); in tegra114_pll_init()
[all …]
Dclk-tegra124.c1173 CLK_SET_RATE_PARENT, 0, NULL); in tegra124_pll_init()
1179 CLK_SET_RATE_PARENT, 1, 1); in tegra124_pll_init()
1208 CLK_SET_RATE_PARENT, 0, NULL); in tegra124_pll_init()
1214 CLK_SET_RATE_PARENT, 1, 1); in tegra124_pll_init()
1232 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra124_pll_init()
1239 CLK_SET_RATE_PARENT, 1, 8); in tegra124_pll_init()
1245 CLK_SET_RATE_PARENT, 1, 10); in tegra124_pll_init()
1251 CLK_SET_RATE_PARENT, 1, 40); in tegra124_pll_init()
1263 CLK_SET_RATE_PARENT, 1, 2); in tegra124_pll_init()
1305 CLK_SET_RATE_PARENT, 1, 1); in tegra124_pll_init()
Dclk-tegra30.c937 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra30_pll_init()
953 CLK_SET_RATE_PARENT, 0, NULL); in tegra30_pll_init()
963 CLK_SET_RATE_PARENT, 1, 2); in tegra30_pll_init()
980 CLK_SET_RATE_PARENT, 1, 2); in tegra30_pll_init()
990 CLK_SET_RATE_PARENT, 1, 2); in tegra30_pll_init()
1048 CLK_SET_RATE_PARENT, in tegra30_super_clk_init()
1083 CLK_SET_RATE_PARENT, in tegra30_super_clk_init()
1092 CLK_SET_RATE_PARENT, in tegra30_super_clk_init()
1099 CLK_SET_RATE_PARENT, 1, 2); in tegra30_super_clk_init()
Dclk-periph.c153 flags |= CLK_SET_RATE_PARENT; in _tegra_clk_register_periph()
205 periph, clk_base, offset, CLK_SET_RATE_PARENT); in tegra_clk_register_periph_nodiv()
Dclk-tegra-periph.c669 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, in init_pllp()
/linux-4.1.27/drivers/clk/zynq/
Dclkc.c146 CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, in zynq_clk_register_fclk()
151 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, in zynq_clk_register_fclk()
202 CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); in zynq_clk_register_periph_clk()
205 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); in zynq_clk_register_periph_clk()
292 "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, in zynq_clk_setup()
326 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT | in zynq_clk_setup()
348 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, in zynq_clk_setup()
352 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, in zynq_clk_setup()
399 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, in zynq_clk_setup()
403 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in zynq_clk_setup()
[all …]
/linux-4.1.27/arch/arm/mach-imx/
Dclk-imx6q.c168 …_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
169 …_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
170 …_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
171 …_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
172 …_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
173 …_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
174 …_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
256 … = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x7… in imx6q_clocks_init()
257 …V] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x1… in imx6q_clocks_init()
258 … = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa… in imx6q_clocks_init()
[all …]
Dclk.h46 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate2()
54 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate2_shared()
85 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, in imx_clk_divider()
100 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate()
107 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate_dis()
132 CLK_SET_RATE_PARENT, mult, div); in imx_clk_fixed_factor()
Dclk-imx6sx.c178 …_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
179 …_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
180 …_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
181 …_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
182 …_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
183 …_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
184 …_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
256 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
258 CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); in imx6sx_clocks_init()
260 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
[all …]
Dclk-imx6sl.c223 …_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
224 …_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
225 …_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
226 …_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
227 …_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
228 …_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
229 …_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
265 …lk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x7… in imx6sl_clocks_init()
266 … clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x1… in imx6sl_clocks_init()
267 …lk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa… in imx6sl_clocks_init()
[all …]
Dclk-vf610.c181 …l1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
182 …l2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
183 …l3_bypass", PLL3_CTRL, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
184 …l4_bypass", PLL4_CTRL, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
185 …l5_bypass", PLL5_CTRL, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
186 …l6_bypass", PLL6_CTRL, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
187 …l7_bypass", PLL7_CTRL, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
Dclk-gate-exclusive.c79 init.flags = CLK_SET_RATE_PARENT; in imx_clk_gate_exclusive()
Dclk-imx51-imx53.c286 spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT); in mx5_clocks_common_init()
410 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT); in mx51_clocks_init()
501 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT); in mx53_clocks_init()
506 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT); in mx53_clocks_init()
514 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT); in mx53_clocks_init()
Dclk-fixup-div.c112 init.flags = CLK_SET_RATE_PARENT; in imx_clk_fixup_divider()
Dclk-busy.c104 init.flags = CLK_SET_RATE_PARENT; in imx_clk_busy_divider()
/linux-4.1.27/drivers/clk/mxs/
Dclk.h46 return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT, in mxs_clk_gate()
55 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mxs_clk_mux()
63 CLK_SET_RATE_PARENT, mult, div); in mxs_clk_fixed_factor()
Dclk-div.c90 init.flags = CLK_SET_RATE_PARENT; in mxs_clk_div()
Dclk-frac.c124 init.flags = CLK_SET_RATE_PARENT; in mxs_clk_frac()
/linux-4.1.27/drivers/clk/rockchip/
Dclk-rk3288.c285 DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
306 COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
309 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
314 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
538 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
541 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
548 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
551 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
556 COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
559 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
[all …]
Dclk-rockchip.c37 int clkflags = CLK_SET_RATE_PARENT; in rk2928_gate_clk_init()
Dclk-cpu.c259 init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0; in rockchip_clk_register_cpuclk()
Dclk.c255 flags |= CLK_SET_RATE_PARENT; in rockchip_clk_register_branches()
Dclk-pll.c429 init.flags = CLK_SET_RATE_PARENT; in rockchip_clk_register_pll()
Dclk-rk3188.c326 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
/linux-4.1.27/drivers/clk/ti/
Dfixed-factor.c53 flags |= CLK_SET_RATE_PARENT; in of_ti_fixed_factor_clk_setup()
Dmux.c174 flags |= CLK_SET_RATE_PARENT; in ti_clk_register_mux()
222 flags |= CLK_SET_RATE_PARENT; in of_mux_clk_setup()
Dgate.c152 flags |= CLK_SET_RATE_PARENT; in ti_clk_register_gate()
243 flags |= CLK_SET_RATE_PARENT; in _of_ti_gate_clk_setup()
Ddivider.c158 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { in ti_clk_divider_bestdiv()
416 flags |= CLK_SET_RATE_PARENT; in ti_clk_register_divider()
551 *flags |= CLK_SET_RATE_PARENT; in ti_clk_divider_populate()
/linux-4.1.27/drivers/clk/at91/
Dclk-usb.c216 CLK_SET_RATE_PARENT; in at91sam9x5_clk_register_usb()
244 init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT; in at91sam9n12_clk_register_usb()
359 init.flags = CLK_SET_RATE_PARENT; in at91rm9200_clk_register_usb()
Dclk-system.c122 init.flags = CLK_SET_RATE_PARENT; in at91_clk_register_system()
/linux-4.1.27/drivers/clk/
Dclk-asm9260.c306 gd->parent_name, gd->flags | CLK_SET_RATE_PARENT, in asm9260_acc_init()
315 dc->parent_name, CLK_SET_RATE_PARENT, in asm9260_acc_init()
Dclk-fixed-factor.c44 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { in clk_factor_round_rate()
Dclk-cdce706.c312 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { in cdce706_divider_round_rate()
562 .flags = CLK_SET_RATE_PARENT, in cdce706_register_dividers()
598 .flags = CLK_SET_RATE_PARENT, in cdce706_register_clkouts()
Dclk-si5351.c666 if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) { in si5351_msynth_round_rate()
1004 if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) { in si5351_clkout_round_rate()
1525 init.flags |= CLK_SET_RATE_PARENT; in si5351_i2c_probe()
1553 init.flags |= CLK_SET_RATE_PARENT; in si5351_i2c_probe()
Dclk-wm831x.c350 .flags = CLK_SET_RATE_PARENT,
Dclk.c814 if (core->flags & CLK_SET_RATE_PARENT) in clk_mux_determine_rate_flags()
830 if (core->flags & CLK_SET_RATE_PARENT) in clk_mux_determine_rate_flags()
1152 else if (clk->flags & CLK_SET_RATE_PARENT) in clk_core_round_rate_nolock()
1665 } else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) { in clk_calc_new_rates()
1694 if ((clk->flags & CLK_SET_RATE_PARENT) && parent && in clk_calc_new_rates()
Dclk-divider.c288 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { in clk_divider_bestdiv()
/linux-4.1.27/drivers/clk/pistachio/
Dclk.c68 CLK_SET_RATE_PARENT, in pistachio_clk_register_gate()
/linux-4.1.27/arch/powerpc/platforms/512x/
Dclock-commonclk.c232 clkflags = CLK_SET_RATE_PARENT; in mpc512x_clk_factor()
264 clkflags = CLK_SET_RATE_PARENT; in mpc512x_clk_gated()
276 clkflags = CLK_SET_RATE_PARENT; in mpc512x_clk_muxed()
/linux-4.1.27/drivers/clk/shmobile/
Dclk-mstp.c140 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; in cpg_mstp_clock_register()
/linux-4.1.27/drivers/clk/ux500/
Du8500_of_clk.c498 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); in u8500_of_clk_init()
503 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); in u8500_of_clk_init()
Du8500_clk.c486 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); in u8500_clk_init()
489 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); in u8500_clk_init()
Du8540_clk.c515 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); in u8540_clk_init()
520 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); in u8540_clk_init()
/linux-4.1.27/drivers/clk/sunxi/
Dclk-factors.c98 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT) in clk_factors_determine_rate()
Dclk-sunxi.c137 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT) in sun6i_ahb1_clk_determine_rate()
798 CLK_SET_RATE_PARENT, reg, in sunxi_mux_clk_setup()
1158 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; in sunxi_divs_clk_setup()
/linux-4.1.27/drivers/clk/st/
Dclkgen-mux.c656 data->clk_flags | CLK_SET_RATE_PARENT, in st_of_clkgen_mux_setup()
689 .clk_flags = CLK_SET_RATE_PARENT,
Dclk-flexgen.c111 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { in flexgen_round_rate()
/linux-4.1.27/sound/soc/samsung/
Di2s.c1191 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, in i2s_register_clock_provider()
1197 CLK_SET_RATE_PARENT, in i2s_register_clock_provider()
1207 p_names[0], CLK_SET_RATE_PARENT, in i2s_register_clock_provider()
/linux-4.1.27/include/linux/
Dclk-provider.h27 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ macro
/linux-4.1.27/arch/mips/alchemy/common/
Dclock.c766 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE; in alchemy_clk_init_fgens()
966 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE; in alchemy_clk_setup_imux()
/linux-4.1.27/arch/arm/mach-omap2/
Ddpll3xxx.c803 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { in omap3_clkoutx2_round_rate()
/linux-4.1.27/drivers/acpi/
Dacpi_lpss.c309 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, in register_device_clock()
/linux-4.1.27/drivers/clk/sirf/
Dclk-common.c502 .flags = CLK_SET_RATE_PARENT,
/linux-4.1.27/drivers/media/platform/exynos4-is/
Dmedia-dev.c1239 init.flags = CLK_SET_RATE_PARENT; in fimc_md_register_clk_provider()