146 			CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,  in zynq_clk_register_fclk()
151 			div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,  in zynq_clk_register_fclk()
202 			CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);  in zynq_clk_register_periph_clk()
205 				CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);  in zynq_clk_register_periph_clk()
292 			"cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,  in zynq_clk_setup()
326 			swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |  in zynq_clk_setup()
348 			CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,  in zynq_clk_setup()
352 			CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,  in zynq_clk_setup()
399 			CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,  in zynq_clk_setup()
403 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,  in zynq_clk_setup()
407 			"gem0_emio_mux", CLK_SET_RATE_PARENT,  in zynq_clk_setup()
424 			CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,  in zynq_clk_setup()
428 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,  in zynq_clk_setup()
432 			"gem1_emio_mux", CLK_SET_RATE_PARENT,  in zynq_clk_setup()
456 			CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,  in zynq_clk_setup()
460 			CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,  in zynq_clk_setup()
463 			CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,  in zynq_clk_setup()
466 			can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |  in zynq_clk_setup()
470 			can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |  in zynq_clk_setup()
474 			can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |  in zynq_clk_setup()
478 			can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |  in zynq_clk_setup()
499 			"dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,  in zynq_clk_setup()