Lines Matching refs:CLK_SET_RATE_PARENT

294 					CLK_SET_RATE_PARENT, 0, "mout_apll"),
409 			DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
423 			DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
426 			DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
430 			DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
433 			DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
442 			DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
445 			DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
449 			DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
482 			SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
484 			SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
486 			SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
488 			SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
490 			SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
493 			SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
495 			SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
497 			SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
502 			SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
505 			SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
507 			SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
509 			SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
511 			SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
513 			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
515 			SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
518 			SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
521 			SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
523 			SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
525 			SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
527 			SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
529 			SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
532 			SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
534 			SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
538 			SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
540 			SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
542 			SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
581 					CLK_SET_RATE_PARENT, 0),