Lines Matching refs:CLK_SET_RATE_PARENT

124 				CLK_SET_RATE_PARENT, 1, 2);  in mmp2_clk_init()
128 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
132 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
136 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
140 CLK_SET_RATE_PARENT, 1, 5); in mmp2_clk_init()
144 CLK_SET_RATE_PARENT, 1, 3); in mmp2_clk_init()
148 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
152 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
156 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
160 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
164 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
168 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
172 CLK_SET_RATE_PARENT, 1, 3); in mmp2_clk_init()
176 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
180 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
184 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
188 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
252 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
263 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
274 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
285 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
296 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
306 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
316 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
326 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
336 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
341 CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0, in mmp2_clk_init()
367 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
372 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0, in mmp2_clk_init()
390 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
395 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1, in mmp2_clk_init()
409 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
414 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in mmp2_clk_init()
427 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in mmp2_clk_init()
437 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
442 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, in mmp2_clk_init()
455 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, in mmp2_clk_init()