Lines Matching refs:CLK_SET_RATE_PARENT

954 					CLK_SET_RATE_PARENT, 1, 2);  in tegra114_fixed_clk_init()
959 					CLK_SET_RATE_PARENT, 1, 4);  in tegra114_fixed_clk_init()
1063 				CLK_SET_RATE_PARENT, 0, NULL);  in tegra114_pll_init()
1088 				CLK_SET_RATE_PARENT, 0, NULL);  in tegra114_pll_init()
1093 					CLK_SET_RATE_PARENT, 1, 1);  in tegra114_pll_init()
1108 				CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,  in tegra114_pll_init()
1114 					CLK_SET_RATE_PARENT, 1, 8);  in tegra114_pll_init()
1119 					CLK_SET_RATE_PARENT, 1, 10);  in tegra114_pll_init()
1124 					CLK_SET_RATE_PARENT, 1, 40);  in tegra114_pll_init()
1134 					CLK_SET_RATE_PARENT, 1, 2);  in tegra114_pll_init()
1144 					CLK_SET_RATE_PARENT, 1, 2);  in tegra114_pll_init()