Lines Matching refs:CLK_SET_RATE_PARENT

890 			CLK_SET_RATE_PARENT, 0),
892 			CLK_SET_RATE_PARENT, 0),
951 		GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
953 		GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
955 		GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
957 		GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
959 		GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
961 		GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
963 		GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
965 		GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
967 		GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
969 		GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
971 		GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
973 		GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
975 		GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
978 		GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
980 		GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
982 		GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
984 		GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
986 		GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
988 		GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
990 		GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
994 			GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
996 			GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
1000 			GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
1002 			GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
1006 		GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1008 		GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1025 			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1182 			GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1184 			GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1186 			GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1188 			GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1190 			GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1192 			GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1194 			GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),