Lines Matching refs:CLK_SET_RATE_PARENT
365 CLK_SET_RATE_PARENT, 0),
372 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
375 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
380 CLK_SET_RATE_PARENT, 0),
385 CLK_SET_RATE_PARENT, 0),
388 CLK_SET_RATE_PARENT, 0),
397 CLK_SET_RATE_PARENT, 0),
400 CLK_SET_RATE_PARENT, 0),
500 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
502 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
504 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
506 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
510 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
514 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
518 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
520 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
522 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
526 GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
528 GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
530 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
532 GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
537 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
539 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
541 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
543 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
547 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
549 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
551 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
553 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
555 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
557 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),