Searched refs:intr (Results 1 - 200 of 674) sorted by relevance

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/linux-4.1.27/drivers/net/ethernet/cisco/enic/
H A Dvnic_intr.c29 void vnic_intr_free(struct vnic_intr *intr) vnic_intr_free() argument
31 intr->ctrl = NULL; vnic_intr_free()
34 int vnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr, vnic_intr_alloc() argument
37 intr->index = index; vnic_intr_alloc()
38 intr->vdev = vdev; vnic_intr_alloc()
40 intr->ctrl = vnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index); vnic_intr_alloc()
41 if (!intr->ctrl) { vnic_intr_alloc()
49 void vnic_intr_init(struct vnic_intr *intr, u32 coalescing_timer, vnic_intr_init() argument
52 vnic_intr_coalescing_timer_set(intr, coalescing_timer); vnic_intr_init()
53 iowrite32(coalescing_type, &intr->ctrl->coalescing_type); vnic_intr_init()
54 iowrite32(mask_on_assertion, &intr->ctrl->mask_on_assertion); vnic_intr_init()
55 iowrite32(0, &intr->ctrl->int_credits); vnic_intr_init()
58 void vnic_intr_coalescing_timer_set(struct vnic_intr *intr, vnic_intr_coalescing_timer_set() argument
61 iowrite32(vnic_dev_intr_coal_timer_usec_to_hw(intr->vdev, vnic_intr_coalescing_timer_set()
62 coalescing_timer), &intr->ctrl->coalescing_timer); vnic_intr_coalescing_timer_set()
65 void vnic_intr_clean(struct vnic_intr *intr) vnic_intr_clean() argument
67 iowrite32(0, &intr->ctrl->int_credits); vnic_intr_clean()
H A Dvnic_intr.h54 static inline void vnic_intr_unmask(struct vnic_intr *intr) vnic_intr_unmask() argument
56 iowrite32(0, &intr->ctrl->mask); vnic_intr_unmask()
59 static inline void vnic_intr_mask(struct vnic_intr *intr) vnic_intr_mask() argument
61 iowrite32(1, &intr->ctrl->mask); vnic_intr_mask()
64 static inline int vnic_intr_masked(struct vnic_intr *intr) vnic_intr_masked() argument
66 return ioread32(&intr->ctrl->mask); vnic_intr_masked()
69 static inline void vnic_intr_return_credits(struct vnic_intr *intr, vnic_intr_return_credits() argument
79 iowrite32(int_credit_return, &intr->ctrl->int_credit_return); vnic_intr_return_credits()
82 static inline unsigned int vnic_intr_credits(struct vnic_intr *intr) vnic_intr_credits() argument
84 return ioread32(&intr->ctrl->int_credits); vnic_intr_credits()
87 static inline void vnic_intr_return_all_credits(struct vnic_intr *intr) vnic_intr_return_all_credits() argument
89 unsigned int credits = vnic_intr_credits(intr); vnic_intr_return_all_credits()
93 vnic_intr_return_credits(intr, credits, unmask, reset_timer); vnic_intr_return_all_credits()
102 void vnic_intr_free(struct vnic_intr *intr);
103 int vnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr,
105 void vnic_intr_init(struct vnic_intr *intr, u32 coalescing_timer,
107 void vnic_intr_coalescing_timer_set(struct vnic_intr *intr,
109 void vnic_intr_clean(struct vnic_intr *intr);
H A Denic_main.c266 vnic_intr_mask(&enic->intr[io_intr]); enic_isr_legacy()
270 vnic_intr_unmask(&enic->intr[io_intr]); enic_isr_legacy()
276 vnic_intr_return_all_credits(&enic->intr[notify_intr]); enic_isr_legacy()
280 vnic_intr_return_all_credits(&enic->intr[err_intr]); enic_isr_legacy()
290 vnic_intr_unmask(&enic->intr[io_intr]); enic_isr_legacy()
332 unsigned int intr = enic_msix_err_intr(enic); enic_isr_msix_err() local
334 vnic_intr_return_all_credits(&enic->intr[intr]); enic_isr_msix_err()
347 unsigned int intr = enic_msix_notify_intr(enic); enic_isr_msix_notify() local
350 vnic_intr_return_all_credits(&enic->intr[intr]); enic_isr_msix_notify()
1158 unsigned int intr = enic_legacy_io_intr(); enic_poll() local
1169 vnic_intr_return_credits(&enic->intr[intr], enic_poll()
1171 0 /* dont unmask intr */, enic_poll()
1172 0 /* dont reset intr timer */); enic_poll()
1180 /* Accumulate intr event credits for this polling enic_poll()
1181 * cycle. An intr event is the completion of a enic_poll()
1188 vnic_intr_return_credits(&enic->intr[intr], enic_poll()
1190 0 /* don't unmask intr */, enic_poll()
1191 0 /* don't reset intr timer */); enic_poll()
1209 vnic_intr_unmask(&enic->intr[intr]); enic_poll()
1218 unsigned int intr = enic_msix_rq_intr(enic, rq->index); enic_set_int_moderation() local
1223 vnic_intr_coalescing_timer_set(&enic->intr[intr], timer); enic_set_int_moderation()
1319 unsigned int intr = enic_msix_rq_intr(enic, rq); enic_busy_poll() local
1329 vnic_intr_return_credits(&enic->intr[intr], enic_busy_poll()
1347 unsigned int intr; enic_poll_msix_wq() local
1354 intr = enic_msix_wq_intr(enic, wq_irq); enic_poll_msix_wq()
1358 vnic_intr_return_credits(&enic->intr[intr], wq_work_done, enic_poll_msix_wq()
1359 0 /* don't unmask intr */, enic_poll_msix_wq()
1360 1 /* reset intr timer */); enic_poll_msix_wq()
1363 vnic_intr_unmask(&enic->intr[intr]); enic_poll_msix_wq()
1376 unsigned int intr = enic_msix_rq_intr(enic, rq); enic_poll_msix_rq() local
1390 /* Return intr event credits for this polling enic_poll_msix_rq()
1391 * cycle. An intr event is the completion of a enic_poll_msix_rq()
1396 vnic_intr_return_credits(&enic->intr[intr], enic_poll_msix_rq()
1398 0 /* don't unmask intr */, enic_poll_msix_rq()
1399 0 /* don't reset intr timer */); enic_poll_msix_rq()
1411 * the intr coalescing timer value based on enic_poll_msix_rq()
1427 vnic_intr_unmask(&enic->intr[intr]); enic_poll_msix_rq()
1470 unsigned int i, intr; enic_request_intr() local
1491 intr = enic_msix_rq_intr(enic, i); enic_request_intr()
1492 snprintf(enic->msix[intr].devname, enic_request_intr()
1493 sizeof(enic->msix[intr].devname), enic_request_intr()
1495 enic->msix[intr].isr = enic_isr_msix; enic_request_intr()
1496 enic->msix[intr].devid = &enic->napi[i]; enic_request_intr()
1502 intr = enic_msix_wq_intr(enic, i); enic_request_intr()
1503 snprintf(enic->msix[intr].devname, enic_request_intr()
1504 sizeof(enic->msix[intr].devname), enic_request_intr()
1506 enic->msix[intr].isr = enic_isr_msix; enic_request_intr()
1507 enic->msix[intr].devid = &enic->napi[wq]; enic_request_intr()
1510 intr = enic_msix_err_intr(enic); enic_request_intr()
1511 snprintf(enic->msix[intr].devname, enic_request_intr()
1512 sizeof(enic->msix[intr].devname), enic_request_intr()
1514 enic->msix[intr].isr = enic_isr_msix_err; enic_request_intr()
1515 enic->msix[intr].devid = enic; enic_request_intr()
1517 intr = enic_msix_notify_intr(enic); enic_request_intr()
1518 snprintf(enic->msix[intr].devname, enic_request_intr()
1519 sizeof(enic->msix[intr].devname), enic_request_intr()
1521 enic->msix[intr].isr = enic_isr_msix_notify; enic_request_intr()
1522 enic->msix[intr].devid = enic; enic_request_intr()
1572 /* If intr mode is not MSIX, do not do adaptive coalescing */ enic_set_rx_coal_setting()
1617 err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */); enic_dev_notify_set()
1632 /* Using intr for notification for INTx/MSI-X */ enic_notify_timer_start()
1689 vnic_intr_unmask(&enic->intr[i]); enic_open()
1714 vnic_intr_mask(&enic->intr[i]); enic_stop()
1715 (void)vnic_intr_masked(&enic->intr[i]); /* flush write */ enic_stop()
1763 vnic_intr_clean(&enic->intr[i]); enic_stop()
1813 vnic_intr_mask(&enic->intr[0]); enic_change_mtu_work()
1823 vnic_intr_clean(&enic->intr[0]); enic_change_mtu_work()
1838 vnic_intr_unmask(&enic->intr[0]); enic_change_mtu_work()
1851 unsigned int i, intr; enic_poll_controller() local
1856 intr = enic_msix_rq_intr(enic, i); enic_poll_controller()
1857 enic_isr_msix(enic->msix_entry[intr].vector, enic_poll_controller()
1862 intr = enic_msix_wq_intr(enic, i); enic_poll_controller()
1863 enic_isr_msix(enic->msix_entry[intr].vector, enic_poll_controller()
2329 dev_err(dev, "Failed to set intr mode based on resource " enic_dev_init()
H A Denic_ethtool.c98 int intr; enic_intr_coal_set_rx() local
101 intr = enic_msix_rq_intr(enic, i); enic_intr_coal_set_rx()
102 vnic_intr_coalescing_timer_set(&enic->intr[intr], timer); enic_intr_coal_set_rx()
246 unsigned int i, intr; enic_set_coalesce() local
269 intr = enic_legacy_io_intr(); enic_set_coalesce()
270 vnic_intr_coalescing_timer_set(&enic->intr[intr], enic_set_coalesce()
281 vnic_intr_coalescing_timer_set(&enic->intr[0], enic_set_coalesce()
291 intr = enic_msix_wq_intr(enic, i); enic_set_coalesce()
292 vnic_intr_coalescing_timer_set(&enic->intr[intr], enic_set_coalesce()
H A Denic_res.c102 "tso/lro %s/%s rss %s intr mode %s type %s timer %d usec " enic_get_vnic_config()
193 vnic_intr_free(&enic->intr[i]); enic_free_vnic_resources()
205 "vNIC resources avail: wq %d rq %d cq %d intr %d\n", enic_get_res_counts()
305 vnic_intr_init(&enic->intr[i], enic_init_vnic_resources()
321 "wq %d rq %d cq %d intr %d intr mode %s\n", enic_alloc_vnic_resources()
362 err = vnic_intr_alloc(enic->vdev, &enic->intr[i], i); enic_alloc_vnic_resources()
H A Dvnic_resource.h46 RES_TYPE_INTR_PBA_LEGACY, /* Legacy intr status */
/linux-4.1.27/drivers/scsi/fnic/
H A Dvnic_intr.c27 void vnic_intr_free(struct vnic_intr *intr) vnic_intr_free() argument
29 intr->ctrl = NULL; vnic_intr_free()
32 int vnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr, vnic_intr_alloc() argument
35 intr->index = index; vnic_intr_alloc()
36 intr->vdev = vdev; vnic_intr_alloc()
38 intr->ctrl = vnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index); vnic_intr_alloc()
39 if (!intr->ctrl) { vnic_intr_alloc()
48 void vnic_intr_init(struct vnic_intr *intr, unsigned int coalescing_timer, vnic_intr_init() argument
51 iowrite32(coalescing_timer, &intr->ctrl->coalescing_timer); vnic_intr_init()
52 iowrite32(coalescing_type, &intr->ctrl->coalescing_type); vnic_intr_init()
53 iowrite32(mask_on_assertion, &intr->ctrl->mask_on_assertion); vnic_intr_init()
54 iowrite32(0, &intr->ctrl->int_credits); vnic_intr_init()
57 void vnic_intr_clean(struct vnic_intr *intr) vnic_intr_clean() argument
59 iowrite32(0, &intr->ctrl->int_credits); vnic_intr_clean()
H A Dvnic_intr.h68 static inline void vnic_intr_unmask(struct vnic_intr *intr) vnic_intr_unmask() argument
70 iowrite32(0, &intr->ctrl->mask); vnic_intr_unmask()
73 static inline void vnic_intr_mask(struct vnic_intr *intr) vnic_intr_mask() argument
75 iowrite32(1, &intr->ctrl->mask); vnic_intr_mask()
78 static inline void vnic_intr_return_credits(struct vnic_intr *intr, vnic_intr_return_credits() argument
88 iowrite32(int_credit_return, &intr->ctrl->int_credit_return); vnic_intr_return_credits()
91 static inline unsigned int vnic_intr_credits(struct vnic_intr *intr) vnic_intr_credits() argument
93 return ioread32(&intr->ctrl->int_credits); vnic_intr_credits()
96 static inline void vnic_intr_return_all_credits(struct vnic_intr *intr) vnic_intr_return_all_credits() argument
98 unsigned int credits = vnic_intr_credits(intr); vnic_intr_return_all_credits()
102 vnic_intr_return_credits(intr, credits, unmask, reset_timer); vnic_intr_return_all_credits()
111 void vnic_intr_free(struct vnic_intr *intr);
112 int vnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr,
114 void vnic_intr_init(struct vnic_intr *intr, unsigned int coalescing_timer,
116 void vnic_intr_clean(struct vnic_intr *intr);
H A Dfnic_isr.c44 vnic_intr_return_all_credits(&fnic->intr[FNIC_INTX_NOTIFY]); fnic_isr_legacy()
49 vnic_intr_return_all_credits(&fnic->intr[FNIC_INTX_ERR]); fnic_isr_legacy()
58 vnic_intr_return_credits(&fnic->intr[FNIC_INTX_WQ_RQ_COPYWQ], fnic_isr_legacy()
60 1 /* unmask intr */, fnic_isr_legacy()
61 1 /* reset intr timer */); fnic_isr_legacy()
79 vnic_intr_return_credits(&fnic->intr[0], fnic_isr_msi()
81 1 /* unmask intr */, fnic_isr_msi()
82 1 /* reset intr timer */); fnic_isr_msi()
96 vnic_intr_return_credits(&fnic->intr[FNIC_MSIX_RQ], fnic_isr_msix_rq()
98 1 /* unmask intr */, fnic_isr_msix_rq()
99 1 /* reset intr timer */); fnic_isr_msix_rq()
113 vnic_intr_return_credits(&fnic->intr[FNIC_MSIX_WQ], fnic_isr_msix_wq()
115 1 /* unmask intr */, fnic_isr_msix_wq()
116 1 /* reset intr timer */); fnic_isr_msix_wq()
129 vnic_intr_return_credits(&fnic->intr[FNIC_MSIX_WQ_COPY], fnic_isr_msix_wq_copy()
131 1 /* unmask intr */, fnic_isr_msix_wq_copy()
132 1 /* reset intr timer */); fnic_isr_msix_wq_copy()
143 vnic_intr_return_all_credits(&fnic->intr[FNIC_MSIX_ERR_NOTIFY]); fnic_isr_msix_err_notify()
H A Dvnic_resource.h39 RES_TYPE_INTR_PBA_LEGACY, /* Legacy intr status */
H A Dfnic_res.c159 "vNIC mtu %d intr timer %d\n", fnic_get_vnic_config()
227 vnic_intr_free(&fnic->intr[i]); fnic_free_vnic_resources()
250 "wq %d cp_wq %d raw_wq %d rq %d cq %d intr %d\n", fnic_alloc_vnic_resources()
316 err = vnic_intr_alloc(fnic->vdev, &fnic->intr[i], i); fnic_alloc_vnic_resources()
420 vnic_intr_init(&fnic->intr[i], fnic_alloc_vnic_resources()
H A Dvnic_dev.c526 int vnic_dev_notify_set(struct vnic_dev *vdev, u16 intr) vnic_dev_notify_set() argument
540 a1 = ((u64)intr << 32) & 0x0000ffff00000000ULL; vnic_dev_notify_set()
552 a1 = 0x0000ffff00000000ULL; /* intr num = -1 to unreg for intr */ vnic_dev_notify_unset()
/linux-4.1.27/drivers/gpu/host1x/
H A DMakefile5 intr.o \
H A Dintr.c27 #include "intr.h"
175 spin_lock(&syncpt->intr.lock); process_wait_list()
177 remove_completed_waiters(&syncpt->intr.wait_head, threshold, process_wait_list()
180 empty = list_empty(&syncpt->intr.wait_head); process_wait_list()
184 reset_threshold_interrupt(host, &syncpt->intr.wait_head, process_wait_list()
187 spin_unlock(&syncpt->intr.lock); process_wait_list()
204 container_of(syncpt_intr, struct host1x_syncpt, intr); syncpt_thresh_work()
237 spin_lock(&syncpt->intr.lock); host1x_intr_add_action()
239 queue_was_empty = list_empty(&syncpt->intr.wait_head); host1x_intr_add_action()
241 if (add_waiter_to_queue(waiter, &syncpt->intr.wait_head)) { host1x_intr_add_action()
250 spin_unlock(&syncpt->intr.lock); host1x_intr_add_action()
287 spin_lock_init(&syncpt->intr.lock); host1x_intr_init()
288 INIT_LIST_HEAD(&syncpt->intr.wait_head); host1x_intr_init()
289 snprintf(syncpt->intr.thresh_irq_name, host1x_intr_init()
290 sizeof(syncpt->intr.thresh_irq_name), host1x_intr_init()
334 &syncpt[id].intr.wait_head, list) { host1x_intr_stop()
342 if (!list_empty(&syncpt[id].intr.wait_head)) { host1x_intr_stop()
345 pr_warn("%s cannot stop syncpt intr id=%d\n", host1x_intr_stop()
H A Dsyncpt.h27 #include "intr.h"
51 struct host1x_syncpt_intr intr; member in struct:host1x_syncpt
/linux-4.1.27/arch/m68k/include/asm/
H A Dmcfintc.h30 #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
31 #define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
32 #define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
33 #define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
34 #define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
35 #define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
36 #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
37 #define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
38 #define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
40 #define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
41 #define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
42 #define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
43 #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
H A Dm54xxpci.h83 #define PCIGSCR_PEE 0x00002000 /* Parity error intr enable */
84 #define PCIGSCR_SEE 0x00001000 /* System error intr enable */
H A Dmac_iop.h27 #define IOP_INT0 0x10 /* intr priority from IOP to host */
28 #define IOP_INT1 0x20 /* intr priority from IOP to host */
H A Dm525xsim.h36 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
197 #define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
198 #define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
199 #define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
/linux-4.1.27/arch/mn10300/proc-mn103e010/include/proc/
H A Dintctl-regs.h8 /* intr acceptance group reg */
24 /* external pin intr spec reg */
H A Ddmactl-regs.h83 #define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
84 #define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
85 #define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
86 #define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
/linux-4.1.27/arch/mn10300/proc-mn2ws0050/include/proc/
H A Dintctl-regs.h8 /* intr acceptance group reg */
24 /* external pin intr spec reg */
H A Ddmactl-regs.h84 #define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
85 #define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
86 #define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
87 #define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
/linux-4.1.27/arch/x86/platform/intel-mid/device_libs/
H A Dplatform_lis331.c21 int intr = get_gpio_by_name("accel_int"); lis331dl_platform_data() local
24 if (intr < 0) lis331dl_platform_data()
29 i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET; lis331dl_platform_data()
H A Dplatform_mpu3050.c20 int intr = get_gpio_by_name("mpu3050_int"); mpu3050_platform_data() local
22 if (intr < 0) mpu3050_platform_data()
25 i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET; mpu3050_platform_data()
H A Dplatform_tca6416.c26 int gpio_base, intr; tca6416_platform_data() local
35 intr = get_gpio_by_name(intr_pin_name); tca6416_platform_data()
40 if (intr >= 0) { tca6416_platform_data()
41 i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET; tca6416_platform_data()
H A Dplatform_emc1403.c22 int intr = get_gpio_by_name("thermal_int"); emc1403_platform_data() local
25 if (intr < 0) emc1403_platform_data()
30 i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET; emc1403_platform_data()
H A Dplatform_max7315.c27 int gpio_base, intr; max7315_platform_data() local
49 intr = get_gpio_by_name(intr_pin_name); max7315_platform_data()
54 if (intr != -1) { max7315_platform_data()
55 i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET; max7315_platform_data()
/linux-4.1.27/arch/mips/kernel/
H A Dsmp-gic.c24 unsigned int intr; gic_send_ipi_single() local
34 intr = plat_ipi_call_int_xlate(cpu); gic_send_ipi_single()
38 intr = plat_ipi_resched_int_xlate(cpu); gic_send_ipi_single()
45 gic_send_ipi(intr); gic_send_ipi_single()
/linux-4.1.27/arch/mn10300/include/asm/
H A Dtermios.h6 /* intr=^C quit=^| erase=del kill=^U
H A Dtimer-regs.h106 #define TM0ICR GxICR(TM0IRQ) /* timer 0 uflow intr ctrl reg */
107 #define TM1ICR GxICR(TM1IRQ) /* timer 1 uflow intr ctrl reg */
108 #define TM2ICR GxICR(TM2IRQ) /* timer 2 uflow intr ctrl reg */
109 #define TM3ICR GxICR(TM3IRQ) /* timer 3 uflow intr ctrl reg */
325 #define TM4ICR GxICR(TM4IRQ) /* timer 4 uflow intr ctrl reg */
326 #define TM5ICR GxICR(TM5IRQ) /* timer 5 uflow intr ctrl reg */
327 #define TM7ICR GxICR(TM7IRQ) /* timer 7 uflow intr ctrl reg */
328 #define TM8ICR GxICR(TM8IRQ) /* timer 8 uflow intr ctrl reg */
329 #define TM9ICR GxICR(TM9IRQ) /* timer 9 uflow intr ctrl reg */
330 #define TM10ICR GxICR(TM10IRQ) /* timer 10 uflow intr ctrl reg */
331 #define TM11ICR GxICR(TM11IRQ) /* timer 11 uflow intr ctrl reg */
333 #define TM12ICR GxICR(TM12IRQ) /* timer 12 uflow intr ctrl reg */
334 #define TM13ICR GxICR(TM13IRQ) /* timer 13 uflow intr ctrl reg */
335 #define TM14ICR GxICR(TM14IRQ) /* timer 14 uflow intr ctrl reg */
336 #define TM15ICR GxICR(TM15IRQ) /* timer 15 uflow intr ctrl reg */
418 #define TM6ICR GxICR(TM6IRQ) /* timer 6 uflow intr ctrl reg */
419 #define TM6AICR GxICR(TM6AIRQ) /* timer 6A intr control reg */
420 #define TM6BICR GxICR(TM6BIRQ) /* timer 6B intr control reg */
446 #define TMTICR GxICR(TMTIRQ) /* OS Tick timer uflow intr ctrl reg */
447 #define TMSICR GxICR(TMSIRQ) /* Timestamp timer uflow intr ctrl reg */
H A Dserial-regs.h92 #define SC0RXICR GxICR(SC0RXIRQ) /* serial 0 receive intr ctrl reg */
93 #define SC0TXICR GxICR(SC0TXIRQ) /* serial 0 transmit intr ctrl reg */
105 #define SC1RXICR GxICR(SC1RXIRQ) /* serial 1 receive intr ctrl reg */
106 #define SC1TXICR GxICR(SC1TXIRQ) /* serial 1 transmit intr ctrl reg */
185 #define SC2RXICR GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */
186 #define SC2TXICR GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */
/linux-4.1.27/arch/frv/include/asm/
H A Dtermios.h6 /* intr=^C quit=^| erase=del kill=^U
/linux-4.1.27/arch/ia64/hp/sim/
H A Dhpsim_irq.c50 static void hpsim_connect_irq(int intr, int irq) hpsim_connect_irq() argument
52 ia64_ssc(intr, irq, 0, 0, SSC_CONNECT_INTERRUPT); hpsim_connect_irq()
55 int hpsim_get_irq(int intr) hpsim_get_irq() argument
62 hpsim_connect_irq(intr, irq); hpsim_get_irq()
/linux-4.1.27/arch/ia64/include/asm/
H A Dhpsim.h13 extern int hpsim_get_irq(int intr);
H A Dtermios.h13 /* intr=^C quit=^\ erase=del kill=^U
/linux-4.1.27/drivers/irqchip/
H A Dirq-mips-gic.c66 static inline void gic_reset_mask(unsigned int intr) gic_reset_mask() argument
68 gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr), gic_reset_mask()
69 1 << GIC_INTR_BIT(intr)); gic_reset_mask()
72 static inline void gic_set_mask(unsigned int intr) gic_set_mask() argument
74 gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr), gic_set_mask()
75 1 << GIC_INTR_BIT(intr)); gic_set_mask()
78 static inline void gic_set_polarity(unsigned int intr, unsigned int pol) gic_set_polarity() argument
81 GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), gic_set_polarity()
82 pol << GIC_INTR_BIT(intr)); gic_set_polarity()
85 static inline void gic_set_trigger(unsigned int intr, unsigned int trig) gic_set_trigger() argument
88 GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), gic_set_trigger()
89 trig << GIC_INTR_BIT(intr)); gic_set_trigger()
92 static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual) gic_set_dual_edge() argument
94 gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr), gic_set_dual_edge()
95 1 << GIC_INTR_BIT(intr), gic_set_dual_edge()
96 dual << GIC_INTR_BIT(intr)); gic_set_dual_edge()
99 static inline void gic_map_to_pin(unsigned int intr, unsigned int pin) gic_map_to_pin() argument
102 GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin); gic_map_to_pin()
105 static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) gic_map_to_vpe() argument
108 GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe), gic_map_to_vpe()
192 static bool gic_local_irq_is_routable(int intr) gic_local_irq_is_routable() argument
201 switch (intr) { gic_local_irq_is_routable()
226 void gic_send_ipi(unsigned int intr) gic_send_ipi() argument
228 gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr)); gic_send_ipi()
276 unsigned int i, intr, virq; gic_handle_shared_int() local
298 intr = find_first_bit(pending, gic_shared_intrs); gic_handle_shared_int()
299 while (intr != gic_shared_intrs) { gic_handle_shared_int()
301 GIC_SHARED_TO_HWIRQ(intr)); gic_handle_shared_int()
308 bitmap_clear(pending, intr, 1); gic_handle_shared_int()
309 intr = find_first_bit(pending, gic_shared_intrs); gic_handle_shared_int()
440 unsigned int intr, virq; gic_handle_local_int() local
447 intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); gic_handle_local_int()
448 while (intr != GIC_NUM_LOCAL_INTRS) { gic_handle_local_int()
450 GIC_LOCAL_TO_HWIRQ(intr)); gic_handle_local_int()
457 bitmap_clear(&pending, intr, 1); gic_handle_local_int()
458 intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); gic_handle_local_int()
464 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); gic_mask_local_irq() local
466 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr); gic_mask_local_irq() local
471 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); gic_unmask_local_irq() local
473 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr); gic_unmask_local_irq() local
484 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); gic_mask_local_irq_all_vpes() local
491 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr); gic_mask_local_irq_all_vpes() local
498 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); gic_unmask_local_irq_all_vpes() local
505 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr); gic_unmask_local_irq_all_vpes() local
568 static __init void gic_ipi_init_one(unsigned int intr, int cpu, gic_ipi_init_one() argument
572 GIC_SHARED_TO_HWIRQ(intr)); gic_ipi_init_one()
575 gic_map_to_vpe(intr, cpu); gic_ipi_init_one()
577 clear_bit(intr, pcpu_masks[i].pcpu_mask); gic_ipi_init_one()
578 set_bit(intr, pcpu_masks[cpu].pcpu_mask); gic_ipi_init_one()
633 int intr = GIC_HWIRQ_TO_LOCAL(hw); gic_local_irq_domain_map() local
638 if (!gic_local_irq_is_routable(intr)) gic_local_irq_domain_map()
646 switch (intr) { gic_local_irq_domain_map()
668 switch (intr) { gic_local_irq_domain_map()
693 pr_err("Invalid local IRQ %d\n", intr); gic_local_irq_domain_map()
706 int intr = GIC_HWIRQ_TO_SHARED(hw); gic_shared_irq_domain_map() local
713 gic_map_to_pin(intr, gic_cpu_pin); gic_shared_irq_domain_map()
715 gic_map_to_vpe(intr, 0); gic_shared_irq_domain_map()
716 set_bit(intr, pcpu_masks[0].pcpu_mask); gic_shared_irq_domain_map()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
H A Dbase.c40 u32 intr = nv_rd32(pmc, 0x000100); nvkm_mc_intr_mask() local
41 if (intr == 0xffffffff) /* likely fallen off the bus */ nvkm_mc_intr_mask()
42 intr = 0x00000000; nvkm_mc_intr_mask()
43 return intr; nvkm_mc_intr_mask()
51 const struct nvkm_mc_intr *map = oclass->intr; nvkm_mc_intr()
53 u32 intr; nvkm_mc_intr() local
57 intr = nvkm_mc_intr_mask(pmc); nvkm_mc_intr()
61 if (intr) { nvkm_mc_intr()
62 u32 stat = intr = nvkm_mc_intr_mask(pmc); nvkm_mc_intr()
64 if (intr & map->stat) { nvkm_mc_intr()
66 if (unit && unit->intr) nvkm_mc_intr()
67 unit->intr(unit); nvkm_mc_intr()
74 nv_error(pmc, "unknown intr 0x%08x\n", stat); nvkm_mc_intr()
78 return intr ? IRQ_HANDLED : IRQ_NONE; nvkm_mc_intr()
H A Dpriv.h30 const struct nvkm_mc_intr *intr; member in struct:nvkm_mc_oclass
H A Dg94.c35 .intr = nv50_mc_intr,
H A Dg98.c56 .intr = g98_mc_intr,
H A Dgf106.c35 .intr = gf100_mc_intr,
H A Dgk20a.c35 .intr = gf100_mc_intr,
H A Dnv40.c42 .intr = nv04_mc_intr,
H A Dnv44.c51 .intr = nv04_mc_intr,
H A Dnv4c.c35 .intr = nv04_mc_intr,
H A Dgf100.c73 .intr = gf100_mc_intr,
H A Dnv04.c77 .intr = nv04_mc_intr,
H A Dnv50.c70 .intr = nv50_mc_intr,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dgf100.c41 u32 intr = nv_rd32(priv, 0x000100); gf100_fb_intr() local
42 if (intr & 0x08000000) { gf100_fb_intr()
43 nv_debug(priv, "PFFB intr\n"); gf100_fb_intr()
44 intr &= ~0x08000000; gf100_fb_intr()
46 if (intr & 0x00002000) { gf100_fb_intr()
47 nv_debug(priv, "PBFB intr\n"); gf100_fb_intr()
48 intr &= ~0x00002000; gf100_fb_intr()
107 nv_subdev(priv)->intr = gf100_fb_intr; gf100_fb_ctor()
/linux-4.1.27/drivers/net/wireless/zd1211rw/
H A Dzd_usb.c373 struct zd_usb_interrupt *intr = &usb->intr; handle_regs_int_override() local
375 spin_lock(&intr->lock); handle_regs_int_override()
376 if (atomic_read(&intr->read_regs_enabled)) { handle_regs_int_override()
377 atomic_set(&intr->read_regs_enabled, 0); handle_regs_int_override()
378 intr->read_regs_int_overridden = 1; handle_regs_int_override()
379 complete(&intr->read_regs.completion); handle_regs_int_override()
381 spin_unlock(&intr->lock); handle_regs_int_override()
387 struct zd_usb_interrupt *intr = &usb->intr; handle_regs_int() local
392 spin_lock(&intr->lock); handle_regs_int()
402 } else if (atomic_read(&intr->read_regs_enabled)) { handle_regs_int()
404 intr->read_regs.length = urb->actual_length; handle_regs_int()
405 if (len > sizeof(intr->read_regs.buffer)) handle_regs_int()
406 len = sizeof(intr->read_regs.buffer); handle_regs_int()
408 memcpy(intr->read_regs.buffer, urb->transfer_buffer, len); handle_regs_int()
416 if (!check_read_regs(usb, intr->read_regs.req, handle_regs_int()
417 intr->read_regs.req_count)) handle_regs_int()
420 atomic_set(&intr->read_regs_enabled, 0); handle_regs_int()
421 intr->read_regs_int_overridden = 0; handle_regs_int()
422 complete(&intr->read_regs.completion); handle_regs_int()
428 spin_unlock(&intr->lock); handle_regs_int()
431 if (int_num == CR_INTERRUPT && atomic_read(&intr->read_regs_enabled)) handle_regs_int()
440 struct zd_usb_interrupt *intr; int_urb_complete() local
473 intr = &usb->intr; int_urb_complete()
474 if (hdr->id != USB_INT_ID_REGS && atomic_read(&intr->read_regs_enabled)) int_urb_complete()
495 /* TODO: add worker to reset intr->urb */ int_urb_complete()
516 struct zd_usb_interrupt *intr = &usb->intr; usb_int_enabled() local
519 spin_lock_irqsave(&intr->lock, flags); usb_int_enabled()
520 urb = intr->urb; usb_int_enabled()
521 spin_unlock_irqrestore(&intr->lock, flags); usb_int_enabled()
529 struct zd_usb_interrupt *intr = &usb->intr; zd_usb_enable_int() local
541 spin_lock_irq(&intr->lock); zd_usb_enable_int()
542 if (intr->urb) { zd_usb_enable_int()
543 spin_unlock_irq(&intr->lock); zd_usb_enable_int()
547 intr->urb = urb; zd_usb_enable_int()
548 spin_unlock_irq(&intr->lock); zd_usb_enable_int()
551 intr->buffer = usb_alloc_coherent(udev, USB_MAX_EP_INT_BUFFER, zd_usb_enable_int()
552 GFP_KERNEL, &intr->buffer_dma); zd_usb_enable_int()
553 if (!intr->buffer) { zd_usb_enable_int()
560 intr->buffer, USB_MAX_EP_INT_BUFFER, zd_usb_enable_int()
562 intr->interval); zd_usb_enable_int()
563 urb->transfer_dma = intr->buffer_dma; zd_usb_enable_int()
566 dev_dbg_f(zd_usb_dev(usb), "submit urb %p\n", intr->urb); zd_usb_enable_int()
577 intr->buffer, intr->buffer_dma); zd_usb_enable_int()
579 spin_lock_irq(&intr->lock); zd_usb_enable_int()
580 intr->urb = NULL; zd_usb_enable_int()
581 spin_unlock_irq(&intr->lock); zd_usb_enable_int()
592 struct zd_usb_interrupt *intr = &usb->intr; zd_usb_disable_int() local
597 spin_lock_irqsave(&intr->lock, flags); zd_usb_disable_int()
598 urb = intr->urb; zd_usb_disable_int()
600 spin_unlock_irqrestore(&intr->lock, flags); zd_usb_disable_int()
603 intr->urb = NULL; zd_usb_disable_int()
604 buffer = intr->buffer; zd_usb_disable_int()
605 buffer_dma = intr->buffer_dma; zd_usb_disable_int()
606 intr->buffer = NULL; zd_usb_disable_int()
607 spin_unlock_irqrestore(&intr->lock, flags); zd_usb_disable_int()
1170 struct zd_usb_interrupt *intr = &usb->intr; init_usb_interrupt() local
1172 spin_lock_init(&intr->lock); init_usb_interrupt()
1173 intr->interval = int_urb_interval(zd_usb_to_usbdev(usb)); init_usb_interrupt()
1174 init_completion(&intr->read_regs.completion); init_usb_interrupt()
1175 atomic_set(&intr->read_regs_enabled, 0); init_usb_interrupt()
1176 intr->read_regs.cr_int_addr = cpu_to_le16((u16)CR_INTERRUPT); init_usb_interrupt()
1615 struct zd_usb_interrupt *intr = &usb->intr; prepare_read_regs_int() local
1617 spin_lock_irq(&intr->lock); prepare_read_regs_int()
1618 atomic_set(&intr->read_regs_enabled, 1); prepare_read_regs_int()
1619 intr->read_regs.req = req; prepare_read_regs_int()
1620 intr->read_regs.req_count = count; prepare_read_regs_int()
1621 reinit_completion(&intr->read_regs.completion); prepare_read_regs_int()
1622 spin_unlock_irq(&intr->lock); prepare_read_regs_int()
1627 struct zd_usb_interrupt *intr = &usb->intr; disable_read_regs_int() local
1629 spin_lock_irq(&intr->lock); disable_read_regs_int()
1630 atomic_set(&intr->read_regs_enabled, 0); disable_read_regs_int()
1631 spin_unlock_irq(&intr->lock); disable_read_regs_int()
1638 struct zd_usb_interrupt *intr = &usb->intr; check_read_regs() local
1639 struct read_regs_int *rr = &intr->read_regs; check_read_regs()
1679 struct zd_usb_interrupt *intr = &usb->intr; get_results() local
1680 struct read_regs_int *rr = &intr->read_regs; get_results()
1683 spin_lock_irq(&intr->lock); get_results()
1688 *retry = !!intr->read_regs_int_overridden; get_results()
1704 spin_unlock_irq(&intr->lock); get_results()
1769 timeout = wait_for_completion_timeout(&usb->intr.read_regs.completion, zd_usb_ioread16v()
H A Dzd_usb.h177 static inline struct usb_int_regs *get_read_regs(struct zd_usb_interrupt *intr) get_read_regs() argument
179 return (struct usb_int_regs *)intr->read_regs.buffer; get_read_regs()
219 struct zd_usb_interrupt intr; member in struct:zd_usb
/linux-4.1.27/drivers/scsi/
H A Dmac53c94.c45 int intr; member in struct:fsc_state
199 int nb, stat, seq, intr; mac53c94_interrupt() local
208 intr = readb(&regs->interrupt); mac53c94_interrupt()
211 printk(KERN_DEBUG "mac53c94_intr, intr=%x stat=%x seq=%x phase=%d\n", mac53c94_interrupt()
212 intr, stat, seq, state->phase); mac53c94_interrupt()
215 if (intr & INTR_RESET) { mac53c94_interrupt()
223 if (intr & INTR_ILL_CMD) { mac53c94_interrupt()
224 printk(KERN_ERR "53c94: invalid cmd, intr=%x stat=%x seq=%x phase=%d\n", mac53c94_interrupt()
225 intr, stat, seq, state->phase); mac53c94_interrupt()
232 printk("53c94: bad error, intr=%x stat=%x seq=%x phase=%d\n", mac53c94_interrupt()
233 intr, stat, seq, state->phase); mac53c94_interrupt()
249 if (intr & INTR_DISCONNECT) { mac53c94_interrupt()
254 if (intr != INTR_BUS_SERV + INTR_DONE) { mac53c94_interrupt()
255 printk(KERN_DEBUG "got intr %x during selection\n", intr); mac53c94_interrupt()
293 if (intr != INTR_BUS_SERV) { mac53c94_interrupt()
294 printk(KERN_DEBUG "got intr %x before status\n", intr); mac53c94_interrupt()
312 printk(KERN_DEBUG "intr %x before data xfer complete\n", intr); mac53c94_interrupt()
321 if (intr != INTR_DONE) { mac53c94_interrupt()
322 printk(KERN_DEBUG "got intr %x on completion\n", intr); mac53c94_interrupt()
333 if (intr != INTR_DISCONNECT) { mac53c94_interrupt()
334 printk(KERN_DEBUG "got intr %x when expected disconnect\n", intr); mac53c94_interrupt()
447 state->intr = macio_irq(mdev, 0); mac53c94_probe()
484 if (request_irq(state->intr, do_mac53c94_interrupt, 0, "53C94",state)) { mac53c94_probe()
486 state->intr, node->full_name); mac53c94_probe()
498 free_irq(state->intr, state); mac53c94_probe()
520 free_irq(fp->intr, fp); mac53c94_remove()
H A Dmesh.c444 dlog(ms, "about to arb, intr/exc/err/fc=%.8x", mesh_start_cmd()
456 dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x", mesh_start_cmd()
463 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x", mesh_start_cmd()
501 dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x", mesh_start_cmd()
507 dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x", mesh_start_cmd()
519 dlog(ms, "after arb, intr/exc/err/fc=%.8x", mesh_start_cmd()
524 dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x", mesh_start_cmd()
535 dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x", mesh_start_cmd()
810 dlog(ms, "enbresel intr/exc/err/fc=%.8x", start_phase()
1659 int intr; mesh_interrupt() local
1668 while ((intr = in_8(&mr->interrupt)) != 0) { mesh_interrupt()
1669 dlog(ms, "interrupt intr/err/exc/seq=%.8x", mesh_interrupt()
1670 MKWORD(intr, mr->error, mr->exception, mr->sequence)); mesh_interrupt()
1671 if (intr & INT_ERROR) { mesh_interrupt()
1673 } else if (intr & INT_EXCEPTION) { mesh_interrupt()
1675 } else if (intr & INT_CMDDONE) { mesh_interrupt()
/linux-4.1.27/include/linux/irqchip/
H A Dmips-gic.h48 #define GIC_INTR_OFS(intr) (((intr) / 32) * 4)
49 #define GIC_INTR_BIT(intr) ((intr) % 32)
75 #define GIC_SH_MAP_TO_PIN(intr) (4 * (intr))
79 #define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
80 ((32 * (intr)) + (((vpe) / 32) * 4))
104 #define GIC_VPE_EIC_SS(intr) (4 * (intr))
107 #define GIC_VPE_EIC_VEC(intr) (4 * (intr))
131 #define GIC_SH_WEDGE_SET(intr) ((intr) | (0x1 << 31))
132 #define GIC_SH_WEDGE_CLR(intr) ((intr) & ~(0x1 << 31))
251 extern void gic_send_ipi(unsigned int intr);
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
H A Dnv04.h17 void (*intr)(struct nvkm_subdev *); member in struct:nv04_bus_impl
H A Dnv04.c41 if (subdev && subdev->intr) nv04_bus_intr()
42 subdev->intr(subdev); nv04_bus_intr()
48 nv_error(pbus, "unknown intr 0x%08x\n", stat); nv04_bus_intr()
78 nv_subdev(priv)->intr = impl->intr; nv04_bus_ctor()
93 .intr = nv04_bus_intr,
H A Dnv31.c36 if (subdev && subdev->intr) nv31_bus_intr()
37 subdev->intr(subdev); nv31_bus_intr()
54 if (subdev && subdev->intr) nv31_bus_intr()
55 subdev->intr(subdev); nv31_bus_intr()
61 nv_error(pbus, "unknown intr 0x%08x\n", stat); nv31_bus_intr()
90 .intr = nv31_bus_intr,
H A Dnv50.c65 if (subdev && subdev->intr) nv50_bus_intr()
66 subdev->intr(subdev); nv50_bus_intr()
72 nv_error(pbus, "unknown intr 0x%08x\n", stat); nv50_bus_intr()
101 .intr = nv50_bus_intr,
H A Dgf100.c50 nv_error(pbus, "unknown intr 0x%08x\n", stat); gf100_bus_intr()
79 .intr = gf100_bus_intr,
H A Dg94.c55 .intr = nv50_bus_intr,
/linux-4.1.27/arch/s390/include/asm/
H A Dtermios.h12 /* intr=^C quit=^\ erase=del kill=^U
/linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp5/
H A Dmdp5_irq.c92 uint32_t intr; mdp5_irq() local
94 intr = mdp5_read(mdp5_kms, REG_MDSS_HW_INTR_STATUS); mdp5_irq()
96 VERB("intr=%08x", intr); mdp5_irq()
98 if (intr & MDSS_HW_INTR_STATUS_INTR_MDP) { mdp5_irq()
100 intr &= ~MDSS_HW_INTR_STATUS_INTR_MDP; mdp5_irq()
103 while (intr) { mdp5_irq()
104 irq_hw_number_t hwirq = fls(intr) - 1; mdp5_irq()
107 intr &= ~(1 << hwirq); mdp5_irq()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
H A Dg84.c144 uint32_t intr; g84_therm_intr() local
148 intr = nv_rd32(therm, 0x20100) & 0x3ff; g84_therm_intr()
151 if (intr & 0x002) { g84_therm_intr()
155 intr &= ~0x002; g84_therm_intr()
159 if (intr & 0x004) { g84_therm_intr()
163 intr &= ~0x004; g84_therm_intr()
167 if (intr & 0x008) { g84_therm_intr()
171 intr &= ~0x008; g84_therm_intr()
175 if (intr & 0x010) { g84_therm_intr()
179 intr &= ~0x010; g84_therm_intr()
182 if (intr) g84_therm_intr()
183 nv_error(therm, "unhandled intr 0x%08x\n", intr); g84_therm_intr()
225 nv_subdev(priv)->intr = g84_therm_intr; g84_therm_ctor()
/linux-4.1.27/arch/avr32/include/asm/
H A Dtermios.h13 /* intr=^C quit=^\ erase=del kill=^U
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dbase.c142 u32 intr = nv_rd32(pmu, 0x10a008) & disp & ~(disp >> 16); nvkm_pmu_intr() local
144 if (intr & 0x00000020) { nvkm_pmu_intr()
150 intr &= ~0x00000020; nvkm_pmu_intr()
154 if (intr & 0x00000040) { nvkm_pmu_intr()
157 intr &= ~0x00000040; nvkm_pmu_intr()
160 if (intr & 0x00000080) { nvkm_pmu_intr()
164 intr &= ~0x00000080; nvkm_pmu_intr()
167 if (intr) { nvkm_pmu_intr()
168 nv_error(pmu, "intr 0x%08x\n", intr); nvkm_pmu_intr()
169 nv_wr32(pmu, 0x10a004, intr); nvkm_pmu_intr()
195 nv_subdev(pmu)->intr = nvkm_pmu_intr; _nvkm_pmu_init()
/linux-4.1.27/arch/mips/sgi-ip27/
H A Dip27-irq.c36 #include <asm/sn/intr.h>
74 * intr enabling. Basically, once we grab the set of intrs we need
76 * sure the same intr does not intr again, causing recursion that
78 * one intr we are do_IRQing, because the non-masked intrs in the
79 * first set might intr again, causing multiple servicings of the
80 * same intr. This effect is mostly seen for intercpu intrs.
H A Dip27-init.c29 #include <asm/sn/intr.h>
186 * hub_rtc init and cpu clock intr enabled for later calibrate_delay. plat_mem_setup()
/linux-4.1.27/drivers/mtd/onenand/
H A Domap2.c93 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr) wait_err() argument
95 printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n", wait_err()
96 msg, state, ctrl, intr); wait_err()
100 unsigned int intr) wait_warn()
103 "intr 0x%04x\n", msg, state, ctrl, intr); wait_warn()
110 unsigned int intr = 0; omap2_onenand_wait() local
134 intr = read_reg(c, ONENAND_REG_INTERRUPT); omap2_onenand_wait()
135 if (intr & ONENAND_INT_MASTER) omap2_onenand_wait()
140 wait_err("controller error", state, ctrl, intr); omap2_onenand_wait()
143 if ((intr & intr_flags) == intr_flags) omap2_onenand_wait()
166 intr = read_reg(c, ONENAND_REG_INTERRUPT); omap2_onenand_wait()
167 wait_err("gpio error", state, ctrl, intr); omap2_onenand_wait()
189 intr = read_reg(c, omap2_onenand_wait()
191 wait_err("timeout", state, ctrl, intr); omap2_onenand_wait()
194 intr = read_reg(c, ONENAND_REG_INTERRUPT); omap2_onenand_wait()
195 if ((intr & ONENAND_INT_MASTER) == 0) omap2_onenand_wait()
196 wait_warn("timeout", state, ctrl, intr); omap2_onenand_wait()
210 intr = read_reg(c, ONENAND_REG_INTERRUPT); omap2_onenand_wait()
211 if (intr & ONENAND_INT_MASTER) omap2_onenand_wait()
233 intr = read_reg(c, ONENAND_REG_INTERRUPT); omap2_onenand_wait()
236 if (intr & ONENAND_INT_READ) { omap2_onenand_wait()
258 wait_err("timeout", state, ctrl, intr); omap2_onenand_wait()
263 wait_err("controller error", state, ctrl, intr); omap2_onenand_wait()
275 wait_warn("unexpected controller status", state, ctrl, intr); omap2_onenand_wait()
99 wait_warn(char *msg, int state, unsigned int ctrl, unsigned int intr) wait_warn() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/
H A Dxtensa.c60 u32 intr = nv_ro32(xtensa, 0xc20); _nvkm_xtensa_intr() local
64 if (intr & 0x10) _nvkm_xtensa_intr()
66 nv_wo32(xtensa, 0xc20, intr); _nvkm_xtensa_intr()
67 intr = nv_ro32(xtensa, 0xc20); _nvkm_xtensa_intr()
68 if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) { _nvkm_xtensa_intr()
89 nv_subdev(xtensa)->intr = _nvkm_xtensa_intr; nvkm_xtensa_create_()
H A Dfalcon.c32 u32 intr = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16); nvkm_falcon_intr() local
34 if (intr & 0x00000010) { nvkm_falcon_intr()
37 intr &= ~0x00000010; nvkm_falcon_intr()
40 if (intr) { nvkm_falcon_intr()
41 nv_error(falcon, "unhandled intr 0x%08x\n", intr); nvkm_falcon_intr()
42 nv_wo32(falcon, 0x004, intr); nvkm_falcon_intr()
/linux-4.1.27/arch/powerpc/platforms/52xx/
H A Dmpc52xx_pic.c133 static struct mpc52xx_intr __iomem *intr; variable in typeref:struct:__iomem
161 io_be_clrbit(&intr->ctrl, 11 - l2irq); mpc52xx_extirq_mask()
167 io_be_setbit(&intr->ctrl, 11 - l2irq); mpc52xx_extirq_unmask()
173 io_be_setbit(&intr->ctrl, 27-l2irq); mpc52xx_extirq_ack()
194 ctrl_reg = in_be32(&intr->ctrl); mpc52xx_extirq_set_type()
197 out_be32(&intr->ctrl, ctrl_reg); mpc52xx_extirq_set_type()
223 io_be_setbit(&intr->main_mask, 16 - l2irq); mpc52xx_main_mask()
229 io_be_clrbit(&intr->main_mask, 16 - l2irq); mpc52xx_main_unmask()
246 io_be_setbit(&intr->per_mask, 31 - l2irq); mpc52xx_periph_mask()
252 io_be_clrbit(&intr->per_mask, 31 - l2irq); mpc52xx_periph_unmask()
356 reg = in_be32(&intr->ctrl); mpc52xx_irqhost_map()
410 intr = of_iomap(picnode, 0); mpc52xx_init_irq()
411 if (!intr) mpc52xx_init_irq()
422 pr_debug("MPC5200 IRQ controller mapped to 0x%p\n", intr); mpc52xx_init_irq()
427 out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */ mpc52xx_init_irq()
428 out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */ mpc52xx_init_irq()
429 intr_ctrl = in_be32(&intr->ctrl); mpc52xx_init_irq()
435 out_be32(&intr->ctrl, intr_ctrl); mpc52xx_init_irq()
438 out_be32(&intr->per_pri1, 0); mpc52xx_init_irq()
439 out_be32(&intr->per_pri2, 0); mpc52xx_init_irq()
440 out_be32(&intr->per_pri3, 0); mpc52xx_init_irq()
441 out_be32(&intr->main_pri1, 0); mpc52xx_init_irq()
442 out_be32(&intr->main_pri2, 0); mpc52xx_init_irq()
492 status = in_be32(&intr->enc_status); mpc52xx_get_irq()
H A Dmpc52xx_pm.c19 static struct mpc52xx_intr __iomem *intr; variable in typeref:struct:__iomem
88 intr = mbar + 0x500; mpc52xx_pm_prepare()
122 intr_main_mask = in_be32(&intr->main_mask); mpc52xx_pm_enter()
123 out_be32(&intr->main_mask, intr_main_mask | 0x1ffff); mpc52xx_pm_enter()
156 mpc52xx_deep_sleep(sram, sdram, cdm, intr); mpc52xx_pm_enter()
175 out_be32(&intr->main_mask, intr_main_mask); mpc52xx_pm_enter()
H A Dmpc52xx_sleep.S20 lwz r8, 0x14(r6) /* intr->main_mask */
28 stw r8, 0x40(r6) /* intr->main_emulate */
130 addi r7, r7, 0x540 /* intr->main_emul */
138 addi r7, r7, 0x524 /* intr->enc_status */
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A Dgk104.c29 u32 intr = nv_rd32(i2c, 0x00dc60); gk104_aux_stat() local
30 u32 stat = nv_rd32(i2c, 0x00dc68) & intr, i; gk104_aux_stat()
37 nv_wr32(i2c, 0x00dc60, intr); gk104_aux_stat()
H A Dg94.c29 u32 intr = nv_rd32(i2c, 0x00e06c); g94_aux_stat() local
30 u32 stat = nv_rd32(i2c, 0x00e068) & intr, i; g94_aux_stat()
37 nv_wr32(i2c, 0x00e06c, intr); g94_aux_stat()
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/
H A Ddma.h22 unsigned intr : 1; member in struct:dma_descr_group
40 unsigned intr : 1; member in struct:dma_descr_context
62 unsigned intr : 1; member in struct:dma_descr_data
H A Ddma_defs.h107 unsigned int intr : 1; member in struct:__anon421
158 unsigned int intr : 1; member in struct:__anon425
258 unsigned int intr : 1; member in struct:__anon429
/linux-4.1.27/drivers/misc/
H A Dfsa9480.c267 static void fsa9480_detect_dev(struct fsa9480_usbsw *usbsw, int intr) fsa9480_detect_dev() argument
277 dev_info(&client->dev, "intr: 0x%x, dev1: 0x%x, dev2: 0x%x\n", fsa9480_detect_dev()
278 intr, val1, val2); fsa9480_detect_dev()
280 if (!intr) fsa9480_detect_dev()
283 if (intr & INT_ATTACH) { /* Attached */ fsa9480_detect_dev()
317 } else if (intr & INT_DETACH) { /* Detached */ fsa9480_detect_dev()
357 int intr; fsa9480_irq_handler() local
360 fsa9480_read_irq(client, &intr); fsa9480_irq_handler()
363 fsa9480_detect_dev(usbsw, intr); fsa9480_irq_handler()
373 int intr; fsa9480_irq_init() local
377 fsa9480_read_irq(client, &intr); fsa9480_irq_init()
/linux-4.1.27/drivers/macintosh/
H A Dmacio-adb.c26 struct preg intr; member in struct:adb_regs
38 /* Bits in intr and intr_enb registers */
111 out_8(&adb->intr.r, 0); macio_init()
212 if (in_8(&adb->intr.r) & TAG) { macio_adb_interrupt()
230 out_8(&adb->intr.r, 0); macio_adb_interrupt()
233 if (in_8(&adb->intr.r) & DFB) { macio_adb_interrupt()
257 out_8(&adb->intr.r, 0); macio_adb_interrupt()
281 if (in_8(&adb->intr.r) != 0) macio_adb_poll()
/linux-4.1.27/drivers/dma-buf/
H A Dseqno-fence.c59 static signed long seqno_wait(struct fence *fence, bool intr, signed long timeout) seqno_wait() argument
62 return f->ops->wait(fence, intr, timeout); seqno_wait()
H A Dfence.c142 * @intr: [in] if true, do an interruptible wait
155 fence_wait_timeout(struct fence *fence, bool intr, signed long timeout) fence_wait_timeout() argument
166 ret = fence->ops->wait(fence, intr, timeout); fence_wait_timeout()
334 * @intr: [in] if true, do an interruptible wait
341 fence_default_wait(struct fence *fence, bool intr, signed long timeout) fence_default_wait() argument
353 if (intr && signal_pending(current)) { fence_default_wait()
377 if (intr) fence_default_wait()
386 if (ret > 0 && intr && signal_pending(current)) fence_default_wait()
/linux-4.1.27/sound/pci/ca0106/
H A Dca_midi.h55 void (*interrupt_enable)(struct snd_ca_midi *midi, int intr);
56 void (*interrupt_disable)(struct snd_ca_midi *midi, int intr);
/linux-4.1.27/drivers/isdn/hisax/
H A Dst5481_usb.c242 struct st5481_intr *intr = &adapter->intr; st5481_setup_usb() local
299 intr->urb = urb; st5481_setup_usb()
317 usb_free_urb(intr->urb); st5481_setup_usb()
318 intr->urb = NULL; st5481_setup_usb()
332 struct st5481_intr *intr = &adapter->intr; st5481_release_usb() local
343 usb_kill_urb(intr->urb); st5481_release_usb()
344 kfree(intr->urb->transfer_buffer); st5481_release_usb()
345 usb_free_urb(intr->urb); st5481_release_usb()
346 intr->urb = NULL; st5481_release_usb()
371 struct st5481_intr *intr = &adapter->intr; st5481_start() local
380 SUBMIT_URB(intr->urb, GFP_KERNEL); st5481_start()
/linux-4.1.27/arch/microblaze/kernel/
H A Dintc.c148 ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq); xilinx_intc_of_init()
150 pr_err("%s: unable to read xlnx,num-intr-inputs\n", __func__); xilinx_intc_of_init()
154 ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask); xilinx_intc_of_init()
156 pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__); xilinx_intc_of_init()
161 pr_warn("%s: mismatch in kind-of-intr param\n", __func__); xilinx_intc_of_init()
/linux-4.1.27/drivers/net/vmxnet3/
H A Dvmxnet3_drv.c52 * Enable/Disable the given intr
76 for (i = 0; i < adapter->intr.num_intrs; i++) vmxnet3_enable_all_intrs()
90 for (i = 0; i < adapter->intr.num_intrs; i++) vmxnet3_disable_all_intrs()
1663 * Returns whether or not the intr is handled
1672 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) vmxnet3_msix_tx()
1693 * intr is handled
1702 /* disable intr if needed */ vmxnet3_msix_rx()
1703 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) vmxnet3_msix_rx()
1715 * vmxnet3 msix event intr handler
1718 * whether or not the intr is handled
1729 /* disable intr if needed */ vmxnet3_msix_event()
1730 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) vmxnet3_msix_event()
1731 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx); vmxnet3_msix_event()
1736 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx); vmxnet3_msix_event()
1751 if (adapter->intr.type == VMXNET3_IT_INTX) { vmxnet3_intr()
1759 /* disable intr if needed */ vmxnet3_intr()
1760 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) vmxnet3_intr()
1776 switch (adapter->intr.type) { vmxnet3_netpoll()
1797 struct vmxnet3_intr *intr = &adapter->intr; vmxnet3_request_irqs() local
1802 if (adapter->intr.type == VMXNET3_IT_MSIX) { vmxnet3_request_irqs()
1808 intr->msix_entries[vector].vector, vmxnet3_request_irqs()
1847 err = request_irq(intr->msix_entries[vector].vector, vmxnet3_request_irqs()
1862 sprintf(intr->event_msi_vector_name, "%s-event-%d", vmxnet3_request_irqs()
1864 err = request_irq(intr->msix_entries[vector].vector, vmxnet3_request_irqs()
1866 intr->event_msi_vector_name, adapter->netdev); vmxnet3_request_irqs()
1867 intr->event_intr_idx = vector; vmxnet3_request_irqs()
1869 } else if (intr->type == VMXNET3_IT_MSI) { vmxnet3_request_irqs()
1882 intr->num_intrs = vector + 1; vmxnet3_request_irqs()
1885 "Failed to request irq (intr type:%d), error %d\n", vmxnet3_request_irqs()
1886 intr->type, err); vmxnet3_request_irqs()
1897 /* init our intr settings */ vmxnet3_request_irqs()
1898 for (i = 0; i < intr->num_intrs; i++) vmxnet3_request_irqs()
1899 intr->mod_levels[i] = UPT1_IML_ADAPTIVE; vmxnet3_request_irqs()
1900 if (adapter->intr.type != VMXNET3_IT_MSIX) { vmxnet3_request_irqs()
1901 adapter->intr.event_intr_idx = 0; vmxnet3_request_irqs()
1908 "intr type %u, mode %u, %u vectors allocated\n", vmxnet3_request_irqs()
1909 intr->type, intr->mask_mode, intr->num_intrs); vmxnet3_request_irqs()
1919 struct vmxnet3_intr *intr = &adapter->intr; vmxnet3_free_irqs() local
1920 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0); vmxnet3_free_irqs()
1922 switch (intr->type) { vmxnet3_free_irqs()
1930 free_irq(intr->msix_entries[vector++].vector, vmxnet3_free_irqs()
1938 free_irq(intr->msix_entries[vector++].vector, vmxnet3_free_irqs()
1942 free_irq(intr->msix_entries[vector].vector, vmxnet3_free_irqs()
1944 BUG_ON(vector >= intr->num_intrs); vmxnet3_free_irqs()
2237 /* intr settings */ vmxnet3_setup_driver_shared()
2238 devRead->intrConf.autoMask = adapter->intr.mask_mode == vmxnet3_setup_driver_shared()
2240 devRead->intrConf.numIntrs = adapter->intr.num_intrs; vmxnet3_setup_driver_shared()
2241 for (i = 0; i < adapter->intr.num_intrs; i++) vmxnet3_setup_driver_shared()
2242 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i]; vmxnet3_setup_driver_shared()
2244 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx; vmxnet3_setup_driver_shared()
2759 adapter->intr.msix_entries, nvec, nvec); vmxnet3_acquire_msix_vectors()
2767 adapter->intr.msix_entries, vmxnet3_acquire_msix_vectors()
2789 /* intr settings */ vmxnet3_alloc_intr_resources()
2795 adapter->intr.type = cfg & 0x3; vmxnet3_alloc_intr_resources()
2796 adapter->intr.mask_mode = (cfg >> 2) & 0x3; vmxnet3_alloc_intr_resources()
2798 if (adapter->intr.type == VMXNET3_IT_AUTO) { vmxnet3_alloc_intr_resources()
2799 adapter->intr.type = VMXNET3_IT_MSIX; vmxnet3_alloc_intr_resources()
2803 if (adapter->intr.type == VMXNET3_IT_MSIX) { vmxnet3_alloc_intr_resources()
2815 adapter->intr.msix_entries[i].entry = i; vmxnet3_alloc_intr_resources()
2834 adapter->intr.num_intrs = nvec; vmxnet3_alloc_intr_resources()
2843 adapter->intr.type = VMXNET3_IT_MSI; vmxnet3_alloc_intr_resources()
2846 if (adapter->intr.type == VMXNET3_IT_MSI) { vmxnet3_alloc_intr_resources()
2849 adapter->intr.num_intrs = 1; vmxnet3_alloc_intr_resources()
2858 adapter->intr.type = VMXNET3_IT_INTX; vmxnet3_alloc_intr_resources()
2861 adapter->intr.num_intrs = 1; vmxnet3_alloc_intr_resources()
2868 if (adapter->intr.type == VMXNET3_IT_MSIX) vmxnet3_free_intr_resources()
2870 else if (adapter->intr.type == VMXNET3_IT_MSI) vmxnet3_free_intr_resources()
2873 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX); vmxnet3_free_intr_resources()
3072 adapter->intr.type == VMXNET3_IT_MSIX) { vmxnet3_probe_device()
3092 if (adapter->intr.type == VMXNET3_IT_MSIX) { vmxnet3_probe_device()
H A Dupt1_defs.h60 UPT1_IML_HIGHEST = 7, /* least intr generated */
61 UPT1_IML_ADAPTIVE = 8, /* adpative intr moderation */
H A Dvmxnet3_int.h299 u8 num_intrs; /* # of intr vectors */
300 u8 event_intr_idx; /* idx of the intr vector for event */
320 struct vmxnet3_intr intr; member in struct:vmxnet3_adapter
/linux-4.1.27/drivers/gpu/drm/nouveau/
H A Dnouveau_fence.c314 nouveau_fence_wait_legacy(struct fence *f, bool intr, long wait) nouveau_fence_wait_legacy() argument
330 __set_current_state(intr ? TASK_INTERRUPTIBLE : nouveau_fence_wait_legacy()
339 if (intr && signal_pending(current)) nouveau_fence_wait_legacy()
349 nouveau_fence_wait_busy(struct nouveau_fence *fence, bool intr) nouveau_fence_wait_busy() argument
359 __set_current_state(intr ? nouveau_fence_wait_busy()
363 if (intr && signal_pending(current)) { nouveau_fence_wait_busy()
374 nouveau_fence_wait(struct nouveau_fence *fence, bool lazy, bool intr) nouveau_fence_wait() argument
379 return nouveau_fence_wait_busy(fence, intr); nouveau_fence_wait()
381 ret = fence_wait_timeout(&fence->base, intr, 15 * HZ); nouveau_fence_wait()
391 nouveau_fence_sync(struct nouveau_bo *nvbo, struct nouveau_channel *chan, bool exclusive, bool intr) nouveau_fence_sync() argument
424 ret = fence_wait(fence, intr); nouveau_fence_sync()
449 ret = fence_wait(fence, intr); nouveau_fence_sync()
H A Dnouveau_fence.h28 int nouveau_fence_wait(struct nouveau_fence *, bool lazy, bool intr);
29 int nouveau_fence_sync(struct nouveau_bo *, struct nouveau_channel *, bool exclusive, bool intr);
H A Dnouveau_bo.c1062 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, nouveau_bo_move_m2mf() argument
1082 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr); nouveau_bo_move_m2mf()
1162 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, nouveau_bo_move_flipd() argument
1179 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu); nouveau_bo_move_flipd()
1187 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem); nouveau_bo_move_flipd()
1198 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, nouveau_bo_move_flips() argument
1215 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu); nouveau_bo_move_flips()
1223 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem); nouveau_bo_move_flips()
1289 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, nouveau_bo_move() argument
1318 ret = nouveau_bo_move_flipd(bo, evict, intr, nouveau_bo_move()
1321 ret = nouveau_bo_move_flips(bo, evict, intr, nouveau_bo_move()
1324 ret = nouveau_bo_move_m2mf(bo, evict, intr, nouveau_bo_move()
1331 ret = ttm_bo_wait(bo, true, intr, no_wait_gpu); nouveau_bo_move()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
H A Dnv10.c83 u32 intr = nv_rd32(gpio, 0x001104); nv10_gpio_intr_stat() local
84 u32 stat = nv_rd32(gpio, 0x001144) & intr; nv10_gpio_intr_stat()
87 nv_wr32(gpio, 0x001104, intr); nv10_gpio_intr_stat()
H A Dnv50.c95 u32 intr = nv_rd32(gpio, 0x00e054); nv50_gpio_intr_stat() local
96 u32 stat = nv_rd32(gpio, 0x00e050) & intr; nv50_gpio_intr_stat()
99 nv_wr32(gpio, 0x00e054, intr); nv50_gpio_intr_stat()
/linux-4.1.27/drivers/gpu/host1x/hw/
H A Dintr_hw.c24 #include "../intr.h"
41 queue_work(host->intr_wq, &syncpt->intr.work); host1x_intr_syncpt_handle()
83 INIT_WORK(&host->syncpt[i].intr.work, syncpt_thresh_work); _host1x_intr_init_host_sync()
/linux-4.1.27/arch/mips/pci/
H A Dops-gt64xxx_pci0.c46 u32 intr; gt64xxx_pci0_pcibios_config_access() local
83 intr = GT_READ(GT_INTRCAUSE_OFS); gt64xxx_pci0_pcibios_config_access()
85 if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) { gt64xxx_pci0_pcibios_config_access()
H A Dops-msc.c50 u32 intr; msc_pcibios_config_access() local
69 MSC_READ(MSC01_PCI_INTSTAT, intr); msc_pcibios_config_access()
70 if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) { msc_pcibios_config_access()
/linux-4.1.27/drivers/net/wan/
H A Dx25_asy.h23 struct net_device *dev; /* easy for intr handling */
H A Dsdla.c948 struct intr_info intr; sdla_close() local
968 memset(&intr, 0, sizeof(intr)); sdla_close()
977 sdla_cmd(dev, SDLA_SET_IRQ_TRIGGER, 0, 0, &intr, sizeof(char) + sizeof(short), NULL, NULL); sdla_close()
986 sdla_cmd(dev, SDLA_SET_IRQ_TRIGGER, 0, 0, &intr, sizeof(struct intr_info), NULL, NULL); sdla_close()
1009 struct intr_info intr; sdla_open() local
1040 memset(&intr, 0, sizeof(intr)); sdla_open()
1055 intr.flags = SDLA_INTR_RX | SDLA_INTR_STATUS | SDLA_INTR_MODEM; sdla_open()
1056 sdla_cmd(dev, SDLA_SET_IRQ_TRIGGER, 0, 0, &intr, sizeof(char) + sizeof(short), NULL, NULL); sdla_open()
1067 intr.flags = SDLA_INTR_RX | SDLA_INTR_STATUS | SDLA_INTR_MODEM; sdla_open()
1068 intr.irq = dev->irq; sdla_open()
1069 sdla_cmd(dev, SDLA_SET_IRQ_TRIGGER, 0, 0, &intr, sizeof(struct intr_info), NULL, NULL); sdla_open()
H A Dz85230.c710 u8 uninitialized_var(intr); z8530_interrupt()
727 intr = read_zsreg(&dev->chanA, R3); z8530_interrupt()
728 if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT))) z8530_interrupt()
739 if(intr & (CHARxIP|CHATxIP|CHAEXT)) z8530_interrupt()
741 if(intr&CHARxIP) z8530_interrupt()
743 if(intr&CHATxIP) z8530_interrupt()
745 if(intr&CHAEXT) z8530_interrupt()
751 if(intr & (CHBRxIP|CHBTxIP|CHBEXT)) z8530_interrupt()
753 if(intr&CHBRxIP) z8530_interrupt()
755 if(intr&CHBTxIP) z8530_interrupt()
757 if(intr&CHBEXT) z8530_interrupt()
764 dev->name, intr); z8530_interrupt()
/linux-4.1.27/arch/tile/include/hv/
H A Ddrv_pcie_rc_intf.h34 int intr; /**< interrupt number used for downcall */ member in struct:pcie_rc_config
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A Dgk104.c74 nv_warn(priv, "unhandled intr 0x%08x\n", stat); gk104_ce_intr()
94 nv_subdev(priv)->intr = gk104_ce_intr; gk104_ce0_ctor()
115 nv_subdev(priv)->intr = gk104_ce_intr; gk104_ce1_ctor()
136 nv_subdev(priv)->intr = gk104_ce_intr; gk104_ce2_ctor()
H A Dgm204.c74 nv_warn(priv, "unhandled intr 0x%08x\n", stat); gm204_ce_intr()
94 nv_subdev(priv)->intr = gm204_ce_intr; gm204_ce0_ctor()
115 nv_subdev(priv)->intr = gm204_ce_intr; gm204_ce1_ctor()
136 nv_subdev(priv)->intr = gm204_ce_intr; gm204_ce2_ctor()
H A Dgf100.c107 nv_subdev(priv)->intr = gt215_ce_intr; gf100_ce0_ctor()
132 nv_subdev(priv)->intr = gt215_ce_intr; gf100_ce1_ctor()
H A Dgt215.c108 nv_error(falcon, "unhandled intr 0x%08x\n", stat); gt215_ce_intr()
131 nv_subdev(priv)->intr = gt215_ce_intr; gt215_ce_ctor()
/linux-4.1.27/arch/mips/kvm/
H A Dinterrupt.c58 int intr = (int)irq->irq; kvm_mips_queue_io_int_cb() local
65 switch (intr) { kvm_mips_queue_io_int_cb()
91 int intr = (int)irq->irq; kvm_mips_dequeue_io_int_cb() local
93 switch (intr) { kvm_mips_dequeue_io_int_cb()
H A Dmips.c421 int intr = (int)irq->irq; kvm_vcpu_ioctl_interrupt() local
424 if (intr == 3 || intr == -3 || intr == 4 || intr == -4) kvm_vcpu_ioctl_interrupt()
426 (int)intr); kvm_vcpu_ioctl_interrupt()
433 if (intr == 2 || intr == 3 || intr == 4) { kvm_vcpu_ioctl_interrupt()
436 } else if (intr == -2 || intr == -3 || intr == -4) { kvm_vcpu_ioctl_interrupt()
/linux-4.1.27/arch/parisc/include/asm/
H A Dtermios.h7 /* intr=^C quit=^\ erase=del kill=^U
/linux-4.1.27/arch/cris/include/asm/
H A Dtermios.h7 /* intr=^C quit=^\ erase=del kill=^U
/linux-4.1.27/arch/m32r/include/asm/
H A Dtermios.h7 /* intr=^C quit=^\ erase=del kill=^U
/linux-4.1.27/drivers/spmi/
H A Dspmi-pmic-arb.c107 * @intr: address of the SPMI interrupt control registers.
126 void __iomem *intr; member in struct:spmi_pmic_arb_dev
442 status = readl_relaxed(pa->intr + pa->ver_ops->irq_status(apid)); periph_interrupt()
458 void __iomem *intr = pa->intr; pmic_arb_chained_irq() local
467 status = readl_relaxed(intr + pmic_arb_chained_irq()
488 writel_relaxed(1 << irq, pa->intr + pa->ver_ops->irq_clear(apid)); qpnpint_irq_ack()
505 status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid)); qpnpint_irq_mask()
508 writel_relaxed(status, pa->intr + qpnpint_irq_mask()
527 status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid)); qpnpint_irq_unmask()
530 pa->intr + pa->ver_ops->acc_enable(apid)); qpnpint_irq_unmask()
858 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr"); spmi_pmic_arb_probe()
859 pa->intr = devm_ioremap_resource(&ctrl->dev, res); spmi_pmic_arb_probe()
860 if (IS_ERR(pa->intr)) { spmi_pmic_arb_probe()
861 err = PTR_ERR(pa->intr); spmi_pmic_arb_probe()
/linux-4.1.27/drivers/scsi/bfa/
H A Dbfa_core.c769 u32 intr, qintr; bfa_msix_all() local
772 intr = readl(bfa->iocfc.bfa_regs.intr_status); bfa_msix_all()
773 if (!intr) bfa_msix_all()
779 qintr = intr & __HFN_INT_RME_MASK; bfa_msix_all()
785 intr &= ~qintr; bfa_msix_all()
786 if (!intr) bfa_msix_all()
792 qintr = intr & __HFN_INT_CPE_MASK; bfa_msix_all()
797 intr &= ~qintr; bfa_msix_all()
798 if (!intr) bfa_msix_all()
801 bfa_msix_lpu_err(bfa, intr); bfa_msix_all()
807 u32 intr, qintr; bfa_intx() local
811 intr = readl(bfa->iocfc.bfa_regs.intr_status); bfa_intx()
813 qintr = intr & (__HFN_INT_RME_MASK | __HFN_INT_CPE_MASK); bfa_intx()
826 if (!intr) bfa_intx()
832 qintr = intr & __HFN_INT_CPE_MASK; bfa_intx()
837 intr &= ~qintr; bfa_intx()
838 if (!intr) bfa_intx()
842 bfa_msix_lpu_err(bfa, intr); bfa_intx()
912 u32 intr, curr_value; bfa_msix_lpu_err() local
915 intr = readl(bfa->iocfc.bfa_regs.intr_status); bfa_msix_lpu_err()
918 halt_isr = intr & __HFN_INT_CPQ_HALT_CT2; bfa_msix_lpu_err()
919 pss_isr = intr & __HFN_INT_ERR_PSS_CT2; bfa_msix_lpu_err()
920 lpu_isr = intr & (__HFN_INT_MBOX_LPU0_CT2 | bfa_msix_lpu_err()
922 intr &= __HFN_INT_ERR_MASK_CT2; bfa_msix_lpu_err()
925 (intr & __HFN_INT_LL_HALT) : 0; bfa_msix_lpu_err()
926 pss_isr = intr & __HFN_INT_ERR_PSS; bfa_msix_lpu_err()
927 lpu_isr = intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1); bfa_msix_lpu_err()
928 intr &= __HFN_INT_ERR_MASK; bfa_msix_lpu_err()
934 if (intr) { bfa_msix_lpu_err()
958 writel(intr, bfa->iocfc.bfa_regs.intr_status); bfa_msix_lpu_err()
/linux-4.1.27/drivers/block/
H A Dswim3.c74 REG(intr);
110 /* Bits in intr and intr_enable registers */
411 in_8(&sw->intr); /* clear SEEN_SECTOR bit */ scan_track()
415 /* enable intr when track found */ scan_track()
433 /* enable intr when seek finished */ seek_track()
495 in_8(&sw->intr); setup_transfer()
497 /* enable intr when transfer complete */ setup_transfer()
679 int intr, err, n; swim3_interrupt() local
689 intr = in_8(&sw->intr); swim3_interrupt()
690 err = (intr & ERROR_INTR)? in_8(&sw->error): 0; swim3_interrupt()
691 if ((intr & ERROR_INTR) && fs->state != do_transfer) swim3_interrupt()
692 swim3_err("Non-transfer error interrupt: state=%d, dir=%x, intr=%x, err=%x\n", swim3_interrupt()
693 fs->state, rq_data_dir(req), intr, err); swim3_interrupt()
696 if (intr & SEEN_SECTOR) { swim3_interrupt()
745 if ((intr & (ERROR_INTR | TRANSFER_DONE)) == 0) swim3_interrupt()
763 if ((intr & ERROR_INTR) == 0 && cp->xfer_status == 0) { swim3_interrupt()
776 if (intr & ERROR_INTR) { swim3_interrupt()
796 swim3_err(" state=%d, dir=%x, intr=%x, err=%x\n", swim3_interrupt()
797 fs->state, rq_data_dir(req), intr, err); swim3_interrupt()
1108 in_8(&sw->intr); swim3_mb_event()
H A Dcpqarray.c257 (unsigned int) h->io_mem_addr, (unsigned int)h->intr, ida_proc_show()
336 free_irq(hba[i]->intr, hba[i]); cpqarray_remove_one()
408 if (request_irq(hba[i]->intr, do_ida_intr, IRQF_SHARED, cpqarray_register_ctlr()
412 hba[i]->intr, hba[i]->devname); cpqarray_register_ctlr()
494 free_irq(hba[i]->intr, hba[i]); cpqarray_register_ctlr()
661 c->intr = irq; cpqarray_pci_init()
749 int intr; cpqarray_eisa_detect() local
786 intr = inb(eisa[i]+0xCC0) >> 4; cpqarray_eisa_detect()
787 if (intr & 1) intr = 11; cpqarray_eisa_detect()
788 else if (intr & 2) intr = 10; cpqarray_eisa_detect()
789 else if (intr & 4) intr = 14; cpqarray_eisa_detect()
790 else if (intr & 8) intr = 15; cpqarray_eisa_detect()
792 hba[ctlr]->intr = intr; cpqarray_eisa_detect()
802 printk("irq = %x\n", intr); cpqarray_eisa_detect()
/linux-4.1.27/drivers/mmc/host/
H A Dmvsdio.c147 u32 cmdreg = 0, xfer = 0, intr = 0; mvsd_request() local
175 intr |= MVSD_NOR_UNEXP_RSP; mvsd_request()
192 intr |= MVSD_NOR_TX_AVAIL; mvsd_request()
194 intr |= MVSD_NOR_RX_FIFO_8W; mvsd_request()
196 intr |= MVSD_NOR_RX_READY; mvsd_request()
214 intr |= MVSD_NOR_AUTOCMD12_DONE; mvsd_request()
216 intr |= MVSD_NOR_XFER_DONE; mvsd_request()
219 intr |= MVSD_NOR_CMD_DONE; mvsd_request()
236 host->intr_en |= intr | MVSD_NOR_ERROR; mvsd_request()
357 dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n", mvsd_irq()
367 dev_dbg(host->dev, "spurious irq detected intr 0x%04x intr_en 0x%04x erri 0x%04x erri_en 0x%04x\n", mvsd_irq()
419 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", mvsd_irq()
456 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", mvsd_irq()
/linux-4.1.27/drivers/net/wireless/ti/wl1251/
H A Dmain.c219 u32 intr, ctr = WL1251_IRQ_LOOP_COUNT; wl1251_irq_work() local
237 intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_CLEAR); wl1251_irq_work()
238 wl1251_debug(DEBUG_IRQ, "intr: 0x%x", intr); wl1251_irq_work()
250 intr &= ~WL1251_ACX_INTR_RX0_DATA; wl1251_irq_work()
251 intr &= ~WL1251_ACX_INTR_RX1_DATA; wl1251_irq_work()
255 intr |= WL1251_ACX_INTR_RX0_DATA; wl1251_irq_work()
256 intr &= ~WL1251_ACX_INTR_RX1_DATA; wl1251_irq_work()
260 intr |= WL1251_ACX_INTR_RX0_DATA; wl1251_irq_work()
261 intr |= WL1251_ACX_INTR_RX1_DATA; wl1251_irq_work()
276 intr &= wl->intr_mask; wl1251_irq_work()
278 if (intr == 0) { wl1251_irq_work()
283 if (intr & WL1251_ACX_INTR_RX0_DATA) { wl1251_irq_work()
288 if (intr & WL1251_ACX_INTR_RX1_DATA) { wl1251_irq_work()
293 if (intr & WL1251_ACX_INTR_TX_RESULT) { wl1251_irq_work()
298 if (intr & WL1251_ACX_INTR_EVENT_A) { wl1251_irq_work()
303 if (intr & WL1251_ACX_INTR_EVENT_B) { wl1251_irq_work()
308 if (intr & WL1251_ACX_INTR_INIT_COMPLETE) wl1251_irq_work()
315 intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_CLEAR); wl1251_irq_work()
316 } while (intr); wl1251_irq_work()
H A Dcmd.c25 u32 intr; wl1251_cmd_send() local
40 intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); wl1251_cmd_send()
41 while (!(intr & WL1251_ACX_INTR_CMD_COMPLETE)) { wl1251_cmd_send()
50 intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); wl1251_cmd_send()
/linux-4.1.27/arch/sparc/kernel/
H A Dof_device_32.c342 const struct linux_prom_irqs *intr; scan_one_device() local
354 intr = of_get_property(dp, "intr", &len); scan_one_device()
355 if (intr) { scan_one_device()
359 sparc_config.build_device_irq(op, intr[i].pri); scan_one_device()
H A Dprom_32.c139 unsigned int *intr, *device, *vendor, reg0; ambapp_path_component() local
157 intr = &interrupt; /* IRQ0 does not exist */ ambapp_path_component()
159 intr = prop->value; ambapp_path_component()
172 *intr, reg0); ambapp_path_component()
H A Dsun4m_irq.c71 * This ambiguity is resolved in the 'intr' property for device nodes
72 * in the OF device tree. Each 'intr' property entry is composed of
81 * For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
83 * 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
H A Dgf100.c87 u32 intr = nv_rd32(priv, base + 0x020); gf100_ltc_lts_intr() local
88 u32 stat = intr & 0x0000ffff; gf100_ltc_lts_intr()
96 nv_wr32(priv, base + 0x020, intr); gf100_ltc_lts_intr()
225 nv_subdev(priv)->intr = gf100_ltc_intr; gf100_ltc_ctor()
238 .intr = gf100_ltc_intr,
H A Dgk104.c53 .intr = gf100_ltc_intr,
H A Dpriv.h54 void (*intr)(struct nvkm_subdev *); member in struct:nvkm_ltc_impl
H A Dbase.c115 priv->base.base.intr = impl->intr; nvkm_ltc_create_()
/linux-4.1.27/drivers/clocksource/
H A Dzevio-timer.c110 u32 intr; zevio_timer_interrupt() local
112 intr = readl(timer->interrupt_regs + IO_INTR_ACK); zevio_timer_interrupt()
113 if (!(intr & TIMER_INTR_MSK)) zevio_timer_interrupt()
/linux-4.1.27/drivers/gpu/drm/ttm/
H A Dttm_execbuf_util.c96 struct list_head *list, bool intr, ttm_eu_reserve_buffers()
115 ret = __ttm_bo_reserve(bo, intr, (ticket == NULL), true, list_for_each_entry()
145 if (ret == -EDEADLK && intr) { list_for_each_entry()
95 ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket, struct list_head *list, bool intr, struct list_head *dups) ttm_eu_reserve_buffers() argument
/linux-4.1.27/include/drm/ttm/
H A Dttm_execbuf_util.h70 * @intr: should the wait be interruptible
83 * If intr is set to true, this function may return -ERESTARTSYS if the
99 struct list_head *list, bool intr,
/linux-4.1.27/drivers/isdn/hysdn/
H A Dboardergo.h91 #define PCI9050_INTR_REG_STAT1 0x04 /* 1= intr. active, 0= intr. not active (def.) */
/linux-4.1.27/drivers/net/ethernet/8390/
H A Dapne.c232 outb(0xff, ioaddr + NE_EN0_ISR); /* Ack all intr. */ apne_probe1()
380 outb(ENISR_RESET, NE_BASE + NE_EN0_ISR); /* Ack intr. */ apne_reset_8390()
399 "[DMAstat:%d][irqlock:%d][intr:%d].\n", apne_get_8390_hdr()
423 outb(ENISR_RDC, nic_base + NE_EN0_ISR); /* Ack intr. */ apne_get_8390_hdr()
446 "[DMAstat:%d][irqlock:%d][intr:%d].\n", apne_block_input()
471 outb(ENISR_RDC, nic_base + NE_EN0_ISR); /* Ack intr. */ apne_block_input()
494 "[DMAstat:%d][irqlock:%d][intr:%d]\n", apne_block_output()
531 outb(ENISR_RDC, nic_base + NE_EN0_ISR); /* Ack intr. */ apne_block_output()
H A Dzorro8390.c106 z_writeb(ENISR_RESET, NE_BASE + NE_EN0_ISR); /* Ack intr */ zorro8390_reset_8390()
143 z_writeb(ENISR_RDC, nic_base + NE_EN0_ISR); /* Ack intr */ zorro8390_get_8390_hdr()
186 z_writeb(ENISR_RDC, nic_base + NE_EN0_ISR); /* Ack intr */ zorro8390_block_input()
242 z_writeb(ENISR_RDC, nic_base + NE_EN0_ISR); /* Ack intr */ zorro8390_block_output()
319 z_writeb(0xff, ioaddr + NE_EN0_ISR); /* Ack all intr. */ zorro8390_init()
/linux-4.1.27/arch/powerpc/include/asm/
H A Ddbdma.h74 #define INTR_IFSET 0x10 /* intr if condition bit is 1 */
75 #define INTR_IFCLR 0x20 /* intr if condition bit is 0 */
/linux-4.1.27/arch/arm/mach-tegra/
H A Dflowctrl.c100 reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ flowctrl_cpu_suspend_enter()
138 reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */ flowctrl_cpu_suspend_exit()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dgf100.c517 u32 intr = nv_rd32(priv, 0x00254c); gf100_fifo_intr_sched() local
518 u32 code = intr & 0x000000ff; gf100_fifo_intr_sched()
714 u32 intr = nv_rd32(priv, 0x002a00); gf100_fifo_intr_runlist() local
716 if (intr & 0x10000000) { gf100_fifo_intr_runlist()
719 intr &= ~0x10000000; gf100_fifo_intr_runlist()
722 if (intr) { gf100_fifo_intr_runlist()
723 nv_error(priv, "RUNLIST 0x%08x\n", intr); gf100_fifo_intr_runlist()
724 nv_wr32(priv, 0x002a00, intr); gf100_fifo_intr_runlist()
731 u32 intr = nv_rd32(priv, 0x0025a8 + (engn * 0x04)); gf100_fifo_intr_engine_unit() local
735 nv_wr32(priv, 0x0025a8 + (engn * 0x04), intr); gf100_fifo_intr_engine_unit()
738 u32 ints = (intr >> (unkn * 0x04)) & inte; gf100_fifo_intr_engine_unit()
769 u32 intr = nv_rd32(priv, 0x00252c); gf100_fifo_intr() local
770 nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr); gf100_fifo_intr()
782 u32 intr = nv_rd32(priv, 0x00256c); gf100_fifo_intr() local
783 nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr); gf100_fifo_intr()
789 u32 intr = nv_rd32(priv, 0x00258c); gf100_fifo_intr() local
790 nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr); gf100_fifo_intr()
897 nv_subdev(priv)->intr = gf100_fifo_intr; gf100_fifo_ctor()
/linux-4.1.27/drivers/iio/light/
H A Dtsl2563.c127 u8 intr; member in struct:tsl2563_chip
648 if (state && !(chip->intr & 0x30)) { tsl2563_write_interrupt_config()
649 chip->intr &= ~0x30; tsl2563_write_interrupt_config()
650 chip->intr |= 0x10; tsl2563_write_interrupt_config()
663 chip->intr); tsl2563_write_interrupt_config()
667 if (!state && (chip->intr & 0x30)) { tsl2563_write_interrupt_config()
668 chip->intr &= ~0x30; tsl2563_write_interrupt_config()
671 chip->intr); tsl2563_write_interrupt_config()
752 chip->intr = TSL2563_INT_PERSIST(4); tsl2563_probe()
823 chip->intr &= ~0x30; tsl2563_remove()
825 chip->intr); tsl2563_remove()
/linux-4.1.27/drivers/staging/unisys/uislib/
H A Duislib.c347 dev->intr = msg->cmd.create_device.intr; create_device()
429 cmd.add_vhba.intr = dev->intr; create_device()
446 cmd.add_vhba.intr = dev->intr; create_device()
816 struct irq_info *intr) uislib_client_inject_add_vhba()
836 if (intr) uislib_client_inject_add_vhba()
837 msg.cmd.create_device.intr = *intr; uislib_client_inject_add_vhba()
839 memset(&msg.cmd.create_device.intr, 0, uislib_client_inject_add_vhba()
871 struct irq_info *intr) uislib_client_inject_add_vnic()
891 if (intr) uislib_client_inject_add_vnic()
892 msg.cmd.create_device.intr = *intr; uislib_client_inject_add_vnic()
894 memset(&msg.cmd.create_device.intr, 0, uislib_client_inject_add_vnic()
813 uislib_client_inject_add_vhba(u32 bus_no, u32 dev_no, u64 phys_chan_addr, u32 chan_bytes, int is_test_addr, uuid_le inst_uuid, struct irq_info *intr) uislib_client_inject_add_vhba() argument
868 uislib_client_inject_add_vnic(u32 bus_no, u32 dev_no, u64 phys_chan_addr, u32 chan_bytes, int is_test_addr, uuid_le inst_uuid, struct irq_info *intr) uislib_client_inject_add_vnic() argument
/linux-4.1.27/drivers/block/rsxx/
H A Drsxx_cfg.h50 __u32 count; /* Number of intr to coalesce */
H A Dcore.c290 static void __enable_intr(unsigned int *mask, unsigned int intr) __enable_intr() argument
292 *mask |= intr; __enable_intr()
295 static void __disable_intr(unsigned int *mask, unsigned int intr) __disable_intr() argument
297 *mask &= ~intr; __disable_intr()
307 void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr) rsxx_enable_ier() argument
313 __enable_intr(&card->ier_mask, intr); rsxx_enable_ier()
317 void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr) rsxx_disable_ier() argument
322 __disable_intr(&card->ier_mask, intr); rsxx_disable_ier()
327 unsigned int intr) rsxx_enable_ier_and_isr()
333 __enable_intr(&card->isr_mask, intr); rsxx_enable_ier_and_isr()
334 __enable_intr(&card->ier_mask, intr); rsxx_enable_ier_and_isr()
338 unsigned int intr) rsxx_disable_ier_and_isr()
343 __disable_intr(&card->isr_mask, intr); rsxx_disable_ier_and_isr()
344 __disable_intr(&card->ier_mask, intr); rsxx_disable_ier_and_isr()
326 rsxx_enable_ier_and_isr(struct rsxx_cardinfo *card, unsigned int intr) rsxx_enable_ier_and_isr() argument
337 rsxx_disable_ier_and_isr(struct rsxx_cardinfo *card, unsigned int intr) rsxx_disable_ier_and_isr() argument
H A Drsxx_priv.h365 void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr);
366 void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr);
368 unsigned int intr);
370 unsigned int intr);
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dradeon_fence.c474 * @intr: use interruptable sleep
479 * @intr selects whether to use interruptable (true) or non-interruptable
487 u64 *target_seq, bool intr, radeon_fence_wait_seq_timeout()
505 if (intr) { radeon_fence_wait_seq_timeout()
533 * @intr: use interruptible sleep
536 * @intr selects whether to use interruptable (true) or non-interruptable
540 int radeon_fence_wait(struct radeon_fence *fence, bool intr) radeon_fence_wait() argument
552 return fence_wait(&fence->base, intr); radeon_fence_wait()
555 r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, MAX_SCHEDULE_TIMEOUT); radeon_fence_wait()
571 * @intr: use interruptable sleep
574 * array is indexed by ring id. @intr selects whether to use
581 bool intr) radeon_fence_wait_any()
602 r = radeon_fence_wait_seq_timeout(rdev, seq, intr, MAX_SCHEDULE_TIMEOUT); radeon_fence_wait_any()
1047 static signed long radeon_fence_default_wait(struct fence *f, bool intr, radeon_fence_default_wait() argument
1060 if (intr) radeon_fence_default_wait()
1079 if (t > 0 && intr && signal_pending(current)) radeon_fence_default_wait()
486 radeon_fence_wait_seq_timeout(struct radeon_device *rdev, u64 *target_seq, bool intr, long timeout) radeon_fence_wait_seq_timeout() argument
579 radeon_fence_wait_any(struct radeon_device *rdev, struct radeon_fence **fences, bool intr) radeon_fence_wait_any() argument
/linux-4.1.27/arch/ia64/include/asm/sn/
H A Dintr.h49 int irq_last_intr; /* For Shub lb lost intr WAR */
H A Dnodepda.h14 #include <asm/sn/intr.h>
H A Dioc3.h174 #define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */
186 #define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */
190 #define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */
H A Dsn_sal.h409 ia64_sn_console_intr_enable(u64 intr) ia64_sn_console_intr_enable() argument
418 intr, SAL_CONSOLE_INTR_ON, ia64_sn_console_intr_enable()
426 ia64_sn_console_intr_disable(u64 intr) ia64_sn_console_intr_disable() argument
435 intr, SAL_CONSOLE_INTR_OFF, ia64_sn_console_intr_disable()
873 * Enable the interrupt indicated by the intr parameter (either
877 ia64_sn_irtr_intr_enable(nasid_t nasid, int subch, u64 intr) ia64_sn_irtr_intr_enable() argument
881 (u64) nasid, (u64) subch, intr, 0, 0, 0); ia64_sn_irtr_intr_enable()
886 * Disable the interrupt indicated by the intr parameter (either
890 ia64_sn_irtr_intr_disable(nasid_t nasid, int subch, u64 intr) ia64_sn_irtr_intr_disable() argument
894 (u64) nasid, (u64) subch, intr, 0, 0, 0); ia64_sn_irtr_intr_disable()
/linux-4.1.27/arch/arc/include/asm/
H A Dstacktrace.h30 * - Asynchronous unwinding of intr/excp etc: @tsk !NULL, @regs !NULL
/linux-4.1.27/drivers/w1/masters/
H A Dds1wm.c110 /* byte to write that makes all intr disabled, */
131 u8 intr; ds1wm_isr() local
142 intr = ds1wm_read_register(ds1wm_data, DS1WM_INT); ds1wm_isr()
144 ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1; ds1wm_isr()
146 if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete) { ds1wm_isr()
150 if (intr & DS1WM_INT_RBF) { ds1wm_isr()
158 if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete) { ds1wm_isr()
/linux-4.1.27/include/linux/
H A Dfence.h153 * Must return -ERESTARTSYS if the wait is intr = true and the wait was
170 signed long (*wait)(struct fence *fence, bool intr, signed long timeout);
223 signed long fence_default_wait(struct fence *fence, bool intr, signed long timeout);
307 signed long fence_wait_timeout(struct fence *, bool intr, signed long timeout);
313 * @intr: [in] if true, do an interruptible wait
323 static inline signed long fence_wait(struct fence *fence, bool intr) fence_wait() argument
331 ret = fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT); fence_wait()
/linux-4.1.27/drivers/net/ethernet/apple/
H A Dmacmace.c535 static void mace_handle_misc_intrs(struct net_device *dev, int intr) mace_handle_misc_intrs() argument
541 if (intr & MPCO) mace_handle_misc_intrs()
544 if (intr & RNTPCO) mace_handle_misc_intrs()
547 if (intr & CERR) mace_handle_misc_intrs()
549 if (intr & BABBLE) mace_handle_misc_intrs()
552 if (intr & JABBER) mace_handle_misc_intrs()
562 int intr, fs; mace_interrupt() local
568 intr = mb->ir; /* read interrupt register */ mace_interrupt()
569 mace_handle_misc_intrs(dev, intr); mace_interrupt()
571 if (intr & XMTINT) { mace_interrupt()
H A Dmace.c638 static void mace_handle_misc_intrs(struct mace_data *mp, int intr, struct net_device *dev) mace_handle_misc_intrs() argument
643 if (intr & MPCO) mace_handle_misc_intrs()
646 if (intr & RNTPCO) mace_handle_misc_intrs()
649 if (intr & CERR) mace_handle_misc_intrs()
651 if (intr & BABBLE) mace_handle_misc_intrs()
654 if (intr & JABBER) mace_handle_misc_intrs()
666 int intr, fs, i, stat, x; mace_interrupt() local
672 intr = in_8(&mb->ir); /* read interrupt register */ mace_interrupt()
674 mace_handle_misc_intrs(mp, intr, dev); mace_interrupt()
685 intr = in_8(&mb->ir); mace_interrupt()
686 if (intr != 0) mace_interrupt()
687 mace_handle_misc_intrs(mp, intr, dev); mace_interrupt()
/linux-4.1.27/arch/mips/sgi-ip32/
H A Dip32-irq.c345 printk("CRIME intr mask: %016lx\n", crime->imask); ip32_unknown_interrupt()
346 printk("CRIME intr status: %016lx\n", crime->istat); ip32_unknown_interrupt()
347 printk("CRIME hardware intr register: %016lx\n", crime->hard_int); ip32_unknown_interrupt()
348 printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); ip32_unknown_interrupt()
349 printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); ip32_unknown_interrupt()
/linux-4.1.27/drivers/infiniband/hw/mthca/
H A Dmthca_eq.c59 u8 intr; member in struct:mthca_eq_context
467 u8 intr, mthca_create_eq()
542 eq_context->intr = intr; mthca_create_eq()
770 u8 intr; mthca_init_eq_table() local
795 intr = dev->eq_table.inta_pin; mthca_init_eq_table()
798 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 128 : intr, mthca_init_eq_table()
804 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 129 : intr, mthca_init_eq_table()
810 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 130 : intr, mthca_init_eq_table()
465 mthca_create_eq(struct mthca_dev *dev, int nent, u8 intr, struct mthca_eq *eq) mthca_create_eq() argument
/linux-4.1.27/drivers/net/ethernet/atheros/alx/
H A Dmain.c292 static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr) alx_intr_handle() argument
300 alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS); alx_intr_handle()
301 intr &= alx->int_mask; alx_intr_handle()
303 if (intr & ALX_ISR_FATAL) { alx_intr_handle()
305 "fatal interrupt 0x%x, resetting\n", intr); alx_intr_handle()
310 if (intr & ALX_ISR_ALERT) alx_intr_handle()
311 netdev_warn(alx->dev, "alert interrupt: 0x%x\n", intr); alx_intr_handle()
313 if (intr & ALX_ISR_PHY) { alx_intr_handle()
323 if (intr & (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0)) { alx_intr_handle()
351 u32 intr; alx_intr_legacy() local
353 intr = alx_read_mem32(hw, ALX_ISR); alx_intr_legacy()
355 if (intr & ALX_ISR_DIS || !(intr & alx->int_mask)) alx_intr_legacy()
358 return alx_intr_handle(alx, intr); alx_intr_legacy()
/linux-4.1.27/drivers/rtc/
H A Drtc-imxdi.c135 static void di_int_enable(struct imxdi_dev *imxdi, u32 intr) di_int_enable() argument
140 __raw_writel(__raw_readl(imxdi->ioaddr + DIER) | intr, di_int_enable()
148 static void di_int_disable(struct imxdi_dev *imxdi, u32 intr) di_int_disable() argument
153 __raw_writel(__raw_readl(imxdi->ioaddr + DIER) & ~intr, di_int_disable()
325 di_int_enable(imxdi, DIER_CAIE); /* enable alarm intr */ dryice_rtc_set_alarm()
327 di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */ dryice_rtc_set_alarm()
/linux-4.1.27/drivers/usb/misc/
H A Drio500.c284 int intr; write_rio() local
286 intr = mutex_lock_interruptible(&(rio->lock)); write_rio()
287 if (intr) write_rio()
372 int intr; read_rio() local
374 intr = mutex_lock_interruptible(&(rio->lock)); read_rio()
375 if (intr) read_rio()
/linux-4.1.27/drivers/net/ethernet/pasemi/
H A Dpasemi_mac.h44 struct pasemi_mac *mac; /* Needed in intr handler */
57 struct pasemi_mac *mac; /* Needed in intr handler */
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dnv04.c171 nv_info(priv, "PVIDEO intr: %08x\n", pvideo); nv04_disp_intr()
191 nv_subdev(priv)->intr = nv04_disp_intr; nv04_disp_ctor()
H A Dg94.c101 nv_subdev(priv)->intr = nv50_disp_intr; g94_disp_ctor()
H A Dgf110.c1203 u32 intr = nv_rd32(priv, 0x610088); gf110_disp_intr() local
1206 if (intr & 0x00000001) { gf110_disp_intr()
1213 intr &= ~0x00000001; gf110_disp_intr()
1216 if (intr & 0x00000002) { gf110_disp_intr()
1221 intr &= ~0x00000002; gf110_disp_intr()
1224 if (intr & 0x00100000) { gf110_disp_intr()
1238 intr &= ~0x00100000; gf110_disp_intr()
1243 if (mask & intr) { gf110_disp_intr()
1274 nv_subdev(priv)->intr = gf110_disp_intr; gf110_disp_ctor()
H A Dgk110.c73 nv_subdev(priv)->intr = gf110_disp_intr; gk110_disp_ctor()
H A Dgm107.c73 nv_subdev(priv)->intr = gf110_disp_intr; gm107_disp_ctor()
H A Dgm204.c74 nv_subdev(priv)->intr = gf110_disp_intr; gm204_disp_ctor()
H A Dgt200.c117 nv_subdev(priv)->intr = nv50_disp_intr; gt200_disp_ctor()
H A Dgt215.c72 nv_subdev(priv)->intr = nv50_disp_intr; gt215_disp_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sec/
H A Dg98.c106 nv_error(priv, "unhandled intr 0x%08x\n", stat); g98_sec_intr()
128 nv_subdev(priv)->intr = g98_sec_intr; g98_sec_ctor()
/linux-4.1.27/drivers/char/mwave/
H A Dmwavedd.h136 unsigned long ulIPCSource_ISR; /* IPC source bits for recently processed intr, set during ISR processing */
137 unsigned long ulIPCSource_DPC; /* IPC source bits for recently processed intr, set during DPC processing */
/linux-4.1.27/arch/m68k/coldfire/
H A Dintc-2.c33 #define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */
34 #define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv2a.c109 nv_subdev(priv)->intr = nv20_gr_intr; nv2a_gr_ctor()
H A Dnv25.c142 nv_subdev(priv)->intr = nv20_gr_intr; nv25_gr_ctor()
H A Dnv34.c143 nv_subdev(priv)->intr = nv20_gr_intr; nv34_gr_ctor()
H A Dnv35.c143 nv_subdev(priv)->intr = nv20_gr_intr; nv35_gr_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
H A Dg84.c79 nv_subdev(priv)->intr = nv50_mpeg_intr; g84_mpeg_ctor()
H A Dnv40.c118 nv_subdev(priv)->intr = nv40_mpeg_intr; nv40_mpeg_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/
H A Dgf100.c92 nv_subdev(priv)->intr = nvkm_falcon_intr; gf100_mspdec_ctor()
H A Dgk104.c92 nv_subdev(priv)->intr = nvkm_falcon_intr; gk104_mspdec_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msppp/
H A Dgf100.c92 nv_subdev(priv)->intr = nvkm_falcon_intr; gf100_msppp_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msvld/
H A Dgf100.c92 nv_subdev(priv)->intr = nvkm_falcon_intr; gf100_msvld_ctor()
H A Dgk104.c92 nv_subdev(priv)->intr = nvkm_falcon_intr; gk104_msvld_ctor()
/linux-4.1.27/arch/mips/include/asm/
H A Dtermios.h16 * intr=^C quit=^\ erase=del kill=^U
/linux-4.1.27/arch/alpha/include/asm/
H A Dtermios.h8 intr=^C quit=^\ susp=^Z <OSF/1 VDSUSP>
/linux-4.1.27/include/asm-generic/
H A Dtermios.h8 /* intr=^C quit=^\ erase=del kill=^U
/linux-4.1.27/drivers/sbus/char/
H A Ductrl.c266 int stat, incnt, outcnt, bytecnt, intr; uctrl_do_txn() local
270 intr = sbus_readl(&driver->regs->uctrl_intr); uctrl_do_txn()
273 dprintk(("interrupt stat 0x%x int 0x%x\n", stat, intr)); uctrl_do_txn()
/linux-4.1.27/arch/cris/arch-v32/kernel/
H A Dtime.c211 reg_timer_r_masked_intr intr; crisv32_timer_interrupt() local
213 intr = REG_RD(timer, timer_base, r_masked_intr); crisv32_timer_interrupt()
214 if (!intr.tmr0) crisv32_timer_interrupt()
/linux-4.1.27/drivers/thermal/
H A Dx86_pkg_temp_thermal.c227 u32 mask, shift, intr; sys_set_trip_temp() local
244 intr = THERM_INT_THRESHOLD1_ENABLE; sys_set_trip_temp()
248 intr = THERM_INT_THRESHOLD0_ENABLE; sys_set_trip_temp()
256 l &= ~intr; sys_set_trip_temp()
259 l |= intr; sys_set_trip_temp()
/linux-4.1.27/drivers/iio/accel/
H A Dbmc150-accel.c169 int intr; member in struct:bmc150_accel_trigger
504 struct bmc150_accel_interrupt *intr = &data->interrupts[i]; bmc150_accel_set_interrupt() local
505 const struct bmc150_accel_interrupt_info *info = intr->info; bmc150_accel_set_interrupt()
509 if (atomic_inc_return(&intr->users) > 1) bmc150_accel_set_interrupt()
512 if (atomic_dec_return(&intr->users) > 0) bmc150_accel_set_interrupt()
1280 ret = bmc150_accel_set_interrupt(data, t->intr, state); bmc150_accel_trigger_set_state()
1448 int intr; member in struct:__anon4754
1453 .intr = 0,
1457 .intr = 1,
1495 t->intr = bmc150_accel_triggers[i].intr; bmc150_accel_triggers_setup()
/linux-4.1.27/net/bluetooth/hidp/
H A Dcore.c434 int type, const u8 *data, int len, int intr) hidp_process_report()
440 hid_input_report(session->hid, type, session->input_buf, len, intr); hidp_process_report()
912 struct bt_sock *ctrl, *intr; hidp_session_new() local
915 intr = bt_sk(intr_sock->sk); hidp_session_new()
938 session->intr_mtu = min_t(uint, l2cap_pi(intr)->chan->omtu, hidp_session_new()
939 l2cap_pi(intr)->chan->imtu); hidp_session_new()
1203 /* parse incoming intr-skbs */ hidp_session_run()
1212 /* send pending intr-skbs */ hidp_session_run()
1296 struct bt_sock *ctrl, *intr; hidp_verify_sockets() local
1310 intr = bt_sk(intr_sock->sk); hidp_verify_sockets()
1313 intr->sk.sk_state != BT_CONNECTED) hidp_verify_sockets()
433 hidp_process_report(struct hidp_session *session, int type, const u8 *data, int len, int intr) hidp_process_report() argument
/linux-4.1.27/arch/arc/kernel/
H A Dentry.S193 ;Which mode (user/kernel) was the system in when intr occured
244 ;Which mode (user/kernel) was the system in when intr occured
619 ; !CONFIG_PREEMPT: To ensure restore_regs is intr safe
673 ; However the context returning might not have taken L2 intr itself
674 ; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
675 ; Special considerations needed for the context which took L2 intr
677 ld r9, [sp, PT_event] ; Ensure this is L2 intr context
/linux-4.1.27/drivers/sn/
H A Dioc3.c414 ioc3_ethernet->intr) { ioc3_intr_io()
415 handled = handled && !ioc3_ethernet->intr(ioc3_ethernet, ioc3_intr_io()
424 && ioc3_submodules[id]->intr) { ioc3_intr_io()
427 if(!ioc3_submodules[id]->intr(ioc3_submodules[id], ioc3_intr_io()
455 && ioc3_ethernet->intr) ioc3_intr_eth()
456 handled = handled && !ioc3_ethernet->intr(ioc3_ethernet, idd, 0); ioc3_intr_eth()
/linux-4.1.27/drivers/tty/serial/
H A Dpnx8xxx_uart.c133 /* Disable TX intr */ pnx8xxx_stop_tx()
137 /* Clear all pending TX intr */ pnx8xxx_stop_tx()
150 /* Clear all pending TX intr */ pnx8xxx_start_tx()
153 /* Enable TX intr */ pnx8xxx_start_tx()
167 /* Disable RX intr */ pnx8xxx_stop_rx()
171 /* Clear all pending RX intr */ pnx8xxx_stop_rx()
/linux-4.1.27/drivers/watchdog/
H A Dpcwd_usb.c128 /* the buffer to intr data */
130 /* the dma address for the intr buffer */
132 /* the size of the intr buffer */
134 /* the urb used for the intr pipe */
208 pr_err("can't resubmit intr, usb_submit_urb failed with result %d\n", usb_pcwd_intr_done()
675 /* initialise the intr urb's */ usb_pcwd_probe()
/linux-4.1.27/drivers/spi/
H A Dspi-bcm63xx.c303 u8 intr; bcm63xx_spi_interrupt() local
306 intr = bcm_spi_readb(bs, SPI_INT_STATUS); bcm63xx_spi_interrupt()
311 if (intr & SPI_INTR_CMD_DONE) bcm63xx_spi_interrupt()
/linux-4.1.27/drivers/staging/unisys/include/
H A Duisqueue.h134 struct irq_info intr; member in struct:device_info
215 struct irq_info intr; /* contains recv & send member in struct:add_virt_iopart
347 struct irq_info intr; /* recv/send interrupt info */ member in struct:add_virt_guestpart
/linux-4.1.27/drivers/net/slip/
H A Dslip.h54 struct net_device *dev; /* easy for intr handling */
/linux-4.1.27/drivers/staging/unisys/virtpci/
H A Dvirtpci.h63 struct irq_info intr; /* interrupt info */ member in struct:virtpci_dev
/linux-4.1.27/drivers/net/wireless/ti/wl12xx/
H A Dwl12xx.h131 __le32 intr; member in struct:wl12xx_fw_status
/linux-4.1.27/drivers/net/wireless/ti/wlcore/
H A Dboot.c440 u32 chip_id, intr; wlcore_boot_run_firmware() local
466 ret = wlcore_read_reg(wl, REG_INTERRUPT_NO_CLEAR, &intr); wlcore_boot_run_firmware()
470 if (intr == 0xffffffff) { wlcore_boot_run_firmware()
476 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) { wlcore_boot_run_firmware()
/linux-4.1.27/arch/x86/kernel/cpu/
H A Dintel_pt.h59 u64 intr : 1; member in struct:topa_entry
/linux-4.1.27/arch/x86/kvm/
H A Dirq.h68 int output; /* intr from master PIC */
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dsubdev.h17 void (*intr)(struct nvkm_subdev *); member in struct:nvkm_subdev
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sw/
H A Dnv04.c126 nv_subdev(priv)->intr = nv04_sw_intr; nv04_sw_ctor()
H A Dnv10.c109 nv_subdev(priv)->intr = nv04_sw_intr; nv10_sw_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
H A Dgf100.c109 nv_subdev(priv)->intr = gf100_ibus_intr; gf100_ibus_ctor()
H A Dgk20a.c89 nv_subdev(priv)->intr = gk20a_ibus_intr; gk20a_ibus_ctor()

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