1/* 2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. 3 * All rights reserved 4 * www.brocade.com 5 * 6 * Linux driver for Brocade Fibre Channel Host Bus Adapter. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License (GPL) Version 2 as 10 * published by the Free Software Foundation 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 */ 17 18#include "bfad_drv.h" 19#include "bfa_modules.h" 20#include "bfi_reg.h" 21 22BFA_TRC_FILE(HAL, CORE); 23 24/* 25 * BFA module list terminated by NULL 26 */ 27static struct bfa_module_s *hal_mods[] = { 28 &hal_mod_fcdiag, 29 &hal_mod_sgpg, 30 &hal_mod_fcport, 31 &hal_mod_fcxp, 32 &hal_mod_lps, 33 &hal_mod_uf, 34 &hal_mod_rport, 35 &hal_mod_fcp, 36 &hal_mod_dconf, 37 NULL 38}; 39 40/* 41 * Message handlers for various modules. 42 */ 43static bfa_isr_func_t bfa_isrs[BFI_MC_MAX] = { 44 bfa_isr_unhandled, /* NONE */ 45 bfa_isr_unhandled, /* BFI_MC_IOC */ 46 bfa_fcdiag_intr, /* BFI_MC_DIAG */ 47 bfa_isr_unhandled, /* BFI_MC_FLASH */ 48 bfa_isr_unhandled, /* BFI_MC_CEE */ 49 bfa_fcport_isr, /* BFI_MC_FCPORT */ 50 bfa_isr_unhandled, /* BFI_MC_IOCFC */ 51 bfa_isr_unhandled, /* BFI_MC_LL */ 52 bfa_uf_isr, /* BFI_MC_UF */ 53 bfa_fcxp_isr, /* BFI_MC_FCXP */ 54 bfa_lps_isr, /* BFI_MC_LPS */ 55 bfa_rport_isr, /* BFI_MC_RPORT */ 56 bfa_itn_isr, /* BFI_MC_ITN */ 57 bfa_isr_unhandled, /* BFI_MC_IOIM_READ */ 58 bfa_isr_unhandled, /* BFI_MC_IOIM_WRITE */ 59 bfa_isr_unhandled, /* BFI_MC_IOIM_IO */ 60 bfa_ioim_isr, /* BFI_MC_IOIM */ 61 bfa_ioim_good_comp_isr, /* BFI_MC_IOIM_IOCOM */ 62 bfa_tskim_isr, /* BFI_MC_TSKIM */ 63 bfa_isr_unhandled, /* BFI_MC_SBOOT */ 64 bfa_isr_unhandled, /* BFI_MC_IPFC */ 65 bfa_isr_unhandled, /* BFI_MC_PORT */ 66 bfa_isr_unhandled, /* --------- */ 67 bfa_isr_unhandled, /* --------- */ 68 bfa_isr_unhandled, /* --------- */ 69 bfa_isr_unhandled, /* --------- */ 70 bfa_isr_unhandled, /* --------- */ 71 bfa_isr_unhandled, /* --------- */ 72 bfa_isr_unhandled, /* --------- */ 73 bfa_isr_unhandled, /* --------- */ 74 bfa_isr_unhandled, /* --------- */ 75 bfa_isr_unhandled, /* --------- */ 76}; 77/* 78 * Message handlers for mailbox command classes 79 */ 80static bfa_ioc_mbox_mcfunc_t bfa_mbox_isrs[BFI_MC_MAX] = { 81 NULL, 82 NULL, /* BFI_MC_IOC */ 83 NULL, /* BFI_MC_DIAG */ 84 NULL, /* BFI_MC_FLASH */ 85 NULL, /* BFI_MC_CEE */ 86 NULL, /* BFI_MC_PORT */ 87 bfa_iocfc_isr, /* BFI_MC_IOCFC */ 88 NULL, 89}; 90 91 92 93static void 94bfa_com_port_attach(struct bfa_s *bfa) 95{ 96 struct bfa_port_s *port = &bfa->modules.port; 97 struct bfa_mem_dma_s *port_dma = BFA_MEM_PORT_DMA(bfa); 98 99 bfa_port_attach(port, &bfa->ioc, bfa, bfa->trcmod); 100 bfa_port_mem_claim(port, port_dma->kva_curp, port_dma->dma_curp); 101} 102 103/* 104 * ablk module attach 105 */ 106static void 107bfa_com_ablk_attach(struct bfa_s *bfa) 108{ 109 struct bfa_ablk_s *ablk = &bfa->modules.ablk; 110 struct bfa_mem_dma_s *ablk_dma = BFA_MEM_ABLK_DMA(bfa); 111 112 bfa_ablk_attach(ablk, &bfa->ioc); 113 bfa_ablk_memclaim(ablk, ablk_dma->kva_curp, ablk_dma->dma_curp); 114} 115 116static void 117bfa_com_cee_attach(struct bfa_s *bfa) 118{ 119 struct bfa_cee_s *cee = &bfa->modules.cee; 120 struct bfa_mem_dma_s *cee_dma = BFA_MEM_CEE_DMA(bfa); 121 122 cee->trcmod = bfa->trcmod; 123 bfa_cee_attach(cee, &bfa->ioc, bfa); 124 bfa_cee_mem_claim(cee, cee_dma->kva_curp, cee_dma->dma_curp); 125} 126 127static void 128bfa_com_sfp_attach(struct bfa_s *bfa) 129{ 130 struct bfa_sfp_s *sfp = BFA_SFP_MOD(bfa); 131 struct bfa_mem_dma_s *sfp_dma = BFA_MEM_SFP_DMA(bfa); 132 133 bfa_sfp_attach(sfp, &bfa->ioc, bfa, bfa->trcmod); 134 bfa_sfp_memclaim(sfp, sfp_dma->kva_curp, sfp_dma->dma_curp); 135} 136 137static void 138bfa_com_flash_attach(struct bfa_s *bfa, bfa_boolean_t mincfg) 139{ 140 struct bfa_flash_s *flash = BFA_FLASH(bfa); 141 struct bfa_mem_dma_s *flash_dma = BFA_MEM_FLASH_DMA(bfa); 142 143 bfa_flash_attach(flash, &bfa->ioc, bfa, bfa->trcmod, mincfg); 144 bfa_flash_memclaim(flash, flash_dma->kva_curp, 145 flash_dma->dma_curp, mincfg); 146} 147 148static void 149bfa_com_diag_attach(struct bfa_s *bfa) 150{ 151 struct bfa_diag_s *diag = BFA_DIAG_MOD(bfa); 152 struct bfa_mem_dma_s *diag_dma = BFA_MEM_DIAG_DMA(bfa); 153 154 bfa_diag_attach(diag, &bfa->ioc, bfa, bfa_fcport_beacon, bfa->trcmod); 155 bfa_diag_memclaim(diag, diag_dma->kva_curp, diag_dma->dma_curp); 156} 157 158static void 159bfa_com_phy_attach(struct bfa_s *bfa, bfa_boolean_t mincfg) 160{ 161 struct bfa_phy_s *phy = BFA_PHY(bfa); 162 struct bfa_mem_dma_s *phy_dma = BFA_MEM_PHY_DMA(bfa); 163 164 bfa_phy_attach(phy, &bfa->ioc, bfa, bfa->trcmod, mincfg); 165 bfa_phy_memclaim(phy, phy_dma->kva_curp, phy_dma->dma_curp, mincfg); 166} 167 168static void 169bfa_com_fru_attach(struct bfa_s *bfa, bfa_boolean_t mincfg) 170{ 171 struct bfa_fru_s *fru = BFA_FRU(bfa); 172 struct bfa_mem_dma_s *fru_dma = BFA_MEM_FRU_DMA(bfa); 173 174 bfa_fru_attach(fru, &bfa->ioc, bfa, bfa->trcmod, mincfg); 175 bfa_fru_memclaim(fru, fru_dma->kva_curp, fru_dma->dma_curp, mincfg); 176} 177 178/* 179 * BFA IOC FC related definitions 180 */ 181 182/* 183 * IOC local definitions 184 */ 185#define BFA_IOCFC_TOV 5000 /* msecs */ 186 187enum { 188 BFA_IOCFC_ACT_NONE = 0, 189 BFA_IOCFC_ACT_INIT = 1, 190 BFA_IOCFC_ACT_STOP = 2, 191 BFA_IOCFC_ACT_DISABLE = 3, 192 BFA_IOCFC_ACT_ENABLE = 4, 193}; 194 195#define DEF_CFG_NUM_FABRICS 1 196#define DEF_CFG_NUM_LPORTS 256 197#define DEF_CFG_NUM_CQS 4 198#define DEF_CFG_NUM_IOIM_REQS (BFA_IOIM_MAX) 199#define DEF_CFG_NUM_TSKIM_REQS 128 200#define DEF_CFG_NUM_FCXP_REQS 64 201#define DEF_CFG_NUM_UF_BUFS 64 202#define DEF_CFG_NUM_RPORTS 1024 203#define DEF_CFG_NUM_ITNIMS (DEF_CFG_NUM_RPORTS) 204#define DEF_CFG_NUM_TINS 256 205 206#define DEF_CFG_NUM_SGPGS 2048 207#define DEF_CFG_NUM_REQQ_ELEMS 256 208#define DEF_CFG_NUM_RSPQ_ELEMS 64 209#define DEF_CFG_NUM_SBOOT_TGTS 16 210#define DEF_CFG_NUM_SBOOT_LUNS 16 211 212/* 213 * IOCFC state machine definitions/declarations 214 */ 215bfa_fsm_state_decl(bfa_iocfc, stopped, struct bfa_iocfc_s, enum iocfc_event); 216bfa_fsm_state_decl(bfa_iocfc, initing, struct bfa_iocfc_s, enum iocfc_event); 217bfa_fsm_state_decl(bfa_iocfc, dconf_read, struct bfa_iocfc_s, enum iocfc_event); 218bfa_fsm_state_decl(bfa_iocfc, init_cfg_wait, 219 struct bfa_iocfc_s, enum iocfc_event); 220bfa_fsm_state_decl(bfa_iocfc, init_cfg_done, 221 struct bfa_iocfc_s, enum iocfc_event); 222bfa_fsm_state_decl(bfa_iocfc, operational, 223 struct bfa_iocfc_s, enum iocfc_event); 224bfa_fsm_state_decl(bfa_iocfc, dconf_write, 225 struct bfa_iocfc_s, enum iocfc_event); 226bfa_fsm_state_decl(bfa_iocfc, stopping, struct bfa_iocfc_s, enum iocfc_event); 227bfa_fsm_state_decl(bfa_iocfc, enabling, struct bfa_iocfc_s, enum iocfc_event); 228bfa_fsm_state_decl(bfa_iocfc, cfg_wait, struct bfa_iocfc_s, enum iocfc_event); 229bfa_fsm_state_decl(bfa_iocfc, disabling, struct bfa_iocfc_s, enum iocfc_event); 230bfa_fsm_state_decl(bfa_iocfc, disabled, struct bfa_iocfc_s, enum iocfc_event); 231bfa_fsm_state_decl(bfa_iocfc, failed, struct bfa_iocfc_s, enum iocfc_event); 232bfa_fsm_state_decl(bfa_iocfc, init_failed, 233 struct bfa_iocfc_s, enum iocfc_event); 234 235/* 236 * forward declaration for IOC FC functions 237 */ 238static void bfa_iocfc_start_submod(struct bfa_s *bfa); 239static void bfa_iocfc_disable_submod(struct bfa_s *bfa); 240static void bfa_iocfc_send_cfg(void *bfa_arg); 241static void bfa_iocfc_enable_cbfn(void *bfa_arg, enum bfa_status status); 242static void bfa_iocfc_disable_cbfn(void *bfa_arg); 243static void bfa_iocfc_hbfail_cbfn(void *bfa_arg); 244static void bfa_iocfc_reset_cbfn(void *bfa_arg); 245static struct bfa_ioc_cbfn_s bfa_iocfc_cbfn; 246static void bfa_iocfc_init_cb(void *bfa_arg, bfa_boolean_t complete); 247static void bfa_iocfc_stop_cb(void *bfa_arg, bfa_boolean_t compl); 248static void bfa_iocfc_enable_cb(void *bfa_arg, bfa_boolean_t compl); 249static void bfa_iocfc_disable_cb(void *bfa_arg, bfa_boolean_t compl); 250 251static void 252bfa_iocfc_sm_stopped_entry(struct bfa_iocfc_s *iocfc) 253{ 254} 255 256static void 257bfa_iocfc_sm_stopped(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 258{ 259 bfa_trc(iocfc->bfa, event); 260 261 switch (event) { 262 case IOCFC_E_INIT: 263 case IOCFC_E_ENABLE: 264 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_initing); 265 break; 266 default: 267 bfa_sm_fault(iocfc->bfa, event); 268 break; 269 } 270} 271 272static void 273bfa_iocfc_sm_initing_entry(struct bfa_iocfc_s *iocfc) 274{ 275 bfa_ioc_enable(&iocfc->bfa->ioc); 276} 277 278static void 279bfa_iocfc_sm_initing(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 280{ 281 bfa_trc(iocfc->bfa, event); 282 283 switch (event) { 284 case IOCFC_E_IOC_ENABLED: 285 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_read); 286 break; 287 288 case IOCFC_E_DISABLE: 289 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 290 break; 291 292 case IOCFC_E_STOP: 293 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping); 294 break; 295 296 case IOCFC_E_IOC_FAILED: 297 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_failed); 298 break; 299 default: 300 bfa_sm_fault(iocfc->bfa, event); 301 break; 302 } 303} 304 305static void 306bfa_iocfc_sm_dconf_read_entry(struct bfa_iocfc_s *iocfc) 307{ 308 bfa_dconf_modinit(iocfc->bfa); 309} 310 311static void 312bfa_iocfc_sm_dconf_read(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 313{ 314 bfa_trc(iocfc->bfa, event); 315 316 switch (event) { 317 case IOCFC_E_DCONF_DONE: 318 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_cfg_wait); 319 break; 320 321 case IOCFC_E_DISABLE: 322 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 323 break; 324 325 case IOCFC_E_STOP: 326 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping); 327 break; 328 329 case IOCFC_E_IOC_FAILED: 330 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_failed); 331 break; 332 default: 333 bfa_sm_fault(iocfc->bfa, event); 334 break; 335 } 336} 337 338static void 339bfa_iocfc_sm_init_cfg_wait_entry(struct bfa_iocfc_s *iocfc) 340{ 341 bfa_iocfc_send_cfg(iocfc->bfa); 342} 343 344static void 345bfa_iocfc_sm_init_cfg_wait(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 346{ 347 bfa_trc(iocfc->bfa, event); 348 349 switch (event) { 350 case IOCFC_E_CFG_DONE: 351 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_cfg_done); 352 break; 353 354 case IOCFC_E_DISABLE: 355 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 356 break; 357 358 case IOCFC_E_STOP: 359 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping); 360 break; 361 362 case IOCFC_E_IOC_FAILED: 363 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_failed); 364 break; 365 default: 366 bfa_sm_fault(iocfc->bfa, event); 367 break; 368 } 369} 370 371static void 372bfa_iocfc_sm_init_cfg_done_entry(struct bfa_iocfc_s *iocfc) 373{ 374 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK; 375 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.init_hcb_qe, 376 bfa_iocfc_init_cb, iocfc->bfa); 377} 378 379static void 380bfa_iocfc_sm_init_cfg_done(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 381{ 382 bfa_trc(iocfc->bfa, event); 383 384 switch (event) { 385 case IOCFC_E_START: 386 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_operational); 387 break; 388 case IOCFC_E_STOP: 389 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping); 390 break; 391 case IOCFC_E_DISABLE: 392 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 393 break; 394 case IOCFC_E_IOC_FAILED: 395 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed); 396 break; 397 default: 398 bfa_sm_fault(iocfc->bfa, event); 399 break; 400 } 401} 402 403static void 404bfa_iocfc_sm_operational_entry(struct bfa_iocfc_s *iocfc) 405{ 406 bfa_fcport_init(iocfc->bfa); 407 bfa_iocfc_start_submod(iocfc->bfa); 408} 409 410static void 411bfa_iocfc_sm_operational(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 412{ 413 bfa_trc(iocfc->bfa, event); 414 415 switch (event) { 416 case IOCFC_E_STOP: 417 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write); 418 break; 419 case IOCFC_E_DISABLE: 420 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 421 break; 422 case IOCFC_E_IOC_FAILED: 423 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed); 424 break; 425 default: 426 bfa_sm_fault(iocfc->bfa, event); 427 break; 428 } 429} 430 431static void 432bfa_iocfc_sm_dconf_write_entry(struct bfa_iocfc_s *iocfc) 433{ 434 bfa_dconf_modexit(iocfc->bfa); 435} 436 437static void 438bfa_iocfc_sm_dconf_write(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 439{ 440 bfa_trc(iocfc->bfa, event); 441 442 switch (event) { 443 case IOCFC_E_DCONF_DONE: 444 case IOCFC_E_IOC_FAILED: 445 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping); 446 break; 447 default: 448 bfa_sm_fault(iocfc->bfa, event); 449 break; 450 } 451} 452 453static void 454bfa_iocfc_sm_stopping_entry(struct bfa_iocfc_s *iocfc) 455{ 456 bfa_ioc_disable(&iocfc->bfa->ioc); 457} 458 459static void 460bfa_iocfc_sm_stopping(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 461{ 462 bfa_trc(iocfc->bfa, event); 463 464 switch (event) { 465 case IOCFC_E_IOC_DISABLED: 466 bfa_isr_disable(iocfc->bfa); 467 bfa_iocfc_disable_submod(iocfc->bfa); 468 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopped); 469 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK; 470 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.stop_hcb_qe, 471 bfa_iocfc_stop_cb, iocfc->bfa); 472 break; 473 474 case IOCFC_E_IOC_ENABLED: 475 case IOCFC_E_DCONF_DONE: 476 case IOCFC_E_CFG_DONE: 477 break; 478 479 default: 480 bfa_sm_fault(iocfc->bfa, event); 481 break; 482 } 483} 484 485static void 486bfa_iocfc_sm_enabling_entry(struct bfa_iocfc_s *iocfc) 487{ 488 bfa_ioc_enable(&iocfc->bfa->ioc); 489} 490 491static void 492bfa_iocfc_sm_enabling(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 493{ 494 bfa_trc(iocfc->bfa, event); 495 496 switch (event) { 497 case IOCFC_E_IOC_ENABLED: 498 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_cfg_wait); 499 break; 500 501 case IOCFC_E_DISABLE: 502 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 503 break; 504 505 case IOCFC_E_STOP: 506 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write); 507 break; 508 509 case IOCFC_E_IOC_FAILED: 510 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed); 511 512 if (iocfc->bfa->iocfc.cb_reqd == BFA_FALSE) 513 break; 514 515 iocfc->bfa->iocfc.op_status = BFA_STATUS_FAILED; 516 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.en_hcb_qe, 517 bfa_iocfc_enable_cb, iocfc->bfa); 518 iocfc->bfa->iocfc.cb_reqd = BFA_FALSE; 519 break; 520 default: 521 bfa_sm_fault(iocfc->bfa, event); 522 break; 523 } 524} 525 526static void 527bfa_iocfc_sm_cfg_wait_entry(struct bfa_iocfc_s *iocfc) 528{ 529 bfa_iocfc_send_cfg(iocfc->bfa); 530} 531 532static void 533bfa_iocfc_sm_cfg_wait(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 534{ 535 bfa_trc(iocfc->bfa, event); 536 537 switch (event) { 538 case IOCFC_E_CFG_DONE: 539 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_operational); 540 if (iocfc->bfa->iocfc.cb_reqd == BFA_FALSE) 541 break; 542 543 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK; 544 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.en_hcb_qe, 545 bfa_iocfc_enable_cb, iocfc->bfa); 546 iocfc->bfa->iocfc.cb_reqd = BFA_FALSE; 547 break; 548 case IOCFC_E_DISABLE: 549 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 550 break; 551 552 case IOCFC_E_STOP: 553 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write); 554 break; 555 case IOCFC_E_IOC_FAILED: 556 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed); 557 if (iocfc->bfa->iocfc.cb_reqd == BFA_FALSE) 558 break; 559 560 iocfc->bfa->iocfc.op_status = BFA_STATUS_FAILED; 561 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.en_hcb_qe, 562 bfa_iocfc_enable_cb, iocfc->bfa); 563 iocfc->bfa->iocfc.cb_reqd = BFA_FALSE; 564 break; 565 default: 566 bfa_sm_fault(iocfc->bfa, event); 567 break; 568 } 569} 570 571static void 572bfa_iocfc_sm_disabling_entry(struct bfa_iocfc_s *iocfc) 573{ 574 bfa_ioc_disable(&iocfc->bfa->ioc); 575} 576 577static void 578bfa_iocfc_sm_disabling(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 579{ 580 bfa_trc(iocfc->bfa, event); 581 582 switch (event) { 583 case IOCFC_E_IOC_DISABLED: 584 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabled); 585 break; 586 case IOCFC_E_IOC_ENABLED: 587 case IOCFC_E_DCONF_DONE: 588 case IOCFC_E_CFG_DONE: 589 break; 590 default: 591 bfa_sm_fault(iocfc->bfa, event); 592 break; 593 } 594} 595 596static void 597bfa_iocfc_sm_disabled_entry(struct bfa_iocfc_s *iocfc) 598{ 599 bfa_isr_disable(iocfc->bfa); 600 bfa_iocfc_disable_submod(iocfc->bfa); 601 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK; 602 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.dis_hcb_qe, 603 bfa_iocfc_disable_cb, iocfc->bfa); 604} 605 606static void 607bfa_iocfc_sm_disabled(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 608{ 609 bfa_trc(iocfc->bfa, event); 610 611 switch (event) { 612 case IOCFC_E_STOP: 613 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write); 614 break; 615 case IOCFC_E_ENABLE: 616 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_enabling); 617 break; 618 default: 619 bfa_sm_fault(iocfc->bfa, event); 620 break; 621 } 622} 623 624static void 625bfa_iocfc_sm_failed_entry(struct bfa_iocfc_s *iocfc) 626{ 627 bfa_isr_disable(iocfc->bfa); 628 bfa_iocfc_disable_submod(iocfc->bfa); 629} 630 631static void 632bfa_iocfc_sm_failed(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 633{ 634 bfa_trc(iocfc->bfa, event); 635 636 switch (event) { 637 case IOCFC_E_STOP: 638 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write); 639 break; 640 case IOCFC_E_DISABLE: 641 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 642 break; 643 case IOCFC_E_IOC_ENABLED: 644 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_cfg_wait); 645 break; 646 case IOCFC_E_IOC_FAILED: 647 break; 648 default: 649 bfa_sm_fault(iocfc->bfa, event); 650 break; 651 } 652} 653 654static void 655bfa_iocfc_sm_init_failed_entry(struct bfa_iocfc_s *iocfc) 656{ 657 bfa_isr_disable(iocfc->bfa); 658 iocfc->bfa->iocfc.op_status = BFA_STATUS_FAILED; 659 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.init_hcb_qe, 660 bfa_iocfc_init_cb, iocfc->bfa); 661} 662 663static void 664bfa_iocfc_sm_init_failed(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 665{ 666 bfa_trc(iocfc->bfa, event); 667 668 switch (event) { 669 case IOCFC_E_STOP: 670 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping); 671 break; 672 case IOCFC_E_DISABLE: 673 bfa_ioc_disable(&iocfc->bfa->ioc); 674 break; 675 case IOCFC_E_IOC_ENABLED: 676 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_read); 677 break; 678 case IOCFC_E_IOC_DISABLED: 679 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopped); 680 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK; 681 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.dis_hcb_qe, 682 bfa_iocfc_disable_cb, iocfc->bfa); 683 break; 684 case IOCFC_E_IOC_FAILED: 685 break; 686 default: 687 bfa_sm_fault(iocfc->bfa, event); 688 break; 689 } 690} 691 692/* 693 * BFA Interrupt handling functions 694 */ 695static void 696bfa_reqq_resume(struct bfa_s *bfa, int qid) 697{ 698 struct list_head *waitq, *qe, *qen; 699 struct bfa_reqq_wait_s *wqe; 700 701 waitq = bfa_reqq(bfa, qid); 702 list_for_each_safe(qe, qen, waitq) { 703 /* 704 * Callback only as long as there is room in request queue 705 */ 706 if (bfa_reqq_full(bfa, qid)) 707 break; 708 709 list_del(qe); 710 wqe = (struct bfa_reqq_wait_s *) qe; 711 wqe->qresume(wqe->cbarg); 712 } 713} 714 715bfa_boolean_t 716bfa_isr_rspq(struct bfa_s *bfa, int qid) 717{ 718 struct bfi_msg_s *m; 719 u32 pi, ci; 720 struct list_head *waitq; 721 bfa_boolean_t ret; 722 723 ci = bfa_rspq_ci(bfa, qid); 724 pi = bfa_rspq_pi(bfa, qid); 725 726 ret = (ci != pi); 727 728 while (ci != pi) { 729 m = bfa_rspq_elem(bfa, qid, ci); 730 WARN_ON(m->mhdr.msg_class >= BFI_MC_MAX); 731 732 bfa_isrs[m->mhdr.msg_class] (bfa, m); 733 CQ_INCR(ci, bfa->iocfc.cfg.drvcfg.num_rspq_elems); 734 } 735 736 /* 737 * acknowledge RME completions and update CI 738 */ 739 bfa_isr_rspq_ack(bfa, qid, ci); 740 741 /* 742 * Resume any pending requests in the corresponding reqq. 743 */ 744 waitq = bfa_reqq(bfa, qid); 745 if (!list_empty(waitq)) 746 bfa_reqq_resume(bfa, qid); 747 748 return ret; 749} 750 751static inline void 752bfa_isr_reqq(struct bfa_s *bfa, int qid) 753{ 754 struct list_head *waitq; 755 756 bfa_isr_reqq_ack(bfa, qid); 757 758 /* 759 * Resume any pending requests in the corresponding reqq. 760 */ 761 waitq = bfa_reqq(bfa, qid); 762 if (!list_empty(waitq)) 763 bfa_reqq_resume(bfa, qid); 764} 765 766void 767bfa_msix_all(struct bfa_s *bfa, int vec) 768{ 769 u32 intr, qintr; 770 int queue; 771 772 intr = readl(bfa->iocfc.bfa_regs.intr_status); 773 if (!intr) 774 return; 775 776 /* 777 * RME completion queue interrupt 778 */ 779 qintr = intr & __HFN_INT_RME_MASK; 780 if (qintr && bfa->queue_process) { 781 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++) 782 bfa_isr_rspq(bfa, queue); 783 } 784 785 intr &= ~qintr; 786 if (!intr) 787 return; 788 789 /* 790 * CPE completion queue interrupt 791 */ 792 qintr = intr & __HFN_INT_CPE_MASK; 793 if (qintr && bfa->queue_process) { 794 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++) 795 bfa_isr_reqq(bfa, queue); 796 } 797 intr &= ~qintr; 798 if (!intr) 799 return; 800 801 bfa_msix_lpu_err(bfa, intr); 802} 803 804bfa_boolean_t 805bfa_intx(struct bfa_s *bfa) 806{ 807 u32 intr, qintr; 808 int queue; 809 bfa_boolean_t rspq_comp = BFA_FALSE; 810 811 intr = readl(bfa->iocfc.bfa_regs.intr_status); 812 813 qintr = intr & (__HFN_INT_RME_MASK | __HFN_INT_CPE_MASK); 814 if (qintr) 815 writel(qintr, bfa->iocfc.bfa_regs.intr_status); 816 817 /* 818 * Unconditional RME completion queue interrupt 819 */ 820 if (bfa->queue_process) { 821 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++) 822 if (bfa_isr_rspq(bfa, queue)) 823 rspq_comp = BFA_TRUE; 824 } 825 826 if (!intr) 827 return (qintr | rspq_comp) ? BFA_TRUE : BFA_FALSE; 828 829 /* 830 * CPE completion queue interrupt 831 */ 832 qintr = intr & __HFN_INT_CPE_MASK; 833 if (qintr && bfa->queue_process) { 834 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++) 835 bfa_isr_reqq(bfa, queue); 836 } 837 intr &= ~qintr; 838 if (!intr) 839 return BFA_TRUE; 840 841 if (bfa->intr_enabled) 842 bfa_msix_lpu_err(bfa, intr); 843 844 return BFA_TRUE; 845} 846 847void 848bfa_isr_enable(struct bfa_s *bfa) 849{ 850 u32 umsk; 851 int port_id = bfa_ioc_portid(&bfa->ioc); 852 853 bfa_trc(bfa, bfa_ioc_pcifn(&bfa->ioc)); 854 bfa_trc(bfa, port_id); 855 856 bfa_msix_ctrl_install(bfa); 857 858 if (bfa_asic_id_ct2(bfa->ioc.pcidev.device_id)) { 859 umsk = __HFN_INT_ERR_MASK_CT2; 860 umsk |= port_id == 0 ? 861 __HFN_INT_FN0_MASK_CT2 : __HFN_INT_FN1_MASK_CT2; 862 } else { 863 umsk = __HFN_INT_ERR_MASK; 864 umsk |= port_id == 0 ? __HFN_INT_FN0_MASK : __HFN_INT_FN1_MASK; 865 } 866 867 writel(umsk, bfa->iocfc.bfa_regs.intr_status); 868 writel(~umsk, bfa->iocfc.bfa_regs.intr_mask); 869 bfa->iocfc.intr_mask = ~umsk; 870 bfa_isr_mode_set(bfa, bfa->msix.nvecs != 0); 871 872 /* 873 * Set the flag indicating successful enabling of interrupts 874 */ 875 bfa->intr_enabled = BFA_TRUE; 876} 877 878void 879bfa_isr_disable(struct bfa_s *bfa) 880{ 881 bfa->intr_enabled = BFA_FALSE; 882 bfa_isr_mode_set(bfa, BFA_FALSE); 883 writel(-1L, bfa->iocfc.bfa_regs.intr_mask); 884 bfa_msix_uninstall(bfa); 885} 886 887void 888bfa_msix_reqq(struct bfa_s *bfa, int vec) 889{ 890 bfa_isr_reqq(bfa, vec - bfa->iocfc.hwif.cpe_vec_q0); 891} 892 893void 894bfa_isr_unhandled(struct bfa_s *bfa, struct bfi_msg_s *m) 895{ 896 bfa_trc(bfa, m->mhdr.msg_class); 897 bfa_trc(bfa, m->mhdr.msg_id); 898 bfa_trc(bfa, m->mhdr.mtag.i2htok); 899 WARN_ON(1); 900 bfa_trc_stop(bfa->trcmod); 901} 902 903void 904bfa_msix_rspq(struct bfa_s *bfa, int vec) 905{ 906 bfa_isr_rspq(bfa, vec - bfa->iocfc.hwif.rme_vec_q0); 907} 908 909void 910bfa_msix_lpu_err(struct bfa_s *bfa, int vec) 911{ 912 u32 intr, curr_value; 913 bfa_boolean_t lpu_isr, halt_isr, pss_isr; 914 915 intr = readl(bfa->iocfc.bfa_regs.intr_status); 916 917 if (bfa_asic_id_ct2(bfa->ioc.pcidev.device_id)) { 918 halt_isr = intr & __HFN_INT_CPQ_HALT_CT2; 919 pss_isr = intr & __HFN_INT_ERR_PSS_CT2; 920 lpu_isr = intr & (__HFN_INT_MBOX_LPU0_CT2 | 921 __HFN_INT_MBOX_LPU1_CT2); 922 intr &= __HFN_INT_ERR_MASK_CT2; 923 } else { 924 halt_isr = bfa_asic_id_ct(bfa->ioc.pcidev.device_id) ? 925 (intr & __HFN_INT_LL_HALT) : 0; 926 pss_isr = intr & __HFN_INT_ERR_PSS; 927 lpu_isr = intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1); 928 intr &= __HFN_INT_ERR_MASK; 929 } 930 931 if (lpu_isr) 932 bfa_ioc_mbox_isr(&bfa->ioc); 933 934 if (intr) { 935 if (halt_isr) { 936 /* 937 * If LL_HALT bit is set then FW Init Halt LL Port 938 * Register needs to be cleared as well so Interrupt 939 * Status Register will be cleared. 940 */ 941 curr_value = readl(bfa->ioc.ioc_regs.ll_halt); 942 curr_value &= ~__FW_INIT_HALT_P; 943 writel(curr_value, bfa->ioc.ioc_regs.ll_halt); 944 } 945 946 if (pss_isr) { 947 /* 948 * ERR_PSS bit needs to be cleared as well in case 949 * interrups are shared so driver's interrupt handler is 950 * still called even though it is already masked out. 951 */ 952 curr_value = readl( 953 bfa->ioc.ioc_regs.pss_err_status_reg); 954 writel(curr_value, 955 bfa->ioc.ioc_regs.pss_err_status_reg); 956 } 957 958 writel(intr, bfa->iocfc.bfa_regs.intr_status); 959 bfa_ioc_error_isr(&bfa->ioc); 960 } 961} 962 963/* 964 * BFA IOC FC related functions 965 */ 966 967/* 968 * BFA IOC private functions 969 */ 970 971/* 972 * Use the Mailbox interface to send BFI_IOCFC_H2I_CFG_REQ 973 */ 974static void 975bfa_iocfc_send_cfg(void *bfa_arg) 976{ 977 struct bfa_s *bfa = bfa_arg; 978 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 979 struct bfi_iocfc_cfg_req_s cfg_req; 980 struct bfi_iocfc_cfg_s *cfg_info = iocfc->cfginfo; 981 struct bfa_iocfc_cfg_s *cfg = &iocfc->cfg; 982 int i; 983 984 WARN_ON(cfg->fwcfg.num_cqs > BFI_IOC_MAX_CQS); 985 bfa_trc(bfa, cfg->fwcfg.num_cqs); 986 987 bfa_iocfc_reset_queues(bfa); 988 989 /* 990 * initialize IOC configuration info 991 */ 992 cfg_info->single_msix_vec = 0; 993 if (bfa->msix.nvecs == 1) 994 cfg_info->single_msix_vec = 1; 995 cfg_info->endian_sig = BFI_IOC_ENDIAN_SIG; 996 cfg_info->num_cqs = cfg->fwcfg.num_cqs; 997 cfg_info->num_ioim_reqs = cpu_to_be16(bfa_fcpim_get_throttle_cfg(bfa, 998 cfg->fwcfg.num_ioim_reqs)); 999 cfg_info->num_fwtio_reqs = cpu_to_be16(cfg->fwcfg.num_fwtio_reqs); 1000 1001 bfa_dma_be_addr_set(cfg_info->cfgrsp_addr, iocfc->cfgrsp_dma.pa); 1002 /* 1003 * dma map REQ and RSP circular queues and shadow pointers 1004 */ 1005 for (i = 0; i < cfg->fwcfg.num_cqs; i++) { 1006 bfa_dma_be_addr_set(cfg_info->req_cq_ba[i], 1007 iocfc->req_cq_ba[i].pa); 1008 bfa_dma_be_addr_set(cfg_info->req_shadow_ci[i], 1009 iocfc->req_cq_shadow_ci[i].pa); 1010 cfg_info->req_cq_elems[i] = 1011 cpu_to_be16(cfg->drvcfg.num_reqq_elems); 1012 1013 bfa_dma_be_addr_set(cfg_info->rsp_cq_ba[i], 1014 iocfc->rsp_cq_ba[i].pa); 1015 bfa_dma_be_addr_set(cfg_info->rsp_shadow_pi[i], 1016 iocfc->rsp_cq_shadow_pi[i].pa); 1017 cfg_info->rsp_cq_elems[i] = 1018 cpu_to_be16(cfg->drvcfg.num_rspq_elems); 1019 } 1020 1021 /* 1022 * Enable interrupt coalescing if it is driver init path 1023 * and not ioc disable/enable path. 1024 */ 1025 if (bfa_fsm_cmp_state(iocfc, bfa_iocfc_sm_init_cfg_wait)) 1026 cfg_info->intr_attr.coalesce = BFA_TRUE; 1027 1028 /* 1029 * dma map IOC configuration itself 1030 */ 1031 bfi_h2i_set(cfg_req.mh, BFI_MC_IOCFC, BFI_IOCFC_H2I_CFG_REQ, 1032 bfa_fn_lpu(bfa)); 1033 bfa_dma_be_addr_set(cfg_req.ioc_cfg_dma_addr, iocfc->cfg_info.pa); 1034 1035 bfa_ioc_mbox_send(&bfa->ioc, &cfg_req, 1036 sizeof(struct bfi_iocfc_cfg_req_s)); 1037} 1038 1039static void 1040bfa_iocfc_init_mem(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, 1041 struct bfa_pcidev_s *pcidev) 1042{ 1043 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1044 1045 bfa->bfad = bfad; 1046 iocfc->bfa = bfa; 1047 iocfc->cfg = *cfg; 1048 1049 /* 1050 * Initialize chip specific handlers. 1051 */ 1052 if (bfa_asic_id_ctc(bfa_ioc_devid(&bfa->ioc))) { 1053 iocfc->hwif.hw_reginit = bfa_hwct_reginit; 1054 iocfc->hwif.hw_reqq_ack = bfa_hwct_reqq_ack; 1055 iocfc->hwif.hw_rspq_ack = bfa_hwct_rspq_ack; 1056 iocfc->hwif.hw_msix_init = bfa_hwct_msix_init; 1057 iocfc->hwif.hw_msix_ctrl_install = bfa_hwct_msix_ctrl_install; 1058 iocfc->hwif.hw_msix_queue_install = bfa_hwct_msix_queue_install; 1059 iocfc->hwif.hw_msix_uninstall = bfa_hwct_msix_uninstall; 1060 iocfc->hwif.hw_isr_mode_set = bfa_hwct_isr_mode_set; 1061 iocfc->hwif.hw_msix_getvecs = bfa_hwct_msix_getvecs; 1062 iocfc->hwif.hw_msix_get_rme_range = bfa_hwct_msix_get_rme_range; 1063 iocfc->hwif.rme_vec_q0 = BFI_MSIX_RME_QMIN_CT; 1064 iocfc->hwif.cpe_vec_q0 = BFI_MSIX_CPE_QMIN_CT; 1065 } else { 1066 iocfc->hwif.hw_reginit = bfa_hwcb_reginit; 1067 iocfc->hwif.hw_reqq_ack = NULL; 1068 iocfc->hwif.hw_rspq_ack = bfa_hwcb_rspq_ack; 1069 iocfc->hwif.hw_msix_init = bfa_hwcb_msix_init; 1070 iocfc->hwif.hw_msix_ctrl_install = bfa_hwcb_msix_ctrl_install; 1071 iocfc->hwif.hw_msix_queue_install = bfa_hwcb_msix_queue_install; 1072 iocfc->hwif.hw_msix_uninstall = bfa_hwcb_msix_uninstall; 1073 iocfc->hwif.hw_isr_mode_set = bfa_hwcb_isr_mode_set; 1074 iocfc->hwif.hw_msix_getvecs = bfa_hwcb_msix_getvecs; 1075 iocfc->hwif.hw_msix_get_rme_range = bfa_hwcb_msix_get_rme_range; 1076 iocfc->hwif.rme_vec_q0 = BFI_MSIX_RME_QMIN_CB + 1077 bfa_ioc_pcifn(&bfa->ioc) * BFI_IOC_MAX_CQS; 1078 iocfc->hwif.cpe_vec_q0 = BFI_MSIX_CPE_QMIN_CB + 1079 bfa_ioc_pcifn(&bfa->ioc) * BFI_IOC_MAX_CQS; 1080 } 1081 1082 if (bfa_asic_id_ct2(bfa_ioc_devid(&bfa->ioc))) { 1083 iocfc->hwif.hw_reginit = bfa_hwct2_reginit; 1084 iocfc->hwif.hw_isr_mode_set = NULL; 1085 iocfc->hwif.hw_rspq_ack = bfa_hwct2_rspq_ack; 1086 } 1087 1088 iocfc->hwif.hw_reginit(bfa); 1089 bfa->msix.nvecs = 0; 1090} 1091 1092static void 1093bfa_iocfc_mem_claim(struct bfa_s *bfa, struct bfa_iocfc_cfg_s *cfg) 1094{ 1095 u8 *dm_kva = NULL; 1096 u64 dm_pa = 0; 1097 int i, per_reqq_sz, per_rspq_sz; 1098 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1099 struct bfa_mem_dma_s *ioc_dma = BFA_MEM_IOC_DMA(bfa); 1100 struct bfa_mem_dma_s *iocfc_dma = BFA_MEM_IOCFC_DMA(bfa); 1101 struct bfa_mem_dma_s *reqq_dma, *rspq_dma; 1102 1103 /* First allocate dma memory for IOC */ 1104 bfa_ioc_mem_claim(&bfa->ioc, bfa_mem_dma_virt(ioc_dma), 1105 bfa_mem_dma_phys(ioc_dma)); 1106 1107 /* Claim DMA-able memory for the request/response queues */ 1108 per_reqq_sz = BFA_ROUNDUP((cfg->drvcfg.num_reqq_elems * BFI_LMSG_SZ), 1109 BFA_DMA_ALIGN_SZ); 1110 per_rspq_sz = BFA_ROUNDUP((cfg->drvcfg.num_rspq_elems * BFI_LMSG_SZ), 1111 BFA_DMA_ALIGN_SZ); 1112 1113 for (i = 0; i < cfg->fwcfg.num_cqs; i++) { 1114 reqq_dma = BFA_MEM_REQQ_DMA(bfa, i); 1115 iocfc->req_cq_ba[i].kva = bfa_mem_dma_virt(reqq_dma); 1116 iocfc->req_cq_ba[i].pa = bfa_mem_dma_phys(reqq_dma); 1117 memset(iocfc->req_cq_ba[i].kva, 0, per_reqq_sz); 1118 1119 rspq_dma = BFA_MEM_RSPQ_DMA(bfa, i); 1120 iocfc->rsp_cq_ba[i].kva = bfa_mem_dma_virt(rspq_dma); 1121 iocfc->rsp_cq_ba[i].pa = bfa_mem_dma_phys(rspq_dma); 1122 memset(iocfc->rsp_cq_ba[i].kva, 0, per_rspq_sz); 1123 } 1124 1125 /* Claim IOCFC dma memory - for shadow CI/PI */ 1126 dm_kva = bfa_mem_dma_virt(iocfc_dma); 1127 dm_pa = bfa_mem_dma_phys(iocfc_dma); 1128 1129 for (i = 0; i < cfg->fwcfg.num_cqs; i++) { 1130 iocfc->req_cq_shadow_ci[i].kva = dm_kva; 1131 iocfc->req_cq_shadow_ci[i].pa = dm_pa; 1132 dm_kva += BFA_CACHELINE_SZ; 1133 dm_pa += BFA_CACHELINE_SZ; 1134 1135 iocfc->rsp_cq_shadow_pi[i].kva = dm_kva; 1136 iocfc->rsp_cq_shadow_pi[i].pa = dm_pa; 1137 dm_kva += BFA_CACHELINE_SZ; 1138 dm_pa += BFA_CACHELINE_SZ; 1139 } 1140 1141 /* Claim IOCFC dma memory - for the config info page */ 1142 bfa->iocfc.cfg_info.kva = dm_kva; 1143 bfa->iocfc.cfg_info.pa = dm_pa; 1144 bfa->iocfc.cfginfo = (struct bfi_iocfc_cfg_s *) dm_kva; 1145 dm_kva += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfg_s), BFA_CACHELINE_SZ); 1146 dm_pa += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfg_s), BFA_CACHELINE_SZ); 1147 1148 /* Claim IOCFC dma memory - for the config response */ 1149 bfa->iocfc.cfgrsp_dma.kva = dm_kva; 1150 bfa->iocfc.cfgrsp_dma.pa = dm_pa; 1151 bfa->iocfc.cfgrsp = (struct bfi_iocfc_cfgrsp_s *) dm_kva; 1152 dm_kva += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfgrsp_s), 1153 BFA_CACHELINE_SZ); 1154 dm_pa += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfgrsp_s), 1155 BFA_CACHELINE_SZ); 1156 1157 /* Claim IOCFC kva memory */ 1158 bfa_ioc_debug_memclaim(&bfa->ioc, bfa_mem_kva_curp(iocfc)); 1159 bfa_mem_kva_curp(iocfc) += BFA_DBG_FWTRC_LEN; 1160} 1161 1162/* 1163 * Start BFA submodules. 1164 */ 1165static void 1166bfa_iocfc_start_submod(struct bfa_s *bfa) 1167{ 1168 int i; 1169 1170 bfa->queue_process = BFA_TRUE; 1171 for (i = 0; i < BFI_IOC_MAX_CQS; i++) 1172 bfa_isr_rspq_ack(bfa, i, bfa_rspq_ci(bfa, i)); 1173 1174 for (i = 0; hal_mods[i]; i++) 1175 hal_mods[i]->start(bfa); 1176 1177 bfa->iocfc.submod_enabled = BFA_TRUE; 1178} 1179 1180/* 1181 * Disable BFA submodules. 1182 */ 1183static void 1184bfa_iocfc_disable_submod(struct bfa_s *bfa) 1185{ 1186 int i; 1187 1188 if (bfa->iocfc.submod_enabled == BFA_FALSE) 1189 return; 1190 1191 for (i = 0; hal_mods[i]; i++) 1192 hal_mods[i]->iocdisable(bfa); 1193 1194 bfa->iocfc.submod_enabled = BFA_FALSE; 1195} 1196 1197static void 1198bfa_iocfc_init_cb(void *bfa_arg, bfa_boolean_t complete) 1199{ 1200 struct bfa_s *bfa = bfa_arg; 1201 1202 if (complete) 1203 bfa_cb_init(bfa->bfad, bfa->iocfc.op_status); 1204} 1205 1206static void 1207bfa_iocfc_stop_cb(void *bfa_arg, bfa_boolean_t compl) 1208{ 1209 struct bfa_s *bfa = bfa_arg; 1210 struct bfad_s *bfad = bfa->bfad; 1211 1212 if (compl) 1213 complete(&bfad->comp); 1214} 1215 1216static void 1217bfa_iocfc_enable_cb(void *bfa_arg, bfa_boolean_t compl) 1218{ 1219 struct bfa_s *bfa = bfa_arg; 1220 struct bfad_s *bfad = bfa->bfad; 1221 1222 if (compl) 1223 complete(&bfad->enable_comp); 1224} 1225 1226static void 1227bfa_iocfc_disable_cb(void *bfa_arg, bfa_boolean_t compl) 1228{ 1229 struct bfa_s *bfa = bfa_arg; 1230 struct bfad_s *bfad = bfa->bfad; 1231 1232 if (compl) 1233 complete(&bfad->disable_comp); 1234} 1235 1236/** 1237 * configure queue registers from firmware response 1238 */ 1239static void 1240bfa_iocfc_qreg(struct bfa_s *bfa, struct bfi_iocfc_qreg_s *qreg) 1241{ 1242 int i; 1243 struct bfa_iocfc_regs_s *r = &bfa->iocfc.bfa_regs; 1244 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc); 1245 1246 for (i = 0; i < BFI_IOC_MAX_CQS; i++) { 1247 bfa->iocfc.hw_qid[i] = qreg->hw_qid[i]; 1248 r->cpe_q_ci[i] = kva + be32_to_cpu(qreg->cpe_q_ci_off[i]); 1249 r->cpe_q_pi[i] = kva + be32_to_cpu(qreg->cpe_q_pi_off[i]); 1250 r->cpe_q_ctrl[i] = kva + be32_to_cpu(qreg->cpe_qctl_off[i]); 1251 r->rme_q_ci[i] = kva + be32_to_cpu(qreg->rme_q_ci_off[i]); 1252 r->rme_q_pi[i] = kva + be32_to_cpu(qreg->rme_q_pi_off[i]); 1253 r->rme_q_ctrl[i] = kva + be32_to_cpu(qreg->rme_qctl_off[i]); 1254 } 1255} 1256 1257static void 1258bfa_iocfc_res_recfg(struct bfa_s *bfa, struct bfa_iocfc_fwcfg_s *fwcfg) 1259{ 1260 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1261 struct bfi_iocfc_cfg_s *cfg_info = iocfc->cfginfo; 1262 1263 bfa_fcxp_res_recfg(bfa, fwcfg->num_fcxp_reqs); 1264 bfa_uf_res_recfg(bfa, fwcfg->num_uf_bufs); 1265 bfa_rport_res_recfg(bfa, fwcfg->num_rports); 1266 bfa_fcp_res_recfg(bfa, cpu_to_be16(cfg_info->num_ioim_reqs), 1267 fwcfg->num_ioim_reqs); 1268 bfa_tskim_res_recfg(bfa, fwcfg->num_tskim_reqs); 1269} 1270 1271/* 1272 * Update BFA configuration from firmware configuration. 1273 */ 1274static void 1275bfa_iocfc_cfgrsp(struct bfa_s *bfa) 1276{ 1277 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1278 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp; 1279 struct bfa_iocfc_fwcfg_s *fwcfg = &cfgrsp->fwcfg; 1280 1281 fwcfg->num_cqs = fwcfg->num_cqs; 1282 fwcfg->num_ioim_reqs = be16_to_cpu(fwcfg->num_ioim_reqs); 1283 fwcfg->num_fwtio_reqs = be16_to_cpu(fwcfg->num_fwtio_reqs); 1284 fwcfg->num_tskim_reqs = be16_to_cpu(fwcfg->num_tskim_reqs); 1285 fwcfg->num_fcxp_reqs = be16_to_cpu(fwcfg->num_fcxp_reqs); 1286 fwcfg->num_uf_bufs = be16_to_cpu(fwcfg->num_uf_bufs); 1287 fwcfg->num_rports = be16_to_cpu(fwcfg->num_rports); 1288 1289 /* 1290 * configure queue register offsets as learnt from firmware 1291 */ 1292 bfa_iocfc_qreg(bfa, &cfgrsp->qreg); 1293 1294 /* 1295 * Re-configure resources as learnt from Firmware 1296 */ 1297 bfa_iocfc_res_recfg(bfa, fwcfg); 1298 1299 /* 1300 * Install MSIX queue handlers 1301 */ 1302 bfa_msix_queue_install(bfa); 1303 1304 if (bfa->iocfc.cfgrsp->pbc_cfg.pbc_pwwn != 0) { 1305 bfa->ioc.attr->pwwn = bfa->iocfc.cfgrsp->pbc_cfg.pbc_pwwn; 1306 bfa->ioc.attr->nwwn = bfa->iocfc.cfgrsp->pbc_cfg.pbc_nwwn; 1307 bfa_fsm_send_event(iocfc, IOCFC_E_CFG_DONE); 1308 } 1309} 1310 1311void 1312bfa_iocfc_reset_queues(struct bfa_s *bfa) 1313{ 1314 int q; 1315 1316 for (q = 0; q < BFI_IOC_MAX_CQS; q++) { 1317 bfa_reqq_ci(bfa, q) = 0; 1318 bfa_reqq_pi(bfa, q) = 0; 1319 bfa_rspq_ci(bfa, q) = 0; 1320 bfa_rspq_pi(bfa, q) = 0; 1321 } 1322} 1323 1324/* 1325 * Process FAA pwwn msg from fw. 1326 */ 1327static void 1328bfa_iocfc_process_faa_addr(struct bfa_s *bfa, struct bfi_faa_addr_msg_s *msg) 1329{ 1330 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1331 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp; 1332 1333 cfgrsp->pbc_cfg.pbc_pwwn = msg->pwwn; 1334 cfgrsp->pbc_cfg.pbc_nwwn = msg->nwwn; 1335 1336 bfa->ioc.attr->pwwn = msg->pwwn; 1337 bfa->ioc.attr->nwwn = msg->nwwn; 1338 bfa_fsm_send_event(iocfc, IOCFC_E_CFG_DONE); 1339} 1340 1341/* Fabric Assigned Address specific functions */ 1342 1343/* 1344 * Check whether IOC is ready before sending command down 1345 */ 1346static bfa_status_t 1347bfa_faa_validate_request(struct bfa_s *bfa) 1348{ 1349 enum bfa_ioc_type_e ioc_type = bfa_get_type(bfa); 1350 u32 card_type = bfa->ioc.attr->card_type; 1351 1352 if (bfa_ioc_is_operational(&bfa->ioc)) { 1353 if ((ioc_type != BFA_IOC_TYPE_FC) || bfa_mfg_is_mezz(card_type)) 1354 return BFA_STATUS_FEATURE_NOT_SUPPORTED; 1355 } else { 1356 return BFA_STATUS_IOC_NON_OP; 1357 } 1358 1359 return BFA_STATUS_OK; 1360} 1361 1362bfa_status_t 1363bfa_faa_query(struct bfa_s *bfa, struct bfa_faa_attr_s *attr, 1364 bfa_cb_iocfc_t cbfn, void *cbarg) 1365{ 1366 struct bfi_faa_query_s faa_attr_req; 1367 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1368 bfa_status_t status; 1369 1370 status = bfa_faa_validate_request(bfa); 1371 if (status != BFA_STATUS_OK) 1372 return status; 1373 1374 if (iocfc->faa_args.busy == BFA_TRUE) 1375 return BFA_STATUS_DEVBUSY; 1376 1377 iocfc->faa_args.faa_attr = attr; 1378 iocfc->faa_args.faa_cb.faa_cbfn = cbfn; 1379 iocfc->faa_args.faa_cb.faa_cbarg = cbarg; 1380 1381 iocfc->faa_args.busy = BFA_TRUE; 1382 memset(&faa_attr_req, 0, sizeof(struct bfi_faa_query_s)); 1383 bfi_h2i_set(faa_attr_req.mh, BFI_MC_IOCFC, 1384 BFI_IOCFC_H2I_FAA_QUERY_REQ, bfa_fn_lpu(bfa)); 1385 1386 bfa_ioc_mbox_send(&bfa->ioc, &faa_attr_req, 1387 sizeof(struct bfi_faa_query_s)); 1388 1389 return BFA_STATUS_OK; 1390} 1391 1392/* 1393 * FAA query response 1394 */ 1395static void 1396bfa_faa_query_reply(struct bfa_iocfc_s *iocfc, 1397 bfi_faa_query_rsp_t *rsp) 1398{ 1399 void *cbarg = iocfc->faa_args.faa_cb.faa_cbarg; 1400 1401 if (iocfc->faa_args.faa_attr) { 1402 iocfc->faa_args.faa_attr->faa = rsp->faa; 1403 iocfc->faa_args.faa_attr->faa_state = rsp->faa_status; 1404 iocfc->faa_args.faa_attr->pwwn_source = rsp->addr_source; 1405 } 1406 1407 WARN_ON(!iocfc->faa_args.faa_cb.faa_cbfn); 1408 1409 iocfc->faa_args.faa_cb.faa_cbfn(cbarg, BFA_STATUS_OK); 1410 iocfc->faa_args.busy = BFA_FALSE; 1411} 1412 1413/* 1414 * IOC enable request is complete 1415 */ 1416static void 1417bfa_iocfc_enable_cbfn(void *bfa_arg, enum bfa_status status) 1418{ 1419 struct bfa_s *bfa = bfa_arg; 1420 1421 if (status == BFA_STATUS_OK) 1422 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_ENABLED); 1423 else 1424 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_FAILED); 1425} 1426 1427/* 1428 * IOC disable request is complete 1429 */ 1430static void 1431bfa_iocfc_disable_cbfn(void *bfa_arg) 1432{ 1433 struct bfa_s *bfa = bfa_arg; 1434 1435 bfa->queue_process = BFA_FALSE; 1436 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_DISABLED); 1437} 1438 1439/* 1440 * Notify sub-modules of hardware failure. 1441 */ 1442static void 1443bfa_iocfc_hbfail_cbfn(void *bfa_arg) 1444{ 1445 struct bfa_s *bfa = bfa_arg; 1446 1447 bfa->queue_process = BFA_FALSE; 1448 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_FAILED); 1449} 1450 1451/* 1452 * Actions on chip-reset completion. 1453 */ 1454static void 1455bfa_iocfc_reset_cbfn(void *bfa_arg) 1456{ 1457 struct bfa_s *bfa = bfa_arg; 1458 1459 bfa_iocfc_reset_queues(bfa); 1460 bfa_isr_enable(bfa); 1461} 1462 1463/* 1464 * Query IOC memory requirement information. 1465 */ 1466void 1467bfa_iocfc_meminfo(struct bfa_iocfc_cfg_s *cfg, struct bfa_meminfo_s *meminfo, 1468 struct bfa_s *bfa) 1469{ 1470 int q, per_reqq_sz, per_rspq_sz; 1471 struct bfa_mem_dma_s *ioc_dma = BFA_MEM_IOC_DMA(bfa); 1472 struct bfa_mem_dma_s *iocfc_dma = BFA_MEM_IOCFC_DMA(bfa); 1473 struct bfa_mem_kva_s *iocfc_kva = BFA_MEM_IOCFC_KVA(bfa); 1474 u32 dm_len = 0; 1475 1476 /* dma memory setup for IOC */ 1477 bfa_mem_dma_setup(meminfo, ioc_dma, 1478 BFA_ROUNDUP(sizeof(struct bfi_ioc_attr_s), BFA_DMA_ALIGN_SZ)); 1479 1480 /* dma memory setup for REQ/RSP queues */ 1481 per_reqq_sz = BFA_ROUNDUP((cfg->drvcfg.num_reqq_elems * BFI_LMSG_SZ), 1482 BFA_DMA_ALIGN_SZ); 1483 per_rspq_sz = BFA_ROUNDUP((cfg->drvcfg.num_rspq_elems * BFI_LMSG_SZ), 1484 BFA_DMA_ALIGN_SZ); 1485 1486 for (q = 0; q < cfg->fwcfg.num_cqs; q++) { 1487 bfa_mem_dma_setup(meminfo, BFA_MEM_REQQ_DMA(bfa, q), 1488 per_reqq_sz); 1489 bfa_mem_dma_setup(meminfo, BFA_MEM_RSPQ_DMA(bfa, q), 1490 per_rspq_sz); 1491 } 1492 1493 /* IOCFC dma memory - calculate Shadow CI/PI size */ 1494 for (q = 0; q < cfg->fwcfg.num_cqs; q++) 1495 dm_len += (2 * BFA_CACHELINE_SZ); 1496 1497 /* IOCFC dma memory - calculate config info / rsp size */ 1498 dm_len += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfg_s), BFA_CACHELINE_SZ); 1499 dm_len += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfgrsp_s), 1500 BFA_CACHELINE_SZ); 1501 1502 /* dma memory setup for IOCFC */ 1503 bfa_mem_dma_setup(meminfo, iocfc_dma, dm_len); 1504 1505 /* kva memory setup for IOCFC */ 1506 bfa_mem_kva_setup(meminfo, iocfc_kva, BFA_DBG_FWTRC_LEN); 1507} 1508 1509/* 1510 * Query IOC memory requirement information. 1511 */ 1512void 1513bfa_iocfc_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, 1514 struct bfa_pcidev_s *pcidev) 1515{ 1516 int i; 1517 struct bfa_ioc_s *ioc = &bfa->ioc; 1518 1519 bfa_iocfc_cbfn.enable_cbfn = bfa_iocfc_enable_cbfn; 1520 bfa_iocfc_cbfn.disable_cbfn = bfa_iocfc_disable_cbfn; 1521 bfa_iocfc_cbfn.hbfail_cbfn = bfa_iocfc_hbfail_cbfn; 1522 bfa_iocfc_cbfn.reset_cbfn = bfa_iocfc_reset_cbfn; 1523 1524 ioc->trcmod = bfa->trcmod; 1525 bfa_ioc_attach(&bfa->ioc, bfa, &bfa_iocfc_cbfn, &bfa->timer_mod); 1526 1527 bfa_ioc_pci_init(&bfa->ioc, pcidev, BFI_PCIFN_CLASS_FC); 1528 bfa_ioc_mbox_register(&bfa->ioc, bfa_mbox_isrs); 1529 1530 bfa_iocfc_init_mem(bfa, bfad, cfg, pcidev); 1531 bfa_iocfc_mem_claim(bfa, cfg); 1532 INIT_LIST_HEAD(&bfa->timer_mod.timer_q); 1533 1534 INIT_LIST_HEAD(&bfa->comp_q); 1535 for (i = 0; i < BFI_IOC_MAX_CQS; i++) 1536 INIT_LIST_HEAD(&bfa->reqq_waitq[i]); 1537 1538 bfa->iocfc.cb_reqd = BFA_FALSE; 1539 bfa->iocfc.op_status = BFA_STATUS_OK; 1540 bfa->iocfc.submod_enabled = BFA_FALSE; 1541 1542 bfa_fsm_set_state(&bfa->iocfc, bfa_iocfc_sm_stopped); 1543} 1544 1545/* 1546 * Query IOC memory requirement information. 1547 */ 1548void 1549bfa_iocfc_init(struct bfa_s *bfa) 1550{ 1551 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_INIT); 1552} 1553 1554/* 1555 * IOC start called from bfa_start(). Called to start IOC operations 1556 * at driver instantiation for this instance. 1557 */ 1558void 1559bfa_iocfc_start(struct bfa_s *bfa) 1560{ 1561 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_START); 1562} 1563 1564/* 1565 * IOC stop called from bfa_stop(). Called only when driver is unloaded 1566 * for this instance. 1567 */ 1568void 1569bfa_iocfc_stop(struct bfa_s *bfa) 1570{ 1571 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_STOP); 1572} 1573 1574void 1575bfa_iocfc_isr(void *bfaarg, struct bfi_mbmsg_s *m) 1576{ 1577 struct bfa_s *bfa = bfaarg; 1578 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1579 union bfi_iocfc_i2h_msg_u *msg; 1580 1581 msg = (union bfi_iocfc_i2h_msg_u *) m; 1582 bfa_trc(bfa, msg->mh.msg_id); 1583 1584 switch (msg->mh.msg_id) { 1585 case BFI_IOCFC_I2H_CFG_REPLY: 1586 bfa_iocfc_cfgrsp(bfa); 1587 break; 1588 case BFI_IOCFC_I2H_UPDATEQ_RSP: 1589 iocfc->updateq_cbfn(iocfc->updateq_cbarg, BFA_STATUS_OK); 1590 break; 1591 case BFI_IOCFC_I2H_ADDR_MSG: 1592 bfa_iocfc_process_faa_addr(bfa, 1593 (struct bfi_faa_addr_msg_s *)msg); 1594 break; 1595 case BFI_IOCFC_I2H_FAA_QUERY_RSP: 1596 bfa_faa_query_reply(iocfc, (bfi_faa_query_rsp_t *)msg); 1597 break; 1598 default: 1599 WARN_ON(1); 1600 } 1601} 1602 1603void 1604bfa_iocfc_get_attr(struct bfa_s *bfa, struct bfa_iocfc_attr_s *attr) 1605{ 1606 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1607 1608 attr->intr_attr.coalesce = iocfc->cfginfo->intr_attr.coalesce; 1609 1610 attr->intr_attr.delay = iocfc->cfginfo->intr_attr.delay ? 1611 be16_to_cpu(iocfc->cfginfo->intr_attr.delay) : 1612 be16_to_cpu(iocfc->cfgrsp->intr_attr.delay); 1613 1614 attr->intr_attr.latency = iocfc->cfginfo->intr_attr.latency ? 1615 be16_to_cpu(iocfc->cfginfo->intr_attr.latency) : 1616 be16_to_cpu(iocfc->cfgrsp->intr_attr.latency); 1617 1618 attr->config = iocfc->cfg; 1619} 1620 1621bfa_status_t 1622bfa_iocfc_israttr_set(struct bfa_s *bfa, struct bfa_iocfc_intr_attr_s *attr) 1623{ 1624 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1625 struct bfi_iocfc_set_intr_req_s *m; 1626 1627 iocfc->cfginfo->intr_attr.coalesce = attr->coalesce; 1628 iocfc->cfginfo->intr_attr.delay = cpu_to_be16(attr->delay); 1629 iocfc->cfginfo->intr_attr.latency = cpu_to_be16(attr->latency); 1630 1631 if (!bfa_iocfc_is_operational(bfa)) 1632 return BFA_STATUS_OK; 1633 1634 m = bfa_reqq_next(bfa, BFA_REQQ_IOC); 1635 if (!m) 1636 return BFA_STATUS_DEVBUSY; 1637 1638 bfi_h2i_set(m->mh, BFI_MC_IOCFC, BFI_IOCFC_H2I_SET_INTR_REQ, 1639 bfa_fn_lpu(bfa)); 1640 m->coalesce = iocfc->cfginfo->intr_attr.coalesce; 1641 m->delay = iocfc->cfginfo->intr_attr.delay; 1642 m->latency = iocfc->cfginfo->intr_attr.latency; 1643 1644 bfa_trc(bfa, attr->delay); 1645 bfa_trc(bfa, attr->latency); 1646 1647 bfa_reqq_produce(bfa, BFA_REQQ_IOC, m->mh); 1648 return BFA_STATUS_OK; 1649} 1650 1651void 1652bfa_iocfc_set_snsbase(struct bfa_s *bfa, int seg_no, u64 snsbase_pa) 1653{ 1654 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1655 1656 iocfc->cfginfo->sense_buf_len = (BFI_IOIM_SNSLEN - 1); 1657 bfa_dma_be_addr_set(iocfc->cfginfo->ioim_snsbase[seg_no], snsbase_pa); 1658} 1659/* 1660 * Enable IOC after it is disabled. 1661 */ 1662void 1663bfa_iocfc_enable(struct bfa_s *bfa) 1664{ 1665 bfa_plog_str(bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_MISC, 0, 1666 "IOC Enable"); 1667 bfa->iocfc.cb_reqd = BFA_TRUE; 1668 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_ENABLE); 1669} 1670 1671void 1672bfa_iocfc_disable(struct bfa_s *bfa) 1673{ 1674 bfa_plog_str(bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_MISC, 0, 1675 "IOC Disable"); 1676 1677 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_DISABLE); 1678} 1679 1680bfa_boolean_t 1681bfa_iocfc_is_operational(struct bfa_s *bfa) 1682{ 1683 return bfa_ioc_is_operational(&bfa->ioc) && 1684 bfa_fsm_cmp_state(&bfa->iocfc, bfa_iocfc_sm_operational); 1685} 1686 1687/* 1688 * Return boot target port wwns -- read from boot information in flash. 1689 */ 1690void 1691bfa_iocfc_get_bootwwns(struct bfa_s *bfa, u8 *nwwns, wwn_t *wwns) 1692{ 1693 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1694 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp; 1695 int i; 1696 1697 if (cfgrsp->pbc_cfg.boot_enabled && cfgrsp->pbc_cfg.nbluns) { 1698 bfa_trc(bfa, cfgrsp->pbc_cfg.nbluns); 1699 *nwwns = cfgrsp->pbc_cfg.nbluns; 1700 for (i = 0; i < cfgrsp->pbc_cfg.nbluns; i++) 1701 wwns[i] = cfgrsp->pbc_cfg.blun[i].tgt_pwwn; 1702 1703 return; 1704 } 1705 1706 *nwwns = cfgrsp->bootwwns.nwwns; 1707 memcpy(wwns, cfgrsp->bootwwns.wwn, sizeof(cfgrsp->bootwwns.wwn)); 1708} 1709 1710int 1711bfa_iocfc_get_pbc_vports(struct bfa_s *bfa, struct bfi_pbc_vport_s *pbc_vport) 1712{ 1713 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1714 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp; 1715 1716 memcpy(pbc_vport, cfgrsp->pbc_cfg.vport, sizeof(cfgrsp->pbc_cfg.vport)); 1717 return cfgrsp->pbc_cfg.nvports; 1718} 1719 1720 1721/* 1722 * Use this function query the memory requirement of the BFA library. 1723 * This function needs to be called before bfa_attach() to get the 1724 * memory required of the BFA layer for a given driver configuration. 1725 * 1726 * This call will fail, if the cap is out of range compared to pre-defined 1727 * values within the BFA library 1728 * 1729 * @param[in] cfg - pointer to bfa_ioc_cfg_t. Driver layer should indicate 1730 * its configuration in this structure. 1731 * The default values for struct bfa_iocfc_cfg_s can be 1732 * fetched using bfa_cfg_get_default() API. 1733 * 1734 * If cap's boundary check fails, the library will use 1735 * the default bfa_cap_t values (and log a warning msg). 1736 * 1737 * @param[out] meminfo - pointer to bfa_meminfo_t. This content 1738 * indicates the memory type (see bfa_mem_type_t) and 1739 * amount of memory required. 1740 * 1741 * Driver should allocate the memory, populate the 1742 * starting address for each block and provide the same 1743 * structure as input parameter to bfa_attach() call. 1744 * 1745 * @param[in] bfa - pointer to the bfa structure, used while fetching the 1746 * dma, kva memory information of the bfa sub-modules. 1747 * 1748 * @return void 1749 * 1750 * Special Considerations: @note 1751 */ 1752void 1753bfa_cfg_get_meminfo(struct bfa_iocfc_cfg_s *cfg, struct bfa_meminfo_s *meminfo, 1754 struct bfa_s *bfa) 1755{ 1756 int i; 1757 struct bfa_mem_dma_s *port_dma = BFA_MEM_PORT_DMA(bfa); 1758 struct bfa_mem_dma_s *ablk_dma = BFA_MEM_ABLK_DMA(bfa); 1759 struct bfa_mem_dma_s *cee_dma = BFA_MEM_CEE_DMA(bfa); 1760 struct bfa_mem_dma_s *sfp_dma = BFA_MEM_SFP_DMA(bfa); 1761 struct bfa_mem_dma_s *flash_dma = BFA_MEM_FLASH_DMA(bfa); 1762 struct bfa_mem_dma_s *diag_dma = BFA_MEM_DIAG_DMA(bfa); 1763 struct bfa_mem_dma_s *phy_dma = BFA_MEM_PHY_DMA(bfa); 1764 struct bfa_mem_dma_s *fru_dma = BFA_MEM_FRU_DMA(bfa); 1765 1766 WARN_ON((cfg == NULL) || (meminfo == NULL)); 1767 1768 memset((void *)meminfo, 0, sizeof(struct bfa_meminfo_s)); 1769 1770 /* Initialize the DMA & KVA meminfo queues */ 1771 INIT_LIST_HEAD(&meminfo->dma_info.qe); 1772 INIT_LIST_HEAD(&meminfo->kva_info.qe); 1773 1774 bfa_iocfc_meminfo(cfg, meminfo, bfa); 1775 1776 for (i = 0; hal_mods[i]; i++) 1777 hal_mods[i]->meminfo(cfg, meminfo, bfa); 1778 1779 /* dma info setup */ 1780 bfa_mem_dma_setup(meminfo, port_dma, bfa_port_meminfo()); 1781 bfa_mem_dma_setup(meminfo, ablk_dma, bfa_ablk_meminfo()); 1782 bfa_mem_dma_setup(meminfo, cee_dma, bfa_cee_meminfo()); 1783 bfa_mem_dma_setup(meminfo, sfp_dma, bfa_sfp_meminfo()); 1784 bfa_mem_dma_setup(meminfo, flash_dma, 1785 bfa_flash_meminfo(cfg->drvcfg.min_cfg)); 1786 bfa_mem_dma_setup(meminfo, diag_dma, bfa_diag_meminfo()); 1787 bfa_mem_dma_setup(meminfo, phy_dma, 1788 bfa_phy_meminfo(cfg->drvcfg.min_cfg)); 1789 bfa_mem_dma_setup(meminfo, fru_dma, 1790 bfa_fru_meminfo(cfg->drvcfg.min_cfg)); 1791} 1792 1793/* 1794 * Use this function to do attach the driver instance with the BFA 1795 * library. This function will not trigger any HW initialization 1796 * process (which will be done in bfa_init() call) 1797 * 1798 * This call will fail, if the cap is out of range compared to 1799 * pre-defined values within the BFA library 1800 * 1801 * @param[out] bfa Pointer to bfa_t. 1802 * @param[in] bfad Opaque handle back to the driver's IOC structure 1803 * @param[in] cfg Pointer to bfa_ioc_cfg_t. Should be same structure 1804 * that was used in bfa_cfg_get_meminfo(). 1805 * @param[in] meminfo Pointer to bfa_meminfo_t. The driver should 1806 * use the bfa_cfg_get_meminfo() call to 1807 * find the memory blocks required, allocate the 1808 * required memory and provide the starting addresses. 1809 * @param[in] pcidev pointer to struct bfa_pcidev_s 1810 * 1811 * @return 1812 * void 1813 * 1814 * Special Considerations: 1815 * 1816 * @note 1817 * 1818 */ 1819void 1820bfa_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, 1821 struct bfa_meminfo_s *meminfo, struct bfa_pcidev_s *pcidev) 1822{ 1823 int i; 1824 struct bfa_mem_dma_s *dma_info, *dma_elem; 1825 struct bfa_mem_kva_s *kva_info, *kva_elem; 1826 struct list_head *dm_qe, *km_qe; 1827 1828 bfa->fcs = BFA_FALSE; 1829 1830 WARN_ON((cfg == NULL) || (meminfo == NULL)); 1831 1832 /* Initialize memory pointers for iterative allocation */ 1833 dma_info = &meminfo->dma_info; 1834 dma_info->kva_curp = dma_info->kva; 1835 dma_info->dma_curp = dma_info->dma; 1836 1837 kva_info = &meminfo->kva_info; 1838 kva_info->kva_curp = kva_info->kva; 1839 1840 list_for_each(dm_qe, &dma_info->qe) { 1841 dma_elem = (struct bfa_mem_dma_s *) dm_qe; 1842 dma_elem->kva_curp = dma_elem->kva; 1843 dma_elem->dma_curp = dma_elem->dma; 1844 } 1845 1846 list_for_each(km_qe, &kva_info->qe) { 1847 kva_elem = (struct bfa_mem_kva_s *) km_qe; 1848 kva_elem->kva_curp = kva_elem->kva; 1849 } 1850 1851 bfa_iocfc_attach(bfa, bfad, cfg, pcidev); 1852 1853 for (i = 0; hal_mods[i]; i++) 1854 hal_mods[i]->attach(bfa, bfad, cfg, pcidev); 1855 1856 bfa_com_port_attach(bfa); 1857 bfa_com_ablk_attach(bfa); 1858 bfa_com_cee_attach(bfa); 1859 bfa_com_sfp_attach(bfa); 1860 bfa_com_flash_attach(bfa, cfg->drvcfg.min_cfg); 1861 bfa_com_diag_attach(bfa); 1862 bfa_com_phy_attach(bfa, cfg->drvcfg.min_cfg); 1863 bfa_com_fru_attach(bfa, cfg->drvcfg.min_cfg); 1864} 1865 1866/* 1867 * Use this function to delete a BFA IOC. IOC should be stopped (by 1868 * calling bfa_stop()) before this function call. 1869 * 1870 * @param[in] bfa - pointer to bfa_t. 1871 * 1872 * @return 1873 * void 1874 * 1875 * Special Considerations: 1876 * 1877 * @note 1878 */ 1879void 1880bfa_detach(struct bfa_s *bfa) 1881{ 1882 int i; 1883 1884 for (i = 0; hal_mods[i]; i++) 1885 hal_mods[i]->detach(bfa); 1886 bfa_ioc_detach(&bfa->ioc); 1887} 1888 1889void 1890bfa_comp_deq(struct bfa_s *bfa, struct list_head *comp_q) 1891{ 1892 INIT_LIST_HEAD(comp_q); 1893 list_splice_tail_init(&bfa->comp_q, comp_q); 1894} 1895 1896void 1897bfa_comp_process(struct bfa_s *bfa, struct list_head *comp_q) 1898{ 1899 struct list_head *qe; 1900 struct list_head *qen; 1901 struct bfa_cb_qe_s *hcb_qe; 1902 bfa_cb_cbfn_status_t cbfn; 1903 1904 list_for_each_safe(qe, qen, comp_q) { 1905 hcb_qe = (struct bfa_cb_qe_s *) qe; 1906 if (hcb_qe->pre_rmv) { 1907 /* qe is invalid after return, dequeue before cbfn() */ 1908 list_del(qe); 1909 cbfn = (bfa_cb_cbfn_status_t)(hcb_qe->cbfn); 1910 cbfn(hcb_qe->cbarg, hcb_qe->fw_status); 1911 } else 1912 hcb_qe->cbfn(hcb_qe->cbarg, BFA_TRUE); 1913 } 1914} 1915 1916void 1917bfa_comp_free(struct bfa_s *bfa, struct list_head *comp_q) 1918{ 1919 struct list_head *qe; 1920 struct bfa_cb_qe_s *hcb_qe; 1921 1922 while (!list_empty(comp_q)) { 1923 bfa_q_deq(comp_q, &qe); 1924 hcb_qe = (struct bfa_cb_qe_s *) qe; 1925 WARN_ON(hcb_qe->pre_rmv); 1926 hcb_qe->cbfn(hcb_qe->cbarg, BFA_FALSE); 1927 } 1928} 1929 1930/* 1931 * Return the list of PCI vendor/device id lists supported by this 1932 * BFA instance. 1933 */ 1934void 1935bfa_get_pciids(struct bfa_pciid_s **pciids, int *npciids) 1936{ 1937 static struct bfa_pciid_s __pciids[] = { 1938 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_FC_8G2P}, 1939 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_FC_8G1P}, 1940 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_CT}, 1941 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_CT_FC}, 1942 }; 1943 1944 *npciids = sizeof(__pciids) / sizeof(__pciids[0]); 1945 *pciids = __pciids; 1946} 1947 1948/* 1949 * Use this function query the default struct bfa_iocfc_cfg_s value (compiled 1950 * into BFA layer). The OS driver can then turn back and overwrite entries that 1951 * have been configured by the user. 1952 * 1953 * @param[in] cfg - pointer to bfa_ioc_cfg_t 1954 * 1955 * @return 1956 * void 1957 * 1958 * Special Considerations: 1959 * note 1960 */ 1961void 1962bfa_cfg_get_default(struct bfa_iocfc_cfg_s *cfg) 1963{ 1964 cfg->fwcfg.num_fabrics = DEF_CFG_NUM_FABRICS; 1965 cfg->fwcfg.num_lports = DEF_CFG_NUM_LPORTS; 1966 cfg->fwcfg.num_rports = DEF_CFG_NUM_RPORTS; 1967 cfg->fwcfg.num_ioim_reqs = DEF_CFG_NUM_IOIM_REQS; 1968 cfg->fwcfg.num_tskim_reqs = DEF_CFG_NUM_TSKIM_REQS; 1969 cfg->fwcfg.num_fcxp_reqs = DEF_CFG_NUM_FCXP_REQS; 1970 cfg->fwcfg.num_uf_bufs = DEF_CFG_NUM_UF_BUFS; 1971 cfg->fwcfg.num_cqs = DEF_CFG_NUM_CQS; 1972 cfg->fwcfg.num_fwtio_reqs = 0; 1973 1974 cfg->drvcfg.num_reqq_elems = DEF_CFG_NUM_REQQ_ELEMS; 1975 cfg->drvcfg.num_rspq_elems = DEF_CFG_NUM_RSPQ_ELEMS; 1976 cfg->drvcfg.num_sgpgs = DEF_CFG_NUM_SGPGS; 1977 cfg->drvcfg.num_sboot_tgts = DEF_CFG_NUM_SBOOT_TGTS; 1978 cfg->drvcfg.num_sboot_luns = DEF_CFG_NUM_SBOOT_LUNS; 1979 cfg->drvcfg.path_tov = BFA_FCPIM_PATHTOV_DEF; 1980 cfg->drvcfg.ioc_recover = BFA_FALSE; 1981 cfg->drvcfg.delay_comp = BFA_FALSE; 1982 1983} 1984 1985void 1986bfa_cfg_get_min(struct bfa_iocfc_cfg_s *cfg) 1987{ 1988 bfa_cfg_get_default(cfg); 1989 cfg->fwcfg.num_ioim_reqs = BFA_IOIM_MIN; 1990 cfg->fwcfg.num_tskim_reqs = BFA_TSKIM_MIN; 1991 cfg->fwcfg.num_fcxp_reqs = BFA_FCXP_MIN; 1992 cfg->fwcfg.num_uf_bufs = BFA_UF_MIN; 1993 cfg->fwcfg.num_rports = BFA_RPORT_MIN; 1994 cfg->fwcfg.num_fwtio_reqs = 0; 1995 1996 cfg->drvcfg.num_sgpgs = BFA_SGPG_MIN; 1997 cfg->drvcfg.num_reqq_elems = BFA_REQQ_NELEMS_MIN; 1998 cfg->drvcfg.num_rspq_elems = BFA_RSPQ_NELEMS_MIN; 1999 cfg->drvcfg.min_cfg = BFA_TRUE; 2000} 2001