Searched refs:SW (Results 1 - 200 of 571) sorted by relevance

123

/linux-4.4.14/arch/ia64/kernel/
H A Dentry.h24 #define SW(f) (IA64_SWITCH_STACK_##f##_OFFSET) macro
42 .savesp ar.unat,SW(CALLER_UNAT)+16+(off); \
43 .savesp ar.fpsr,SW(AR_FPSR)+16+(off); \
44 .spillsp f2,SW(F2)+16+(off); .spillsp f3,SW(F3)+16+(off); \
45 .spillsp f4,SW(F4)+16+(off); .spillsp f5,SW(F5)+16+(off); \
46 .spillsp f16,SW(F16)+16+(off); .spillsp f17,SW(F17)+16+(off); \
47 .spillsp f18,SW(F18)+16+(off); .spillsp f19,SW(F19)+16+(off); \
48 .spillsp f20,SW(F20)+16+(off); .spillsp f21,SW(F21)+16+(off); \
49 .spillsp f22,SW(F22)+16+(off); .spillsp f23,SW(F23)+16+(off); \
50 .spillsp f24,SW(F24)+16+(off); .spillsp f25,SW(F25)+16+(off); \
51 .spillsp f26,SW(F26)+16+(off); .spillsp f27,SW(F27)+16+(off); \
52 .spillsp f28,SW(F28)+16+(off); .spillsp f29,SW(F29)+16+(off); \
53 .spillsp f30,SW(F30)+16+(off); .spillsp f31,SW(F31)+16+(off); \
54 .spillsp r4,SW(R4)+16+(off); .spillsp r5,SW(R5)+16+(off); \
55 .spillsp r6,SW(R6)+16+(off); .spillsp r7,SW(R7)+16+(off); \
56 .spillsp b0,SW(B0)+16+(off); .spillsp b1,SW(B1)+16+(off); \
57 .spillsp b2,SW(B2)+16+(off); .spillsp b3,SW(B3)+16+(off); \
58 .spillsp b4,SW(B4)+16+(off); .spillsp b5,SW(B5)+16+(off); \
59 .spillsp ar.pfs,SW(AR_PFS)+16+(off); .spillsp ar.lc,SW(AR_LC)+16+(off); \
60 .spillsp @priunat,SW(AR_UNAT)+16+(off); \
61 .spillsp ar.rnat,SW(AR_RNAT)+16+(off); \
62 .spillsp ar.bspstore,SW(AR_BSPSTORE)+16+(off); \
63 .spillsp pr,SW(PR)+16+(off)
H A Dentry.S250 adds r14=SW(R4)+16,sp
260 adds r15=SW(R5)+16,sp
264 add r14=SW(R4)+16,sp
266 st8.spill [r14]=r4,SW(R6)-SW(R4) // spill r4 and prefetch offset 0x1c0
274 adds r15=SW(R5)+16,sp
277 st8.spill [r15]=r5,SW(R7)-SW(R5) // spill r5
279 add r2=SW(F2)+16,sp // r2 = &sw->f2
281 st8.spill [r14]=r6,SW(B0)-SW(R6) // spill r6
283 add r3=SW(F3)+16,sp // r3 = &sw->f3
290 st8.spill [r15]=r7,SW(B2)-SW(R7) // spill r7
301 st8 [r14]=r21,SW(B1)-SW(B0) // save b0
302 st8 [r15]=r23,SW(B3)-SW(B2) // save b2
306 st8 [r14]=r22,SW(B4)-SW(B1) // save b1
307 st8 [r15]=r24,SW(AR_PFS)-SW(B3) // save b3
312 st8 [r14]=r25,SW(B5)-SW(B4) // save b4
313 st8 [r15]=r16,SW(AR_LC)-SW(AR_PFS) // save ar.pfs
340 stf.spill [r2]=f30,SW(AR_UNAT)-SW(F30)
341 stf.spill [r3]=f31,SW(PR)-SW(F31)
342 add r14=SW(CALLER_UNAT)+16,sp
344 st8 [r2]=r29,SW(AR_RNAT)-SW(AR_UNAT) // save ar.unat
345 st8 [r14]=r17,SW(AR_FPSR)-SW(CALLER_UNAT) // save caller_unat
348 st8 [r2]=r19,SW(AR_BSPSTORE)-SW(AR_RNAT) // save ar.rnat
369 adds r2=SW(AR_BSPSTORE)+16,sp
370 adds r3=SW(AR_UNAT)+16,sp
372 adds r14=SW(CALLER_UNAT)+16,sp
373 adds r15=SW(AR_FPSR)+16,sp
375 ld8 r27=[r2],(SW(B0)-SW(AR_BSPSTORE)) // bspstore
376 ld8 r29=[r3],(SW(B1)-SW(AR_UNAT)) // unat
387 ld8 r16=[r2],(SW(PR)-SW(AR_PFS)) // ar.pfs
388 ld8 r17=[r3],(SW(AR_RNAT)-SW(AR_LC)) // ar.lc
H A Dmca_asm.S566 add temp1=SW(F2), regs
567 add temp2=SW(F3), regs
602 stf.spill [temp1]=f30,SW(B2)-SW(F30)
603 stf.spill [temp2]=f31,SW(B3)-SW(F31)
612 st8 [temp1]=temp3,SW(AR_LC)-SW(B4) // save b4
725 add temp1=SW(F2), regs
726 add temp2=SW(F3), regs
761 ldf.fill f30=[temp1],SW(B2)-SW(F30)
762 ldf.fill f31=[temp2],SW(B3)-SW(F31)
769 ld8 temp3=[temp1],SW(AR_LC)-SW(B4) // restore b4
H A Dunwind.c2255 unw.sw_off[unw.preg_index[UNW_REG_PRI_UNAT_GR]] = SW(CALLER_UNAT); unw_init()
2256 unw.sw_off[unw.preg_index[UNW_REG_BSPSTORE]] = SW(AR_BSPSTORE); unw_init()
2257 unw.sw_off[unw.preg_index[UNW_REG_PFS]] = SW(AR_PFS); unw_init()
2258 unw.sw_off[unw.preg_index[UNW_REG_RP]] = SW(B0); unw_init()
2259 unw.sw_off[unw.preg_index[UNW_REG_UNAT]] = SW(CALLER_UNAT); unw_init()
2260 unw.sw_off[unw.preg_index[UNW_REG_PR]] = SW(PR); unw_init()
2261 unw.sw_off[unw.preg_index[UNW_REG_LC]] = SW(AR_LC); unw_init()
2262 unw.sw_off[unw.preg_index[UNW_REG_FPSR]] = SW(AR_FPSR); unw_init()
2263 for (i = UNW_REG_R4, off = SW(R4); i <= UNW_REG_R7; ++i, off += 8) unw_init()
2265 for (i = UNW_REG_B1, off = SW(B1); i <= UNW_REG_B5; ++i, off += 8) unw_init()
2267 for (i = UNW_REG_F2, off = SW(F2); i <= UNW_REG_F5; ++i, off += 16) unw_init()
2269 for (i = UNW_REG_F16, off = SW(F16); i <= UNW_REG_F31; ++i, off += 16) unw_init()
/linux-4.4.14/arch/powerpc/include/asm/
H A Dpte-fsl-booke.h5 /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
11 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
21 #define _PAGE_RW 0x00004 /* S: Write permission (SW) */
H A Dpte-8xx.h34 #define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */
H A Dpte-44x.h32 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
H A Dtlbflush.h12 * - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
H A Dmmu.h53 * properly and needs SW to track and update the LRU state. This
/linux-4.4.14/arch/arm/mach-mmp/
H A Daspenite.c214 KEY(0, 6, KEY_UP), /* SW 4 */
215 KEY(0, 7, KEY_DOWN), /* SW 5 */
216 KEY(1, 6, KEY_LEFT), /* SW 6 */
217 KEY(1, 7, KEY_RIGHT), /* SW 7 */
218 KEY(4, 6, KEY_ENTER), /* SW 8 */
219 KEY(4, 7, KEY_ESC), /* SW 9 */
/linux-4.4.14/drivers/staging/rtl8188eu/include/
H A Dodm_debug.h30 /* They can help SW engineer to develop or trace states changed */
35 /* which help us to debug SW or HW. */
49 /* Normal case with useful information about current SW or HW state. */
51 /* SW protocol state change, dynamic mechanism state change and so on. */
H A Drtw_pwrctrl.h125 rf_off, /* HW/SW Radio OFF or Inactive Power Save */
130 /* RF Off Level for IPS or HW/SW radio off */
H A Dodm.h35 /* Define ODM SW team support flag. */
843 /* 2012/02/14 MH Add to share 88E ra with other SW team. */
/linux-4.4.14/drivers/staging/rtl8712/
H A Drtl871x_led.h72 SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
74 SW_LED_MODE2, /* SW control 1 LED via GPIO0,
76 SW_LED_MODE3, /* SW control 1 LED via GPIO0,
87 enum LED_PIN_871x LedPin; /* Implementation for this SW led. */
H A Drtl8712_syscfg_bitdef.h130 #define SPS1_SWEN BIT(1) /* Enable vsps18 SW Macro Block.*/
H A Dhal_init.c379 r8712_write8(padapter, SPS0_CTRL + 1, 0x43); /* Set SW PFM */ rtl8712_hal_deinit()
/linux-4.4.14/drivers/staging/rtl8723au/include/
H A Dodm_debug.h25 /* So that, they can help SW engineer to develop or trace states changed */
30 /* which help us to debug SW or HW. */
52 /* Normal case with useful information about current SW or HW state. */
54 /* SW protocol state change, dynamic mechanism state change and so on. */
H A Drtw_pwrctrl.h109 rf_off, /* HW/SW Radio OFF or Inactive Power Save */
114 /* RF Off Level for IPS or HW/SW radio off */
H A DHal8723PwrSeq.h46 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},/* disable SW LPS 0x04[10]= 0*/ \
H A Dhal_com.h125 u8 sw_channel_plan, /* channel plan from SW (registry/module param) */
/linux-4.4.14/arch/sparc/include/asm/
H A Dtsunami.h15 * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME|
19 * SW: Enable Software Table Walks 0=off 1=on
H A Ddcu.h13 #define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */
H A Dchafsr.h37 /* SW handled correctable E-cache Tag ECC error */
55 * an uncorrectable error or a SW correctable error occurs and the status
60 * status bit occur, only uncorrectable and SW correctable ones have
119 /* SW Correctable E-cache ECC error for instruction fetch or data access
H A Dswift.h11 #define SWIFT_ST 0x00800000 /* SW tablewalk enable */
H A Dpgtable_64.h138 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
141 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
142 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
156 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
157 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
/linux-4.4.14/arch/mips/pmcs-msp71xx/
H A Dmsp_smp.c26 #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
27 #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for call */
/linux-4.4.14/arch/x86/math-emu/
H A Derrors.c125 printk("SW: backward compatibility\n"); FPU_printall()
127 printk("SW: condition bit 3\n"); FPU_printall()
129 printk("SW: condition bit 2\n"); FPU_printall()
131 printk("SW: condition bit 1\n"); FPU_printall()
133 printk("SW: condition bit 0\n"); FPU_printall()
135 printk("SW: exception summary\n"); FPU_printall()
137 printk("SW: stack fault\n"); FPU_printall()
139 printk("SW: loss of precision\n"); FPU_printall()
141 printk("SW: underflow\n"); FPU_printall()
143 printk("SW: overflow\n"); FPU_printall()
145 printk("SW: divide by zero\n"); FPU_printall()
147 printk("SW: denormalized operand\n"); FPU_printall()
149 printk("SW: invalid operation\n"); FPU_printall()
152 printk(" SW: b=%d st=%d es=%d sf=%d cc=%d%d%d%d ef=%d%d%d%d%d%d\n", partial_status & 0x8000 ? 1 : 0, /* busy */ FPU_printall()
/linux-4.4.14/drivers/video/fbdev/
H A Dep93xx-fb.c31 #define EP93XXFB_VLINES_TOTAL 0x0000 /* SW locked */
32 #define EP93XXFB_VSYNC 0x0004 /* SW locked */
33 #define EP93XXFB_VACTIVE 0x0008 /* SW locked */
34 #define EP93XXFB_VBLANK 0x0228 /* SW locked */
35 #define EP93XXFB_VCLK 0x000c /* SW locked */
38 #define EP93XXFB_HCLKS_TOTAL 0x0010 /* SW locked */
39 #define EP93XXFB_HSYNC 0x0014 /* SW locked */
40 #define EP93XXFB_HACTIVE 0x0018 /* SW locked */
41 #define EP93XXFB_HBLANK 0x022c /* SW locked */
42 #define EP93XXFB_HCLK 0x001c /* SW locked */
50 #define EP93XXFB_LINE_CARRY 0x003c /* SW locked */
55 #define EP93XXFB_ATTRIBS 0x0024 /* SW locked */
56 #define EP93XXFB_SWLOCK 0x007c /* SW locked */
/linux-4.4.14/arch/powerpc/boot/
H A Dplanetcore.h17 #define PLANETCORE_KEY_SWITCH "SW"
/linux-4.4.14/arch/arm/mach-orion5x/
H A Dls-chl-setup.c261 MPP7_GPIO, /* SW INIT */
262 MPP8_GPIO, /* SW POWER */
264 MPP10_GPIO, /* SW AUTO POWER */
269 MPP15_GPIO, /* SW FUNC */
/linux-4.4.14/arch/mips/kernel/
H A Dsmp-bmips.c64 /* SW interrupts 0,1 are used for interprocessor signaling */
91 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other bmips_smp_setup()
109 /* enable raceless SW interrupts */ bmips_smp_setup()
118 /* clear any pending SW interrupts */ bmips_smp_setup()
268 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
304 * We use one inbound SW IRQ for each CPU.
397 * wait for SW interrupt from bmips_boot_secondary(), then jump play_dead()
/linux-4.4.14/arch/powerpc/kernel/
H A Dalign.c45 #define SW 0x20 /* byte swap */ macro
135 { 4, LD+SW }, /* 10 0 1000: lwbrx */
137 { 4, ST+SW }, /* 10 0 1010: stwbrx */
139 { 2, LD+SW }, /* 10 0 1100: lhbrx */
141 { 2, ST+SW }, /* 10 0 1110: sthbrx */
270 if (swiz == 0 && (flags & SW)) emulate_multiple()
287 flags ^= SW; emulate_multiple()
299 bswiz = (flags & SW)? 3: 0; emulate_multiple()
358 if (flags & SW) emulate_fp_pair()
385 if (flags & SW) emulate_lq_stq()
588 if (flags & SW) { emulate_spe()
669 if (flags & SW) { emulate_vsx()
684 if (flags & SW) emulate_vsx()
814 flags = LD+SW; fix_alignment()
818 flags = ST+SW; fix_alignment()
824 flags ^= SW; fix_alignment()
864 flags |= SW; fix_alignment()
971 if (flags & SW) { fix_alignment()
988 switch (flags & ~(U|SW)) { fix_alignment()
/linux-4.4.14/drivers/net/ethernet/intel/i40evf/
H A Di40e_prototype.h37 * has happened and will assist in the early SW and FW
86 /* prototype for functions used for SW locks */
/linux-4.4.14/arch/cris/include/arch-v10/arch/
H A Dmmu.h45 * things become less confusing in combination with the SW-based
58 /* Bits the HW doesn't care about but the kernel uses them in SW */
/linux-4.4.14/arch/s390/mm/
H A Dhugetlbpage.c32 * SW-bits: p present, y young, d dirty, r read, w write, s special, __pte_to_pmd()
70 * SW-bits: p present, y young, d dirty, r read, w write, s special, __pmd_to_pte()
/linux-4.4.14/drivers/pci/host/
H A Dpcie-iproc.h39 * @need_ob_cfg: indidates SW needs to configure the outbound mapping window
H A Dpcie-iproc.c228 * Some iProc SoCs require the SW to configure the outbound address mapping
/linux-4.4.14/arch/x86/include/asm/
H A Dfloppy.h30 #define SW fd_routine[use_virtual_dma & 1] macro
42 #define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
43 #define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
44 #define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
H A Dmwait.h52 * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0
/linux-4.4.14/include/linux/platform_data/
H A Dmtd-nand-omap2.h25 * 1-bit ECC: calculation and correction by SW
H A Ddma-ste-dma40.h128 * @soft_lli_chans: A vector, that marks physical channels will use LLI by SW
/linux-4.4.14/arch/mips/include/asm/sn/sn0/
H A Dip27.h17 * Simple definitions for the masks which remove SW bits from pte.
/linux-4.4.14/arch/parisc/include/asm/
H A Dfloppy.h41 #define SW fd_routine[use_virtual_dma&1] macro
53 #define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
54 #define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
55 #define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
/linux-4.4.14/arch/arm/mach-imx/
H A Dcpuidle-imx6sx.c77 * and some margin for SW execution, here set it
/linux-4.4.14/arch/sh/boards/
H A Dboard-magicpanelr2.c70 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ setup_chip_select()
76 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ setup_chip_select()
82 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ setup_chip_select()
88 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ setup_chip_select()
94 /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ setup_chip_select()
/linux-4.4.14/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_x540.c581 /* SW only mask does not have FW bit pair */ ixgbe_acquire_swfw_sync_X540()
588 /* SW NVM semaphore bit is used for access to all ixgbe_acquire_swfw_sync_X540()
610 /* Failed to get SW only semaphore */ ixgbe_acquire_swfw_sync_X540()
612 hw_dbg(hw, "Failed to get SW only semaphore\n"); ixgbe_acquire_swfw_sync_X540()
616 /* If the resource is not released by the FW/HW the SW can assume that ixgbe_acquire_swfw_sync_X540()
617 * the FW/HW malfunctions. In that case the SW should set the SW bit(s) ixgbe_acquire_swfw_sync_X540()
631 /* If the resource is not released by other SW the SW can assume that ixgbe_acquire_swfw_sync_X540()
632 * the other SW malfunctions. In that case the SW should clear all SW ixgbe_acquire_swfw_sync_X540()
680 * Sets the hardware semaphores so SW/FW can gain control of shared resources
705 /* Now get the semaphore between SW/FW through the REGSMP bit */ ixgbe_get_swfw_sync_semaphore()
714 /* Release semaphores and return error if SW NVM semaphore ixgbe_get_swfw_sync_semaphore()
H A Dixgbe_82599.c197 * FW/SW lock. It is assumed this lock will be freed with the next
207 /* If LESM is on then we need to hold the SW/FW semaphore. */ prot_autoc_read_82599()
225 * @locked: bool to indicate whether the SW/FW lock was already taken by
228 * This part (82599) may need to hold a the SW/FW lock around all writes to
256 /* Free the SW/FW semaphore as we either grabbed it here or prot_autoc_write_82599()
978 * Issue global reset to the MAC. Needs to be SW reset if link is up. ixgbe_reset_hw_82599()
2025 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
/linux-4.4.14/drivers/media/platform/vivid/
H A Dvivid-radio-common.c55 /* Band SW */
125 * For SW and FM there is a channel every 1000 kHz, for AM there is one vivid_radio_calc_sig_qual()
H A Dvivid-radio-tx.c119 strlcpy(a->name, "AM/FM/SW Transmitter", sizeof(a->name)); vidioc_g_modulator()
H A Dvivid-radio-rx.c237 strlcpy(vt->name, "AM/FM/SW Receiver", sizeof(vt->name)); vivid_radio_rx_g_tuner()
/linux-4.4.14/drivers/net/ethernet/sun/
H A Dsunhme.h440 unsigned short sw_bmcr; /* SW copy of BMCR */
441 unsigned short sw_bmsr; /* SW copy of BMSR */
442 unsigned short sw_physid1; /* SW copy of PHYSID1 */
443 unsigned short sw_physid2; /* SW copy of PHYSID2 */
444 unsigned short sw_advertise; /* SW copy of ADVERTISE */
445 unsigned short sw_lpa; /* SW copy of LPA */
446 unsigned short sw_expansion; /* SW copy of EXPANSION */
447 unsigned short sw_csconfig; /* SW copy of CSCONFIG */
H A Dsunbmac.h308 unsigned short sw_bmsr; /* SW copy of PHY BMSR */
309 unsigned short sw_bmcr; /* SW copy of PHY BMCR */
/linux-4.4.14/drivers/clk/bcm/
H A Dclk-iproc.h46 * Some PLLs require the PLL SW override bit to be set before changes can be
125 * To enable SW control of the PLL
H A Dclk-kona.h57 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
140 * SW means the state of this gate can be software controlled
149 #define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
165 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
177 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
188 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
198 .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
/linux-4.4.14/arch/m68k/include/asm/
H A Dm5206sim.h49 #define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */
50 #define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */
H A Dm5407sim.h28 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
29 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
H A Dm5307sim.h28 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
29 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
H A Dm525xsim.h36 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
37 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
/linux-4.4.14/drivers/staging/rtl8188eu/hal/
H A Drtl8188eu_led.c39 usb_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0) | BIT(5) | BIT(6)); /* SW control led0 on. */ SwLedOn()
H A Dodm_HWConfig.c41 /* IF other SW team do not support the feature, remove this section.?? */ odm_SignalScaleMapping_92CSeries()
/linux-4.4.14/drivers/regulator/
H A Dmc13xxx.h108 MC13xxx_DEFINE(SW, _name, _reg, _vsel_reg, _voltages, ops)
H A Dtps80031-regulator.c579 /* Provide SW control Ops if VBUS is SW control */ tps80031_regulator_config()
H A Dab8500-ext.c71 * To satisfy both HW high power request and SW request, the regulator ab8500_ext_regulator_enable()
/linux-4.4.14/drivers/media/radio/
H A Dradio-raremono.c34 * 'Thanko's Raremono' is a Japanese si4734-based AM/FM/SW USB receiver:
48 MODULE_DESCRIPTION("Thanko's Raremono AM/FM/SW Receiver USB driver");
105 /* Band SW */
227 strlcpy(v->name, "AM/FM/SW", sizeof(v->name)); vidioc_g_tuner()
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb3/
H A Dadapter.h116 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
170 unsigned int cleaned; /* total # of descs SW has reclaimed */
171 unsigned int stop_thres; /* SW TX queue suspend threshold */
177 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
H A Dsge.c109 struct tx_sw_desc { /* SW state per Tx descriptor */
117 struct rx_sw_desc { /* SW state per Rx descriptor */
226 * the SW descriptor state (assorted indices). The send functions
404 * @sd: the SW Rx descriptor to write
408 * Add a buffer of the given length to the supplied HW and SW Rx
601 * @sw_size: the size of the SW state associated with each ring element
603 * @metadata: address of the array holding the SW state for the ring
607 * space for its HW descriptors plus, optionally, space for the SW state
611 * of the SW ring.
668 * Release the HW and SW resources associated with an SGE queue set, such
1171 cntrl |= F_TXPKT_IPCSUM_DIS; /* SW calculates IP csum */ write_tx_pkt_wr()
2147 * HW coalesces credits, we don't do any extra SW coalescing.
3279 * Performs one-time initialization of SGE SW state. Includes determining
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dbcm-ns2.h45 /* GENPLL SW clock channel ID */
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
H A Dbcm-ns2.h45 /* GENPLL SW clock channel ID */
/linux-4.4.14/include/dt-bindings/clock/
H A Dbcm-ns2.h45 /* GENPLL SW clock channel ID */
/linux-4.4.14/arch/s390/include/asm/
H A Dpgtable.h187 #define _PAGE_PRESENT 0x001 /* SW pte present bit */
188 #define _PAGE_YOUNG 0x004 /* SW pte young bit */
189 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */
190 #define _PAGE_READ 0x010 /* SW pte read bit */
191 #define _PAGE_WRITE 0x020 /* SW pte write bit */
192 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */
193 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */
197 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */
235 * SW-bits: p present, y young, d dirty, r read, w write, s special,
287 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */
288 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */
291 #define _SEGMENT_ENTRY_READ 0x0002 /* SW segment read bit */
292 #define _SEGMENT_ENTRY_WRITE 0x0001 /* SW segment write bit */
295 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */
297 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */
318 * SW-bits: y young, d dirty, r read, w write
/linux-4.4.14/arch/sh/include/mach-common/mach/
H A Durquell.h54 #define MDSWMR_OFS 0x1040 /* MODE SW monitor register */
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dbcm-ns2.h45 /* GENPLL SW clock channel ID */
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dbcm-ns2.h45 /* GENPLL SW clock channel ID */
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dbcm-ns2.h45 /* GENPLL SW clock channel ID */
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dbcm-ns2.h45 /* GENPLL SW clock channel ID */
/linux-4.4.14/arch/arm/mach-berlin/
H A Dplatsmp.c92 * Write the secondary startup address into the SW reset address berlin_smp_prepare_cpus()
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/
H A Ddebug.h58 *about current SW or HW state.
61 *SW protocol state change, dynamic
94 #define COMP_SWAS BIT(19) /*For SW Antenna Switch */
/linux-4.4.14/drivers/net/wimax/i2400m/
H A Dop-rfkill.c32 * - implement indications from the stack to change the SW RF Kill
66 * WiMAX stack operation: implement SW RFKill toggling
194 dev_err(dev, "HW BUG? Unknown RF SW state 0x%x\n", sw); i2400m_report_tlv_rf_switches_status()
/linux-4.4.14/drivers/net/ethernet/ezchip/
H A Dnps_enet.h49 /* ct: SW sets to indicate frame ready in Tx buffer for
71 * SW resets to indicate host read received frame
278 * @tx_packet_sent: SW indication if frame is being sent.
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Datombios.h227 USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
228 USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */
244 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
246 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
249 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
250 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
251 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
252 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
254 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
255 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
256 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
257 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
258 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
259 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
261 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
262 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
265 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
266 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
267 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1
268 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
269 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
270 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
273 USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1
278 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
279 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
280 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
281 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
283 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
284 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
286 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
291 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
292 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
293 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
294 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
295 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
299 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
300 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
301 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
302 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
303 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
304 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
305 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
307 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
309 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
310 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
311 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
312 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
313 USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
315 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
316 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
317 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
318 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
319 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
320 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
321 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
730 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
2353 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
2355 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info
2357 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1
2359 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
2360 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
2361 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
2363 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600
2364 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
2367 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
2368 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
2370 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
2371 USHORT Object_Header; // Shared by various SW components,latest version 1.1
2379 USHORT IntegratedSystemInfo; // Shared by various SW components
2381 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
2382 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
2812 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
2813 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
2815 SW components can access the IGP system infor structure in the same way as before
2925 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
3175 // = 0, [6:0]=SW assisted I2C ID
3179 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3469 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3578 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3586 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init
3587 #define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init
4886 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
4889 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
4890 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
4895 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
5110 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5113 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
5114 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5119 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
5311 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5314 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
5315 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5320 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
5439 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
5442 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
5447 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
5450 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
5480 //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type.
6816 /****************************SW I2C CNTL DEFINITIONS**********************/
7627 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
7768 // Following definitions are for compatibility issue in different SW components.
H A Ddce3_1_afmt.c177 HDMI0_ACR_SOURCE | /* select SW CTS value */ dce3_2_hdmi_update_acr()
H A Dradeon_irq.c204 /* SW interrupt */ radeon_driver_irq_handler()
/linux-4.4.14/drivers/gpu/drm/amd/include/
H A Datombios.h221 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
222 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position
234 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
236 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
239 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
240 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
241 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
242 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
244 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
245 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
246 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
247 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
248 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
249 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
251 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
252 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
255 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
256 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
257 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1
258 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
259 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
260 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
263 USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1
268 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
269 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
270 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
271 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
273 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
274 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
276 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
281 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
282 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
283 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
284 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
285 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
289 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
290 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
291 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
292 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
293 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
294 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
295 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
297 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
299 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
300 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
301 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
302 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
303 USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1
305 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
306 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
307 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
308 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
309 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
310 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
311 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
743 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
2421 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
2423 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info
2425 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1
2427 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
2428 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
2429 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
2431 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600
2432 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
2435 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
2436 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
2438 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
2439 USHORT Object_Header; // Shared by various SW components,latest version 1.1
2447 USHORT IntegratedSystemInfo; // Shared by various SW components
2449 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
2450 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
2895 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
2896 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
2898 SW components can access the IGP system infor structure in the same way as before
3008 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
3282 // = 0, [6:0]=SW assisted I2C ID
3286 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3579 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3699 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3707 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init
3708 #define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init
5145 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5148 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
5149 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5154 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
5374 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5377 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
5378 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5383 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
5576 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5579 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
5580 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5585 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
5858 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
5861 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
5866 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
5869 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
5899 //Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type.
7350 /****************************SW I2C CNTL DEFINITIONS**********************/
8196 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
8341 // Following definitions are for compatiblity issue in different SW components.
/linux-4.4.14/drivers/net/ethernet/intel/igb/
H A De1000_i210.c48 /* Get the SW semaphore */ igb_get_hw_semaphore_i210()
59 /* In rare circumstances, the SW semaphore may already be held igb_get_hw_semaphore_i210()
130 * igb_acquire_swfw_sync_i210 - Acquire SW/FW semaphore
134 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
176 * igb_release_swfw_sync_i210 - Release SW/FW semaphore
180 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
/linux-4.4.14/drivers/media/i2c/
H A Dsaa7185.c268 /* SW: a slight sync problem... */ saa7185_s_routing()
277 /* SW: a slight sync problem... */ saa7185_s_routing()
344 /* SW: output off is active */ saa7185_remove()
/linux-4.4.14/arch/x86/include/uapi/asm/
H A Dsigcontext.h26 * are reserved for SW usage. On CPUs supporting XSAVE/XRSTOR, these bytes are
224 * depending on the FP_XSTATE_MAGIC1 encoded in the SW reserved
267 * depending on the FP_XSTATE_MAGIC1 encoded in the SW reserved
/linux-4.4.14/arch/x86/kernel/fpu/
H A Dsignal.c84 /* Setup the bytes not touched by the [f]xsave and reserved for SW. */ save_xstate_epilog()
150 * For [f]xsave state, update the SW reserved fields in the [f]xsave frame
380 * Prepare the SW reserved portion of the fxsave memory layout, indicating
/linux-4.4.14/drivers/vfio/platform/reset/
H A Dvfio_platform_amdxgbe.c117 pr_warn("%s MAC SW reset failed\n", __func__); vfio_platform_amdxgbe_reset()
/linux-4.4.14/drivers/misc/
H A Dhmc6352.c70 return compass_store(dev, buf, count, "SW"); compass_power_mode_store()
/linux-4.4.14/drivers/net/ethernet/intel/i40e/
H A Di40e_fcoe.h98 /* DDP SW context struct */
H A Di40e_fcoe.c158 * Unmap the scatter-gather list associated with the given SW DDP context
183 * i40e_fcoe_ddp_clear - clear the given SW DDP context
184 * @ddp - SW DDP context
617 * requested by SW to the HW is successful or not and take actions accordingly.
996 * a matching SW DDP context for this command. DDP is applicable
1099 * @ddp: the SW DDP context for this DDP
1138 * a matching SW DDP context for this command. DDP is applicable
H A Di40e_prototype.h37 * has happened and will assist in the early SW and FW
302 /* prototype for functions used for SW locks */
/linux-4.4.14/net/wimax/
H A Dstack.c194 pr_err("SW BUG! Forbidden state change %u -> %u\n", __check_new_state()
215 dev_err(dev, "SW BUG: requesting invalid state %u\n", __wimax_state_change()
284 dev_err(dev, "SW BUG: wimax_dev %p is in unknown state %u\n", __wimax_state_change()
293 dev_err(dev, "SW BUG: wimax_dev %p entering NULL state " __wimax_state_change()
H A Dop-rfkill.c370 /* If there is no SW toggle op, SW RFKill is always on */ wimax_rfkill_add()
/linux-4.4.14/arch/arm/mach-omap2/
H A Domap_phy_internal.c45 * prevent core retention if not disabled by SW. USB driver will
H A Domap-headsmp.S106 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
H A Ddma.c162 * Workaround: SW should explicitely disable the channel. configure_dma_errata()
H A Domap-smp.c130 * GIC restoration will cause a problem to CPU0 Non-Secure SW. omap4_boot_secondary()
H A Dpowerdomains44xx_data.c325 * The following power domains are not under SW control
H A Dpowerdomains54xx_data.c299 * The following power domains are not under SW control
H A Dpowerdomains7xx_data.c415 * The following power domains are not under SW control
/linux-4.4.14/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/
H A DEventClass.py8 # is a HW base Intel x86 PEBS event, and user could add more SW/HW
/linux-4.4.14/drivers/tty/
H A Dn_tracerouter.c63 * n_tracerouter_open() - Called when a tty is opened by a SW entity.
69 * Caveats: This should only be opened one time per SW entity.
H A Dn_tracesink.c61 * n_tracesink_open() - Called when a tty is opened by a SW entity.
72 * SW entity calls it.
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dpwrseq.h66 /* disable SW LPS 0x04[10]=0*/ \
150 /*0x04[10] = 1, enable SW LPS*/ \
H A Dsw.c398 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
/linux-4.4.14/drivers/net/wireless/cw1200/
H A Dcw1200_sdio.c161 pr_debug("SW IRQ subscribe\n"); cw1200_sdio_irq_subscribe()
176 pr_debug("SW IRQ unsubscribe\n"); cw1200_sdio_irq_unsubscribe()
H A Dcw1200_spi.c253 pr_debug("SW IRQ subscribe\n"); cw1200_spi_irq_subscribe()
278 pr_debug("SW IRQ unsubscribe\n"); cw1200_spi_irq_unsubscribe()
/linux-4.4.14/drivers/dma/
H A Dmic_x100_dma.h37 * Four channels are assigned for host SW use & the remaining for MIC SW.
/linux-4.4.14/arch/x86/kernel/cpu/
H A Dperf_event_intel_lbr.c507 * SW filter is used:
573 * all branches, may need the help of the SW filter
617 * setup SW LBR filter intel_pmu_setup_lbr_filter()
925 * SW branch filter usage: intel_pmu_lbr_init_core()
943 * SW branch filter usage: intel_pmu_lbr_init_nhm()
964 * SW branch filter usage: intel_pmu_lbr_init_snb()
998 * SW branch filter usage: intel_pmu_lbr_init_skl()
1026 * SW branch filter usage: intel_pmu_lbr_init_atom()
/linux-4.4.14/arch/mips/mti-malta/
H A Dmalta-int.c195 #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
197 #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
H A Dmalta-setup.c133 pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); plat_enable_iocoherency()
/linux-4.4.14/drivers/vme/bridges/
H A Dvme_tsi148.h1008 #define TSI148_LCSR_VICR_IRQL_M (7<<8) /* VMEbus SW IRQ Level Mask */
1009 #define TSI148_LCSR_VICR_IRQL_1 (1<<8) /* VMEbus SW IRQ Level 1 */
1010 #define TSI148_LCSR_VICR_IRQL_2 (2<<8) /* VMEbus SW IRQ Level 2 */
1011 #define TSI148_LCSR_VICR_IRQL_3 (3<<8) /* VMEbus SW IRQ Level 3 */
1012 #define TSI148_LCSR_VICR_IRQL_4 (4<<8) /* VMEbus SW IRQ Level 4 */
1013 #define TSI148_LCSR_VICR_IRQL_5 (5<<8) /* VMEbus SW IRQ Level 5 */
1014 #define TSI148_LCSR_VICR_IRQL_6 (6<<8) /* VMEbus SW IRQ Level 6 */
1015 #define TSI148_LCSR_VICR_IRQL_7 (7<<8) /* VMEbus SW IRQ Level 7 */
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dadapter.h141 struct rx_sw_desc *sdesc; /* address of SW RX descriptor ring */
234 unsigned int cidx; /* SW consumer index */
247 struct tx_sw_desc *sdesc; /* address of SW TX descriptor ring */
475 * t4_os_set_hw_addr - store a port's MAC address in SW
480 * Store the Ethernet address of the given port in SW. Called by the common
/linux-4.4.14/drivers/net/ethernet/intel/e1000e/
H A Dregs.h224 #define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */
228 #define E1000_SWSM 0x05B50 /* SW Semaphore */
230 /* Driver-only SW semaphore (not used by BOOT agents) */
H A D80003es2lan.c284 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
288 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
329 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
333 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
944 /* SW Reset the PHY so all changes take effect */ e1000_copper_link_setup_gg82563_80003es2lan()
H A Ddefines.h54 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
210 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
211 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
389 /* SW Semaphore Register */
H A Dmac.c655 * SW defined pins. If there is no SW over-ride of the flow e1000_set_default_fc_generic()
815 * milliseconds even if the other end is doing it in SW). e1000_poll_fiber_serdes_link_generic()
880 /* For these adapters, the SW definable pin 1 is set when the optics e1000e_setup_fiber_serdes_link()
1378 /* Get the SW semaphore */ e1000e_get_hw_semaphore()
1544 * e1000e_setup_led_generic - Configures SW controllable LED
1547 * This prepares the SW controllable LED for use and saves the current state
H A Dich8lan.h229 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */
/linux-4.4.14/drivers/scsi/snic/
H A Dvnic_wq.h87 /* how many does SW own? */ svnic_wq_desc_avail()
/linux-4.4.14/drivers/scsi/fnic/
H A Dvnic_wq.h98 /* how many does SW own? */ vnic_wq_desc_avail()
H A Dvnic_rq.h107 /* how many does SW own? */ vnic_rq_desc_avail()
/linux-4.4.14/drivers/iio/imu/inv_mpu6050/
H A Dinv_mpu_ring.c189 /* Flush HW and SW FIFOs. */ inv_mpu6050_read_fifo()
/linux-4.4.14/drivers/infiniband/hw/cxgb3/
H A Dcxio_wr.h652 #define TPT_ERR_SWFLUSH 0xC /* SW FLUSHED */
699 struct t3_swsq *sq; /* SW SQ */
704 struct t3_swrq *rq; /* SW RQ (holds consumer wr_ids */
707 struct t3_swrq *rq_oldest_wr; /* oldest wr on the SW RQ */
/linux-4.4.14/drivers/hwmon/
H A Dab8500.c8 * be changed by SW), an interrupt is set, and if no further action is taken
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dled.c97 rtl_write_byte(rtlpriv, ledreg, ledcfg); /*SW control led0 on.*/ rtl8812ae_sw_led_on()
H A Dpwrseq.h49 /* disable SW LPS 0x04[10]=0*/}, \
222 /*0x04[10] = 0, enable SW LPS PCIE only*/}, \
409 /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/}, \
546 /*0x04[10] = 1, enable SW LPS*/}, \
H A Dsw.c447 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
/linux-4.4.14/drivers/net/ethernet/tehuti/
H A Dtehuti.c13 * RX HW/SW interaction overview
17 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
21 * filled by HW and is readen by SW. Each descriptor holds status and ID.
32 * RX SW Data Structures
34 * skb db - used to keep track of all skbs owned by SW and their dma addresses.
42 * RX SW Execution Flow
520 netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n"); bdx_sw_reset()
984 * bdx_rx_init - initialize RX all related HW and SW resources
1339 * TX HW/SW interaction overview
1348 * RX SW Data Structures
1350 * txdb - used to keep track of all skbs owned by SW and their dma addresses.
1358 * TX SW Execution Flow
1363 * When packet is sent, HW write us TXF descriptor and SW frees original skb.
1365 * SW deploys "tx level" technique.
1367 * For every sent packet, SW gets its TXD descriptor sizei
1369 * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
/linux-4.4.14/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac100_dma.c41 /* DMA SW reset */ dwmac100_dma_init()
H A Ddwmac1000_dma.c39 /* DMA SW reset */ dwmac1000_dma_init()
/linux-4.4.14/drivers/net/ethernet/cisco/enic/
H A Dvnic_wq.h105 /* how many does SW own? */ vnic_wq_desc_avail()
H A Dvnic_rq.h102 /* how many does SW own? */ vnic_rq_desc_avail()
/linux-4.4.14/drivers/clk/qcom/
H A Dgdsc.c171 * Disable SW override: Use hardware state-machine for sequencing. gdsc_init()
/linux-4.4.14/arch/mips/include/asm/octeon/
H A Dcvmx-asm.h98 * its dirty bit for a block. Basically, SW is telling HW that the
H A Dcvmx-pow.h142 * Before issuing a *_NSCHED operation, SW must guarantee
145 * hardware provides the opsdone bit and swdone bit for SW
146 * polling. After issuing a *_NSCHED operation, SW must
162 * Before issuing a *_NSCHED operation, SW must guarantee that
165 * provides the opsdone bit and swdone bit for SW
166 * polling. After issuing a *_NSCHED operation, SW must
1184 * ADDWQ command that only contains the pointer). SW must never use
1939 * SW can choose to immediately switch to an ORDERED tag
2022 * SW can choose to immediately switch to an ORDERED tag
2099 * Number of bits of the tag used by software. The SW bits are always
/linux-4.4.14/arch/arm/kernel/
H A Dmachine_kexec.c45 * Validate that if the current HW supports SMP, then the SW supports machine_kexec_prepare()
H A Dreboot.c90 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb/
H A Dsge.c160 * SW Context Command and Freelist Queue Descriptors
175 * SW command, freelist and response rings
182 unsigned int cleaned; /* total # of descs SW has reclaimed */
183 unsigned int stop_thres; /* SW TX queue suspend threshold */
184 u16 pidx; /* producer index (SW) */
189 struct cmdQ_ce *centries; /* SW command context descriptor Q */
197 u16 pidx; /* producer index (SW) */
204 struct freelQ_ce *centries; /* SW freelist context descriptor Q */
211 u16 cidx; /* consumer index (SW) */
223 /* T204 TX SW scheduler */
1855 cpl->ip_csum_dis = 1; /* SW calculates IP csum */ t1_start_xmit()
/linux-4.4.14/drivers/staging/rtl8192u/ieee80211/
H A Drtl819x_Qos.h330 eAcmWay0_SwAndHw = 0, // By SW and HW.
332 eAcmWay2_SW = 2, // By SW.
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dpwrseq.h70 /* disable SW LPS 0x04[10]=0*/ \
158 /*0x04[10] = 1, enable SW LPS*/ \
H A Dsw.c382 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
/linux-4.4.14/drivers/net/ethernet/mellanox/mlx5/core/
H A Den.h90 /* SW counters */
128 /* SW counters */
/linux-4.4.14/drivers/net/vmxnet3/
H A Dvmxnet3_int.h95 VMNET_CAP_SW_TSO = 0x0040, /* Supports SW TCP Segmentation */
99 VMNET_CAP_SW_VLAN = 0x0400, /* VLAN tagging/untagging in SW */
/linux-4.4.14/drivers/net/wireless/ath/ath10k/
H A Dhtt.h70 * The HTT tx MSDU descriptor is created by the host HTT SW for each
1020 /* Num MPDUs requed by SW */
1408 * used exclusively by the host SW. This ring
1410 * between the host SW and the MAC HW. The host SW
1433 * rx buffers the host SW provides for the MAC HW to
1457 * alloc_idx - where HTT SW has deposited empty buffers
1467 /* where HTT SW has processed bufs filled by rx MAC DMA */
/linux-4.4.14/drivers/block/paride/
H A Dppc6lnx.c71 // 0 = PPC Uni SW
73 // 2 = PPC Bi SW
/linux-4.4.14/include/uapi/sound/
H A Dasoc.h217 * FE or BE Stream configuration supported by SW/FW
373 * Describes SW/FW specific features of PCM (FE DAI & DAI link).
/linux-4.4.14/include/uapi/linux/
H A Dmdio.h131 #define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */
158 #define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */
H A Dnubus.h43 /* Known <Cat,Type,SW,HW> tuples: (according to TattleTech and Slots)
/linux-4.4.14/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-util.c226 /* Disable backpressure based on queued buffers. It needs SW support */ cvmx_helper_setup_red()
240 /* Shutoff the dropping based on the per port page count. SW isn't cvmx_helper_setup_red()
/linux-4.4.14/drivers/staging/rtl8192u/
H A Dr8192U.h817 SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
818 SW_LED_MODE1, /* SW control for PCI Express */
819 SW_LED_MODE2, /* SW control for Cameo. */
820 SW_LED_MODE3, /* SW control for RunTop. */
821 SW_LED_MODE4, /* SW control for Netcore. */
/linux-4.4.14/drivers/hid/
H A Dhid-corsair.c275 macro_mode = "SW"; k90_show_macro_mode()
295 if (strncmp(buf, "SW", 2) == 0) k90_store_macro_mode()
/linux-4.4.14/drivers/media/platform/s5p-jpeg/
H A Djpeg-regs.h122 /* JPEG SW reset register */
562 /* JPEG SW reset register */
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Dpwrseq.h81 /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
222 /*0x04[10] = 1, enable SW LPS*/ \
H A Dsw.c401 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
/linux-4.4.14/drivers/net/wireless/iwlwifi/mvm/
H A Dfw-api-coex.h181 * @wifi_tx_prio_boost: SW boost of wifi tx priority
182 * @wifi_rx_prio_boost: SW boost of wifi rx priority
/linux-4.4.14/include/uapi/rdma/hfi/
H A Dhfi1_user.h385 * SW KDETH header.
386 * swdata is SW defined portion.
/linux-4.4.14/drivers/usb/c67x00/
H A Dc67x00-sched.c54 * Hardware parts are little endiannes, SW in CPU endianess.
72 /* SW part */
623 /* SW part */ c67x00_create_td()
640 /* SW part */ c67x00_create_td()
/linux-4.4.14/drivers/staging/comedi/drivers/
H A Dni_660x.c215 {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B},
216 {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B},
250 {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B},
251 {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B},
/linux-4.4.14/drivers/misc/mic/host/
H A Dmic_debugfs.c41 mdev->id, "SMPT entry", "SW DMA addr", "RefCount"); mic_smpt_show()
/linux-4.4.14/drivers/i2c/busses/
H A Di2c-bcm2835.c51 #define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */
/linux-4.4.14/drivers/infiniband/hw/cxgb4/
H A Dcq.c351 * unfortunately. Need to move pertinent HW CQEs to the SW CQ but c4iw_flush_hw_cq()
594 * in the SW SQ. Then the SW SQ is walked to move any poll_cq()
595 * now in-order completions into the SW CQ. This handles poll_cq()
/linux-4.4.14/drivers/mfd/
H A Dab8500-gpadc.c305 * @conv_type: selected conversion type (HW or SW conversion)
343 * @conv_type: selected conversion type (HW or SW conversion)
486 /* Start SW conversion */ ab8500_gpadc_double_read_raw()
534 "gpadc_conversion: only SW double conversion supported\n"); ab8500_gpadc_double_read_raw()
/linux-4.4.14/drivers/misc/genwqe/
H A Dcard_ddcb.h54 __be32 icrc_hsi_shi_32; /* iCRC, Hardware/SW interlock */
/linux-4.4.14/drivers/net/wireless/rt2x00/
H A Drt2x00config.c122 * When the caller tries to send the SW diversity, rt2x00lib_config_antenna()
/linux-4.4.14/drivers/net/wireless/ath/ath9k/
H A Dar9003_eeprom.h202 /* SW controlled internal regulator fields */
H A Ddebug.h152 * @a_retries: No. of AMPDUs retried (SW)
/linux-4.4.14/drivers/net/ethernet/smsc/
H A Dsmc911x.h365 #define INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */
366 #define INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */
487 #define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */
495 #define PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */
/linux-4.4.14/drivers/net/ethernet/broadcom/
H A Dbcm63xx_enet.h89 * SW MIB Counters register definitions
/linux-4.4.14/drivers/pinctrl/
H A Dpinctrl-u300.c258 PINCTRL_PIN(71, "PO ANT SW 2"),
259 PINCTRL_PIN(72, "PO ANT SW 3"),
260 PINCTRL_PIN(73, "PO ANT SW 0"),
261 PINCTRL_PIN(74, "PO ANT SW 1"),
/linux-4.4.14/arch/arm64/kernel/
H A Dprocess.c98 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
/linux-4.4.14/arch/blackfin/mach-bf518/include/mach/
H A Danomaly.h55 /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
/linux-4.4.14/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_dbgmgr.h114 * a SW object combining a user-mode provided "syncvar" and a scheduler event
/linux-4.4.14/net/mac80211/
H A Dkey.c43 * There is currently no way of knowing whether a key is handled in SW
88 * the xmit key is added and SW encryption kicks off. increment_tailroom_need_count()
91 * just before xmit one of the key is deleted and SW encryption kicks increment_tailroom_need_count()
94 * In both the above case SW encryption will find not enough space for increment_tailroom_need_count()
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4.h490 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
559 struct sge_eth_rxq { /* SW Ethernet Rx queue */
572 struct sge_ofld_rxq { /* SW offload Rx queue */
587 unsigned int cidx; /* SW consumer index */
593 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
922 * t4_set_hw_addr - store a port's MAC address in SW
927 * Store the Ethernet address of the given port in SW. Called by the common
/linux-4.4.14/arch/powerpc/mm/
H A Dtlb_low_64e.S205 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
503 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
744 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
798 * with the current scheme when using SW load.
931 * always called as a second level tlb miss for SW load or as a first
/linux-4.4.14/drivers/net/ethernet/intel/e1000/
H A De1000_hw.c723 * SW defined pins. If there is no SW over-ride of the flow e1000_setup_link()
758 * polarity value for the SW controlled pins, and setup the e1000_setup_link()
760 * This is needed because one of the SW controlled pins is used for e1000_setup_link()
926 * it in SW). For internal serdes, we just assume a signal is present, e1000_setup_fiber_serdes_link()
972 /* SW reset the PHY so all changes take effect */ e1000_copper_link_rtl_setup()
1318 /* SW Reset the PHY so all changes take effect */ e1000_copper_link_mgp_setup()
2411 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be e1000_check_for_link()
3040 /* We'll need to use the SW defined pins to shift the write e1000_write_phy_reg_ex()
4516 * Prepares SW controlable LED for use and saves the current state of the LED.
4566 * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
4611 /* Set SW Defineable Pin 0 to turn on the LED */ e1000_led_on()
4617 /* Set SW Defineable Pin 0 to turn on the LED */ e1000_led_on()
4621 /* Clear SW Defineable Pin 0 to turn on the LED */ e1000_led_on()
4628 /* Clear SW Defineable Pin 0 to turn on the LED */ e1000_led_on()
4655 /* Clear SW Defineable Pin 0 to turn off the LED */ e1000_led_off()
4661 /* Clear SW Defineable Pin 0 to turn off the LED */ e1000_led_off()
4665 /* Set SW Defineable Pin 0 to turn off the LED */ e1000_led_off()
4672 /* Set SW Defineable Pin 0 to turn off the LED */ e1000_led_off()
/linux-4.4.14/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h1096 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1097 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1098 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1099 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1110 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
1111 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
1112 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
1113 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
1297 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1298 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1299 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1300 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1312 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1313 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1314 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1315 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1327 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1328 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1329 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1330 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1342 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1343 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1344 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1345 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1670 /* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
2474 * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
2510 * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
/linux-4.4.14/drivers/staging/rtl8723au/hal/
H A Dhal_com.c29 /* sw_channel_plan: channel plan from SW (registry/module param) */
832 /* If it is in HW/SW Radio OFF or IPS state, we do rtl8723a_get_fwlps_rf_on()
/linux-4.4.14/drivers/media/platform/marvell-ccic/
H A Dcafe-driver.c111 #define GCSR_SRS 0x00000001 /* SW Reset set */
112 #define GCSR_SRC 0x00000002 /* SW Reset clear */
/linux-4.4.14/drivers/net/wireless/iwlwifi/
H A Diwl-nvm-parse.c78 /* NVM SW-Section offset (in words) definitions */
99 /* NVM SW-Section offset (in words) definitions */
/linux-4.4.14/drivers/net/wireless/iwlwifi/pcie/
H A Dinternal.h200 * SW entries: | 0 | ... | 31 |
201 * where N is a number between 0 and 7. This means that the SW
H A Drx.c978 IWL_DEBUG_RX(trans, "HW = SW = %d\n", r); iwl_pcie_rx_handle()
989 IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n", iwl_pcie_rx_handle()
1075 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
1341 IWL_ERR(trans, "Microcode SW error detected. " iwl_pcie_irq_handler()
/linux-4.4.14/drivers/net/fddi/skfp/h/
H A Dcmtdef.h407 u_long mac_nobuf_counter ; /* MAC SW counter: no buffer */
408 u_long mac_r_restart_counter ; /* MAC SW counter: rx restarted */
/linux-4.4.14/drivers/net/ethernet/broadcom/genet/
H A Dbcmgenet.h544 unsigned int write_ptr; /* Tx ring write pointer SW copy */
545 unsigned int prod_index; /* Tx ring producer index SW copy */
/linux-4.4.14/drivers/gpu/drm/bridge/
H A Dparade-ps8622.c112 /* SW setting: [1:0] SW output 1.2V voltage is lower to 96% */ ps8622_send_config()
/linux-4.4.14/arch/x86/include/asm/uv/
H A Duv_bau.h118 * SW Ack Timeout (destination) 1 0 0
119 * SW Ack INTD rejected (strong NACK) 1 0 1
/linux-4.4.14/arch/powerpc/kvm/
H A Dbook3s_hv_rm_xics.c586 * Note: If EOI is incorrectly used by SW to lower the CPPR kvmppc_rm_h_eoi()
588 * a pending interrupt, this is a SW error and PAPR sepcifies kvmppc_rm_h_eoi()
/linux-4.4.14/arch/s390/kernel/
H A Debcdic.c107 -SW */
256 -SW */
/linux-4.4.14/drivers/usb/serial/
H A Dssu100.c271 dev_dbg(&port->dev, "%s - set SW flow control failed\n", __func__); ssu100_set_termios()
/linux-4.4.14/drivers/video/fbdev/sis/
H A Dsis_accel.h278 bit 24 = 1: SW command queue empty
/linux-4.4.14/drivers/media/platform/coda/
H A Dcoda_regs.h39 /* Static SW registers */
/linux-4.4.14/drivers/input/keyboard/
H A Dnomadik-ske-keypad.c128 /* clear keypad interrupt for auto(and pending SW) scans */ ske_keypad_chip_init()
/linux-4.4.14/drivers/media/dvb-frontends/
H A Datbm8830.c252 /*SW version test*/ atbm8830_init()
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dsw.c406 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
H A Dsw.c382 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/
H A Dsw.c341 /*SW-WF02-AD15 -Abocom*/
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dsw.c379 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dsw.c430 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
/linux-4.4.14/drivers/net/ethernet/intel/ixgbevf/
H A Ddefines.h49 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */

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