1/* 2 * linux/arch/sh/boards/magicpanel/setup.c 3 * 4 * Copyright (C) 2007 Markus Brunner, Mark Jonas 5 * 6 * Magic Panel Release 2 board setup 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12#include <linux/init.h> 13#include <linux/irq.h> 14#include <linux/platform_device.h> 15#include <linux/delay.h> 16#include <linux/gpio.h> 17#include <linux/regulator/fixed.h> 18#include <linux/regulator/machine.h> 19#include <linux/smsc911x.h> 20#include <linux/mtd/mtd.h> 21#include <linux/mtd/partitions.h> 22#include <linux/mtd/physmap.h> 23#include <linux/mtd/map.h> 24#include <linux/sh_intc.h> 25#include <mach/magicpanelr2.h> 26#include <asm/heartbeat.h> 27#include <cpu/sh7720.h> 28 29/* Dummy supplies, where voltage doesn't matter */ 30static struct regulator_consumer_supply dummy_supplies[] = { 31 REGULATOR_SUPPLY("vddvario", "smsc911x"), 32 REGULATOR_SUPPLY("vdd33a", "smsc911x"), 33}; 34 35#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL) 36 37/* Wait until reset finished. Timeout is 100ms. */ 38static int __init ethernet_reset_finished(void) 39{ 40 int i; 41 42 if (LAN9115_READY) 43 return 1; 44 45 for (i = 0; i < 10; ++i) { 46 mdelay(10); 47 if (LAN9115_READY) 48 return 1; 49 } 50 51 return 0; 52} 53 54static void __init reset_ethernet(void) 55{ 56 /* PMDR: LAN_RESET=on */ 57 CLRBITS_OUTB(0x10, PORT_PMDR); 58 59 udelay(200); 60 61 /* PMDR: LAN_RESET=off */ 62 SETBITS_OUTB(0x10, PORT_PMDR); 63} 64 65static void __init setup_chip_select(void) 66{ 67 /* CS2: LAN (0x08000000 - 0x0bffffff) */ 68 /* no idle cycles, normal space, 8 bit data bus */ 69 __raw_writel(0x36db0400, CS2BCR); 70 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 71 __raw_writel(0x000003c0, CS2WCR); 72 73 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ 74 /* no idle cycles, normal space, 8 bit data bus */ 75 __raw_writel(0x00000200, CS4BCR); 76 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 77 __raw_writel(0x00100981, CS4WCR); 78 79 /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ 80 /* no idle cycles, normal space, 8 bit data bus */ 81 __raw_writel(0x00000200, CS5ABCR); 82 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 83 __raw_writel(0x00100981, CS5AWCR); 84 85 /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ 86 /* no idle cycles, normal space, 8 bit data bus */ 87 __raw_writel(0x00000200, CS5BBCR); 88 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 89 __raw_writel(0x00100981, CS5BWCR); 90 91 /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */ 92 /* no idle cycles, normal space, 8 bit data bus */ 93 __raw_writel(0x00000200, CS6ABCR); 94 /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ 95 __raw_writel(0x001009C1, CS6AWCR); 96} 97 98static void __init setup_port_multiplexing(void) 99{ 100 /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); 101 * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); 102 */ 103 __raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */ 104 105 /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); 106 * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); 107 */ 108 __raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */ 109 110 /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); 111 * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; 112 */ 113 __raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */ 114 115 /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); 116 * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); 117 */ 118 __raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */ 119 120 /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; 121 * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; 122 */ 123 __raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */ 124 125 /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; 126 * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); 127 */ 128 __raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */ 129 130 /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2); 131 * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); 132 */ 133 __raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */ 134 135 /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); 136 * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; 137 */ 138 __raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */ 139 140 /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; 141 * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; 142 */ 143 __raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */ 144 145 /* K7 (x); K6 (x); K5 (x); K4 (x); 146 * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY) 147 */ 148 __raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */ 149 150 /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; 151 * L3 TCK; L2 (x); L1 (x); L0 (x); 152 */ 153 __raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */ 154 155 /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); 156 * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL); 157 * M1 CS5B(CAN3_CS); M0 GPI+(nc); 158 */ 159 __raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */ 160 161 /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, 162 * LAN_RESET=off, BUZZER=off, LCD_BL=off 163 */ 164#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2 165 __raw_writeb(0x30, PORT_PMDR); 166#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3 167 __raw_writeb(0xF0, PORT_PMDR); 168#else 169#error Unknown revision of PLATFORM_MP_R2 170#endif 171 172 /* P7 (x); P6 (x); P5 (x); 173 * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ); 174 * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ) 175 */ 176 __raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */ 177 __raw_writeb(0x10, PORT_PPDR); 178 179 /* R7 A25; R6 A24; R5 A23; R4 A22; 180 * R3 A21; R2 A20; R1 A19; R0 A0; 181 */ 182 gpio_request(GPIO_FN_A25, NULL); 183 gpio_request(GPIO_FN_A24, NULL); 184 gpio_request(GPIO_FN_A23, NULL); 185 gpio_request(GPIO_FN_A22, NULL); 186 gpio_request(GPIO_FN_A21, NULL); 187 gpio_request(GPIO_FN_A20, NULL); 188 gpio_request(GPIO_FN_A19, NULL); 189 gpio_request(GPIO_FN_A0, NULL); 190 191 /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); 192 * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; 193 */ 194 __raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */ 195 196 /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; 197 * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG) 198 */ 199 __raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */ 200 201 /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); 202 * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; 203 */ 204 __raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */ 205 206 /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); 207 * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); 208 */ 209 __raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */ 210} 211 212static void __init mpr2_setup(char **cmdline_p) 213{ 214 /* set Pin Select Register A: 215 * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, 216 * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND 217 */ 218 __raw_writew(0xAABC, PORT_PSELA); 219 /* set Pin Select Register B: 220 * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, 221 * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved 222 */ 223 __raw_writew(0x3C00, PORT_PSELB); 224 /* set Pin Select Register C: 225 * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved 226 */ 227 __raw_writew(0x0000, PORT_PSELC); 228 /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, 229 * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved 230 */ 231 __raw_writew(0x0000, PORT_PSELD); 232 /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */ 233 __raw_writew(0x0101, PORT_UTRCTL); 234 /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */ 235 __raw_writew(0xA5C0, PORT_UCLKCR_W); 236 237 setup_chip_select(); 238 239 setup_port_multiplexing(); 240 241 reset_ethernet(); 242 243 printk(KERN_INFO "Magic Panel Release 2 A.%i\n", 244 CONFIG_SH_MAGIC_PANEL_R2_VERSION); 245 246 if (ethernet_reset_finished() == 0) 247 printk(KERN_WARNING "Ethernet not ready\n"); 248} 249 250static struct resource smsc911x_resources[] = { 251 [0] = { 252 .start = 0xa8000000, 253 .end = 0xabffffff, 254 .flags = IORESOURCE_MEM, 255 }, 256 [1] = { 257 .start = evt2irq(0x660), 258 .end = evt2irq(0x660), 259 .flags = IORESOURCE_IRQ, 260 }, 261}; 262 263static struct smsc911x_platform_config smsc911x_config = { 264 .phy_interface = PHY_INTERFACE_MODE_MII, 265 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 266 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, 267 .flags = SMSC911X_USE_32BIT, 268}; 269 270static struct platform_device smsc911x_device = { 271 .name = "smsc911x", 272 .id = -1, 273 .num_resources = ARRAY_SIZE(smsc911x_resources), 274 .resource = smsc911x_resources, 275 .dev = { 276 .platform_data = &smsc911x_config, 277 }, 278}; 279 280static struct resource heartbeat_resources[] = { 281 [0] = { 282 .start = PA_LED, 283 .end = PA_LED, 284 .flags = IORESOURCE_MEM, 285 }, 286}; 287 288static struct heartbeat_data heartbeat_data = { 289 .flags = HEARTBEAT_INVERTED, 290}; 291 292static struct platform_device heartbeat_device = { 293 .name = "heartbeat", 294 .id = -1, 295 .dev = { 296 .platform_data = &heartbeat_data, 297 }, 298 .num_resources = ARRAY_SIZE(heartbeat_resources), 299 .resource = heartbeat_resources, 300}; 301 302static struct mtd_partition mpr2_partitions[] = { 303 /* Reserved for bootloader, read-only */ 304 { 305 .name = "Bootloader", 306 .offset = 0x00000000UL, 307 .size = MPR2_MTD_BOOTLOADER_SIZE, 308 .mask_flags = MTD_WRITEABLE, 309 }, 310 /* Reserved for kernel image */ 311 { 312 .name = "Kernel", 313 .offset = MTDPART_OFS_NXTBLK, 314 .size = MPR2_MTD_KERNEL_SIZE, 315 }, 316 /* Rest is used for Flash FS */ 317 { 318 .name = "Flash_FS", 319 .offset = MTDPART_OFS_NXTBLK, 320 .size = MTDPART_SIZ_FULL, 321 } 322}; 323 324static struct physmap_flash_data flash_data = { 325 .parts = mpr2_partitions, 326 .nr_parts = ARRAY_SIZE(mpr2_partitions), 327 .width = 2, 328}; 329 330static struct resource flash_resource = { 331 .start = 0x00000000, 332 .end = 0x2000000UL, 333 .flags = IORESOURCE_MEM, 334}; 335 336static struct platform_device flash_device = { 337 .name = "physmap-flash", 338 .id = -1, 339 .resource = &flash_resource, 340 .num_resources = 1, 341 .dev = { 342 .platform_data = &flash_data, 343 }, 344}; 345 346/* 347 * Add all resources to the platform_device 348 */ 349 350static struct platform_device *mpr2_devices[] __initdata = { 351 &heartbeat_device, 352 &smsc911x_device, 353 &flash_device, 354}; 355 356 357static int __init mpr2_devices_setup(void) 358{ 359 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); 360 361 return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices)); 362} 363device_initcall(mpr2_devices_setup); 364 365/* 366 * Initialize IRQ setting 367 */ 368static void __init init_mpr2_IRQ(void) 369{ 370 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ 371 372 irq_set_irq_type(evt2irq(0x600), IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ 373 irq_set_irq_type(evt2irq(0x620), IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ 374 irq_set_irq_type(evt2irq(0x640), IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ 375 irq_set_irq_type(evt2irq(0x660), IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ 376 irq_set_irq_type(evt2irq(0x680), IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ 377 irq_set_irq_type(evt2irq(0x6a0), IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ 378 379 intc_set_priority(evt2irq(0x600), 13); /* IRQ0 CAN1 */ 380 intc_set_priority(evt2irq(0x620), 13); /* IRQ0 CAN2 */ 381 intc_set_priority(evt2irq(0x640), 13); /* IRQ0 CAN3 */ 382 intc_set_priority(evt2irq(0x660), 6); /* IRQ3 SMSC9115 */ 383} 384 385/* 386 * The Machine Vector 387 */ 388 389static struct sh_machine_vector mv_mpr2 __initmv = { 390 .mv_name = "mpr2", 391 .mv_setup = mpr2_setup, 392 .mv_init_irq = init_mpr2_IRQ, 393}; 394