1/* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _HTT_H_ 19#define _HTT_H_ 20 21#include <linux/bug.h> 22#include <linux/interrupt.h> 23#include <linux/dmapool.h> 24#include <linux/hashtable.h> 25#include <net/mac80211.h> 26 27#include "htc.h" 28#include "hw.h" 29#include "rx_desc.h" 30#include "hw.h" 31 32enum htt_dbg_stats_type { 33 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 34 HTT_DBG_STATS_RX_REORDER = 1 << 1, 35 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 36 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 37 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 38 /* bits 5-23 currently reserved */ 39 40 HTT_DBG_NUM_STATS /* keep this last */ 41}; 42 43enum htt_h2t_msg_type { /* host-to-target */ 44 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 45 HTT_H2T_MSG_TYPE_TX_FRM = 1, 46 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 47 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 48 HTT_H2T_MSG_TYPE_SYNC = 4, 49 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 50 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 51 52 /* This command is used for sending management frames in HTT < 3.0. 53 * HTT >= 3.0 uses TX_FRM for everything. */ 54 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 55 56 HTT_H2T_NUM_MSGS /* keep this last */ 57}; 58 59struct htt_cmd_hdr { 60 u8 msg_type; 61} __packed; 62 63struct htt_ver_req { 64 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 65} __packed; 66 67/* 68 * HTT tx MSDU descriptor 69 * 70 * The HTT tx MSDU descriptor is created by the host HTT SW for each 71 * tx MSDU. The HTT tx MSDU descriptor contains the information that 72 * the target firmware needs for the FW's tx processing, particularly 73 * for creating the HW msdu descriptor. 74 * The same HTT tx descriptor is used for HL and LL systems, though 75 * a few fields within the tx descriptor are used only by LL or 76 * only by HL. 77 * The HTT tx descriptor is defined in two manners: by a struct with 78 * bitfields, and by a series of [dword offset, bit mask, bit shift] 79 * definitions. 80 * The target should use the struct def, for simplicitly and clarity, 81 * but the host shall use the bit-mast + bit-shift defs, to be endian- 82 * neutral. Specifically, the host shall use the get/set macros built 83 * around the mask + shift defs. 84 */ 85struct htt_data_tx_desc_frag { 86 union { 87 struct double_word_addr { 88 __le32 paddr; 89 __le32 len; 90 } __packed dword_addr; 91 struct triple_word_addr { 92 __le32 paddr_lo; 93 __le16 paddr_hi; 94 __le16 len_16; 95 } __packed tword_addr; 96 } __packed; 97} __packed; 98 99struct htt_msdu_ext_desc { 100 __le32 tso_flag[3]; 101 __le16 ip_identification; 102 u8 flags; 103 u8 reserved; 104 struct htt_data_tx_desc_frag frags[6]; 105}; 106 107#define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0) 108#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1) 109#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2) 110#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3) 111#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4) 112 113#define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \ 114 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \ 115 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \ 116 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \ 117 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE) 118 119enum htt_data_tx_desc_flags0 { 120 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 121 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 122 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 123 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 124 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 125#define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 126#define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 127}; 128 129enum htt_data_tx_desc_flags1 { 130#define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 131#define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 132#define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 133#define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 134#define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 135#define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 136 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 137 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 138 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 139 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 140 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15 141}; 142 143enum htt_data_tx_ext_tid { 144 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 145 HTT_DATA_TX_EXT_TID_MGMT = 17, 146 HTT_DATA_TX_EXT_TID_INVALID = 31 147}; 148 149#define HTT_INVALID_PEERID 0xFFFF 150 151/* 152 * htt_data_tx_desc - used for data tx path 153 * 154 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 155 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 156 * for special kinds of tids 157 * postponed: only for HL hosts. indicates if this is a resend 158 * (HL hosts manage queues on the host ) 159 * more_in_batch: only for HL hosts. indicates if more packets are 160 * pending. this allows target to wait and aggregate 161 * freq: 0 means home channel of given vdev. intended for offchannel 162 */ 163struct htt_data_tx_desc { 164 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 165 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 166 __le16 len; 167 __le16 id; 168 __le32 frags_paddr; 169 __le16 peerid; 170 __le16 freq; 171 u8 prefetch[0]; /* start of frame, for FW classification engine */ 172} __packed; 173 174enum htt_rx_ring_flags { 175 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 176 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 177 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 178 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 179 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 180 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 181 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 182 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 183 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 184 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 185 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 186 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 187 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 188 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 189 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 190 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 191}; 192 193#define HTT_RX_RING_SIZE_MIN 128 194#define HTT_RX_RING_SIZE_MAX 2048 195 196struct htt_rx_ring_setup_ring { 197 __le32 fw_idx_shadow_reg_paddr; 198 __le32 rx_ring_base_paddr; 199 __le16 rx_ring_len; /* in 4-byte words */ 200 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 201 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 202 __le16 fw_idx_init_val; 203 204 /* the following offsets are in 4-byte units */ 205 __le16 mac80211_hdr_offset; 206 __le16 msdu_payload_offset; 207 __le16 ppdu_start_offset; 208 __le16 ppdu_end_offset; 209 __le16 mpdu_start_offset; 210 __le16 mpdu_end_offset; 211 __le16 msdu_start_offset; 212 __le16 msdu_end_offset; 213 __le16 rx_attention_offset; 214 __le16 frag_info_offset; 215} __packed; 216 217struct htt_rx_ring_setup_hdr { 218 u8 num_rings; /* supported values: 1, 2 */ 219 __le16 rsvd0; 220} __packed; 221 222struct htt_rx_ring_setup { 223 struct htt_rx_ring_setup_hdr hdr; 224 struct htt_rx_ring_setup_ring rings[0]; 225} __packed; 226 227/* 228 * htt_stats_req - request target to send specified statistics 229 * 230 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 231 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 232 * so make sure its little-endian. 233 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 234 * so make sure its little-endian. 235 * @cfg_val: stat_type specific configuration 236 * @stat_type: see %htt_dbg_stats_type 237 * @cookie_lsb: used for confirmation message from target->host 238 * @cookie_msb: ditto as %cookie 239 */ 240struct htt_stats_req { 241 u8 upload_types[3]; 242 u8 rsvd0; 243 u8 reset_types[3]; 244 struct { 245 u8 mpdu_bytes; 246 u8 mpdu_num_msdus; 247 u8 msdu_bytes; 248 } __packed; 249 u8 stat_type; 250 __le32 cookie_lsb; 251 __le32 cookie_msb; 252} __packed; 253 254#define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 255 256/* 257 * htt_oob_sync_req - request out-of-band sync 258 * 259 * The HTT SYNC tells the target to suspend processing of subsequent 260 * HTT host-to-target messages until some other target agent locally 261 * informs the target HTT FW that the current sync counter is equal to 262 * or greater than (in a modulo sense) the sync counter specified in 263 * the SYNC message. 264 * 265 * This allows other host-target components to synchronize their operation 266 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 267 * security key has been downloaded to and activated by the target. 268 * In the absence of any explicit synchronization counter value 269 * specification, the target HTT FW will use zero as the default current 270 * sync value. 271 * 272 * The HTT target FW will suspend its host->target message processing as long 273 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 274 */ 275struct htt_oob_sync_req { 276 u8 sync_count; 277 __le16 rsvd0; 278} __packed; 279 280struct htt_aggr_conf { 281 u8 max_num_ampdu_subframes; 282 /* amsdu_subframes is limited by 0x1F mask */ 283 u8 max_num_amsdu_subframes; 284} __packed; 285 286#define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 287struct htt_mgmt_tx_desc_qca99x0 { 288 __le32 rate; 289} __packed; 290 291struct htt_mgmt_tx_desc { 292 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 293 __le32 msdu_paddr; 294 __le32 desc_id; 295 __le32 len; 296 __le32 vdev_id; 297 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 298 union { 299 struct htt_mgmt_tx_desc_qca99x0 qca99x0; 300 } __packed; 301} __packed; 302 303enum htt_mgmt_tx_status { 304 HTT_MGMT_TX_STATUS_OK = 0, 305 HTT_MGMT_TX_STATUS_RETRY = 1, 306 HTT_MGMT_TX_STATUS_DROP = 2 307}; 308 309/*=== target -> host messages ===============================================*/ 310 311enum htt_main_t2h_msg_type { 312 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0, 313 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1, 314 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2, 315 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3, 316 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 317 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5, 318 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6, 319 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 320 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8, 321 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9, 322 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 323 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb, 324 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 325 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 326 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 327 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10, 328 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 329 HTT_MAIN_T2H_MSG_TYPE_TEST, 330 /* keep this last */ 331 HTT_MAIN_T2H_NUM_MSGS 332}; 333 334enum htt_10x_t2h_msg_type { 335 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0, 336 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1, 337 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2, 338 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3, 339 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 340 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5, 341 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6, 342 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 343 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8, 344 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9, 345 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 346 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb, 347 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 348 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 349 HTT_10X_T2H_MSG_TYPE_TEST = 0xe, 350 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 351 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11, 352 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12, 353 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13, 354 /* keep this last */ 355 HTT_10X_T2H_NUM_MSGS 356}; 357 358enum htt_tlv_t2h_msg_type { 359 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0, 360 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1, 361 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2, 362 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3, 363 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 364 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5, 365 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6, 366 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 367 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8, 368 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9, 369 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 370 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb, 371 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */ 372 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 373 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 374 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 375 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10, 376 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 377 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 378 /* 0x13 reservd */ 379 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 380 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 381 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 382 HTT_TLV_T2H_MSG_TYPE_TEST, 383 /* keep this last */ 384 HTT_TLV_T2H_NUM_MSGS 385}; 386 387enum htt_10_4_t2h_msg_type { 388 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0, 389 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1, 390 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2, 391 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3, 392 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 393 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5, 394 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6, 395 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 396 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8, 397 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9, 398 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 399 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb, 400 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 401 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 402 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 403 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 404 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10, 405 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11, 406 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12, 407 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13, 408 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14, 409 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15, 410 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16, 411 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONF = 0x17, 412 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18, 413 /* 0x19 to 0x2f are reserved */ 414 HTT_10_4_T2H_MSG_TYPE_TX_LOW_LATENCY_IND = 0x30, 415 /* keep this last */ 416 HTT_10_4_T2H_NUM_MSGS 417}; 418 419enum htt_t2h_msg_type { 420 HTT_T2H_MSG_TYPE_VERSION_CONF, 421 HTT_T2H_MSG_TYPE_RX_IND, 422 HTT_T2H_MSG_TYPE_RX_FLUSH, 423 HTT_T2H_MSG_TYPE_PEER_MAP, 424 HTT_T2H_MSG_TYPE_PEER_UNMAP, 425 HTT_T2H_MSG_TYPE_RX_ADDBA, 426 HTT_T2H_MSG_TYPE_RX_DELBA, 427 HTT_T2H_MSG_TYPE_TX_COMPL_IND, 428 HTT_T2H_MSG_TYPE_PKTLOG, 429 HTT_T2H_MSG_TYPE_STATS_CONF, 430 HTT_T2H_MSG_TYPE_RX_FRAG_IND, 431 HTT_T2H_MSG_TYPE_SEC_IND, 432 HTT_T2H_MSG_TYPE_RC_UPDATE_IND, 433 HTT_T2H_MSG_TYPE_TX_INSPECT_IND, 434 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION, 435 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND, 436 HTT_T2H_MSG_TYPE_RX_PN_IND, 437 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND, 438 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND, 439 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE, 440 HTT_T2H_MSG_TYPE_CHAN_CHANGE, 441 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR, 442 HTT_T2H_MSG_TYPE_AGGR_CONF, 443 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD, 444 HTT_T2H_MSG_TYPE_TEST, 445 HTT_T2H_MSG_TYPE_EN_STATS, 446 HTT_T2H_MSG_TYPE_TX_FETCH_IND, 447 HTT_T2H_MSG_TYPE_TX_FETCH_CONF, 448 HTT_T2H_MSG_TYPE_TX_LOW_LATENCY_IND, 449 /* keep this last */ 450 HTT_T2H_NUM_MSGS 451}; 452 453/* 454 * htt_resp_hdr - header for target-to-host messages 455 * 456 * msg_type: see htt_t2h_msg_type 457 */ 458struct htt_resp_hdr { 459 u8 msg_type; 460} __packed; 461 462#define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 463#define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 464#define HTT_RESP_HDR_MSG_TYPE_LSB 0 465 466/* htt_ver_resp - response sent for htt_ver_req */ 467struct htt_ver_resp { 468 u8 minor; 469 u8 major; 470 u8 rsvd0; 471} __packed; 472 473struct htt_mgmt_tx_completion { 474 u8 rsvd0; 475 u8 rsvd1; 476 u8 rsvd2; 477 __le32 desc_id; 478 __le32 status; 479} __packed; 480 481#define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x3F) 482#define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 483#define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 6) 484#define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 7) 485 486#define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 487#define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 488#define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 489#define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 490#define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 491#define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 492#define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 493#define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 494#define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 495#define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 496 497struct htt_rx_indication_hdr { 498 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 499 __le16 peer_id; 500 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 501} __packed; 502 503#define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 504#define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 505#define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 506#define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 507#define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 508#define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 509 510#define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 511#define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 512#define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 513#define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 514 515#define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 516#define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 517#define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 518#define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 519 520enum htt_rx_legacy_rate { 521 HTT_RX_OFDM_48 = 0, 522 HTT_RX_OFDM_24 = 1, 523 HTT_RX_OFDM_12, 524 HTT_RX_OFDM_6, 525 HTT_RX_OFDM_54, 526 HTT_RX_OFDM_36, 527 HTT_RX_OFDM_18, 528 HTT_RX_OFDM_9, 529 530 /* long preamble */ 531 HTT_RX_CCK_11_LP = 0, 532 HTT_RX_CCK_5_5_LP = 1, 533 HTT_RX_CCK_2_LP, 534 HTT_RX_CCK_1_LP, 535 /* short preamble */ 536 HTT_RX_CCK_11_SP, 537 HTT_RX_CCK_5_5_SP, 538 HTT_RX_CCK_2_SP 539}; 540 541enum htt_rx_legacy_rate_type { 542 HTT_RX_LEGACY_RATE_OFDM = 0, 543 HTT_RX_LEGACY_RATE_CCK 544}; 545 546enum htt_rx_preamble_type { 547 HTT_RX_LEGACY = 0x4, 548 HTT_RX_HT = 0x8, 549 HTT_RX_HT_WITH_TXBF = 0x9, 550 HTT_RX_VHT = 0xC, 551 HTT_RX_VHT_WITH_TXBF = 0xD, 552}; 553 554/* 555 * Fields: phy_err_valid, phy_err_code, tsf, 556 * usec_timestamp, sub_usec_timestamp 557 * ..are valid only if end_valid == 1. 558 * 559 * Fields: rssi_chains, legacy_rate_type, 560 * legacy_rate_cck, preamble_type, service, 561 * vht_sig_* 562 * ..are valid only if start_valid == 1; 563 */ 564struct htt_rx_indication_ppdu { 565 u8 combined_rssi; 566 u8 sub_usec_timestamp; 567 u8 phy_err_code; 568 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 569 struct { 570 u8 pri20_db; 571 u8 ext20_db; 572 u8 ext40_db; 573 u8 ext80_db; 574 } __packed rssi_chains[4]; 575 __le32 tsf; 576 __le32 usec_timestamp; 577 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 578 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 579} __packed; 580 581enum htt_rx_mpdu_status { 582 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 583 HTT_RX_IND_MPDU_STATUS_OK, 584 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 585 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 586 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 587 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 588 /* only accept EAPOL frames */ 589 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 590 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 591 /* Non-data in promiscous mode */ 592 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 593 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 594 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 595 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 596 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 597 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 598 599 /* 600 * MISC: discard for unspecified reasons. 601 * Leave this enum value last. 602 */ 603 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 604}; 605 606struct htt_rx_indication_mpdu_range { 607 u8 mpdu_count; 608 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 609 u8 pad0; 610 u8 pad1; 611} __packed; 612 613struct htt_rx_indication_prefix { 614 __le16 fw_rx_desc_bytes; 615 u8 pad0; 616 u8 pad1; 617}; 618 619struct htt_rx_indication { 620 struct htt_rx_indication_hdr hdr; 621 struct htt_rx_indication_ppdu ppdu; 622 struct htt_rx_indication_prefix prefix; 623 624 /* 625 * the following fields are both dynamically sized, so 626 * take care addressing them 627 */ 628 629 /* the size of this is %fw_rx_desc_bytes */ 630 struct fw_rx_desc_base fw_desc; 631 632 /* 633 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 634 * and has %num_mpdu_ranges elements. 635 */ 636 struct htt_rx_indication_mpdu_range mpdu_ranges[0]; 637} __packed; 638 639static inline struct htt_rx_indication_mpdu_range * 640 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 641{ 642 void *ptr = rx_ind; 643 644 ptr += sizeof(rx_ind->hdr) 645 + sizeof(rx_ind->ppdu) 646 + sizeof(rx_ind->prefix) 647 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 648 return ptr; 649} 650 651enum htt_rx_flush_mpdu_status { 652 HTT_RX_FLUSH_MPDU_DISCARD = 0, 653 HTT_RX_FLUSH_MPDU_REORDER = 1, 654}; 655 656/* 657 * htt_rx_flush - discard or reorder given range of mpdus 658 * 659 * Note: host must check if all sequence numbers between 660 * [seq_num_start, seq_num_end-1] are valid. 661 */ 662struct htt_rx_flush { 663 __le16 peer_id; 664 u8 tid; 665 u8 rsvd0; 666 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 667 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 668 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 669}; 670 671struct htt_rx_peer_map { 672 u8 vdev_id; 673 __le16 peer_id; 674 u8 addr[6]; 675 u8 rsvd0; 676 u8 rsvd1; 677} __packed; 678 679struct htt_rx_peer_unmap { 680 u8 rsvd0; 681 __le16 peer_id; 682} __packed; 683 684enum htt_security_types { 685 HTT_SECURITY_NONE, 686 HTT_SECURITY_WEP128, 687 HTT_SECURITY_WEP104, 688 HTT_SECURITY_WEP40, 689 HTT_SECURITY_TKIP, 690 HTT_SECURITY_TKIP_NOMIC, 691 HTT_SECURITY_AES_CCMP, 692 HTT_SECURITY_WAPI, 693 694 HTT_NUM_SECURITY_TYPES /* keep this last! */ 695}; 696 697enum htt_security_flags { 698#define HTT_SECURITY_TYPE_MASK 0x7F 699#define HTT_SECURITY_TYPE_LSB 0 700 HTT_SECURITY_IS_UNICAST = 1 << 7 701}; 702 703struct htt_security_indication { 704 union { 705 /* dont use bitfields; undefined behaviour */ 706 u8 flags; /* %htt_security_flags */ 707 struct { 708 u8 security_type:7, /* %htt_security_types */ 709 is_unicast:1; 710 } __packed; 711 } __packed; 712 __le16 peer_id; 713 u8 michael_key[8]; 714 u8 wapi_rsc[16]; 715} __packed; 716 717#define HTT_RX_BA_INFO0_TID_MASK 0x000F 718#define HTT_RX_BA_INFO0_TID_LSB 0 719#define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 720#define HTT_RX_BA_INFO0_PEER_ID_LSB 4 721 722struct htt_rx_addba { 723 u8 window_size; 724 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 725} __packed; 726 727struct htt_rx_delba { 728 u8 rsvd0; 729 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 730} __packed; 731 732enum htt_data_tx_status { 733 HTT_DATA_TX_STATUS_OK = 0, 734 HTT_DATA_TX_STATUS_DISCARD = 1, 735 HTT_DATA_TX_STATUS_NO_ACK = 2, 736 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */ 737 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128 738}; 739 740enum htt_data_tx_flags { 741#define HTT_DATA_TX_STATUS_MASK 0x07 742#define HTT_DATA_TX_STATUS_LSB 0 743#define HTT_DATA_TX_TID_MASK 0x78 744#define HTT_DATA_TX_TID_LSB 3 745 HTT_DATA_TX_TID_INVALID = 1 << 7 746}; 747 748#define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 749 750struct htt_data_tx_completion { 751 union { 752 u8 flags; 753 struct { 754 u8 status:3, 755 tid:4, 756 tid_invalid:1; 757 } __packed; 758 } __packed; 759 u8 num_msdus; 760 u8 rsvd0; 761 __le16 msdus[0]; /* variable length based on %num_msdus */ 762} __packed; 763 764struct htt_tx_compl_ind_base { 765 u32 hdr; 766 u16 payload[1/*or more*/]; 767} __packed; 768 769struct htt_rc_tx_done_params { 770 u32 rate_code; 771 u32 rate_code_flags; 772 u32 flags; 773 u32 num_enqued; /* 1 for non-AMPDU */ 774 u32 num_retries; 775 u32 num_failed; /* for AMPDU */ 776 u32 ack_rssi; 777 u32 time_stamp; 778 u32 is_probe; 779}; 780 781struct htt_rc_update { 782 u8 vdev_id; 783 __le16 peer_id; 784 u8 addr[6]; 785 u8 num_elems; 786 u8 rsvd0; 787 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */ 788} __packed; 789 790/* see htt_rx_indication for similar fields and descriptions */ 791struct htt_rx_fragment_indication { 792 union { 793 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 794 struct { 795 u8 ext_tid:5, 796 flush_valid:1; 797 } __packed; 798 } __packed; 799 __le16 peer_id; 800 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 801 __le16 fw_rx_desc_bytes; 802 __le16 rsvd0; 803 804 u8 fw_msdu_rx_desc[0]; 805} __packed; 806 807#define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 808#define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 809#define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 810#define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 811 812#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 813#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 814#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 815#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 816 817struct htt_rx_pn_ind { 818 __le16 peer_id; 819 u8 tid; 820 u8 seqno_start; 821 u8 seqno_end; 822 u8 pn_ie_count; 823 u8 reserved; 824 u8 pn_ies[0]; 825} __packed; 826 827struct htt_rx_offload_msdu { 828 __le16 msdu_len; 829 __le16 peer_id; 830 u8 vdev_id; 831 u8 tid; 832 u8 fw_desc; 833 u8 payload[0]; 834} __packed; 835 836struct htt_rx_offload_ind { 837 u8 reserved; 838 __le16 msdu_count; 839} __packed; 840 841struct htt_rx_in_ord_msdu_desc { 842 __le32 msdu_paddr; 843 __le16 msdu_len; 844 u8 fw_desc; 845 u8 reserved; 846} __packed; 847 848struct htt_rx_in_ord_ind { 849 u8 info; 850 __le16 peer_id; 851 u8 vdev_id; 852 u8 reserved; 853 __le16 msdu_count; 854 struct htt_rx_in_ord_msdu_desc msdu_descs[0]; 855} __packed; 856 857#define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f 858#define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0 859#define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020 860#define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5 861#define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040 862#define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6 863 864/* 865 * target -> host test message definition 866 * 867 * The following field definitions describe the format of the test 868 * message sent from the target to the host. 869 * The message consists of a 4-octet header, followed by a variable 870 * number of 32-bit integer values, followed by a variable number 871 * of 8-bit character values. 872 * 873 * |31 16|15 8|7 0| 874 * |-----------------------------------------------------------| 875 * | num chars | num ints | msg type | 876 * |-----------------------------------------------------------| 877 * | int 0 | 878 * |-----------------------------------------------------------| 879 * | int 1 | 880 * |-----------------------------------------------------------| 881 * | ... | 882 * |-----------------------------------------------------------| 883 * | char 3 | char 2 | char 1 | char 0 | 884 * |-----------------------------------------------------------| 885 * | | | ... | char 4 | 886 * |-----------------------------------------------------------| 887 * - MSG_TYPE 888 * Bits 7:0 889 * Purpose: identifies this as a test message 890 * Value: HTT_MSG_TYPE_TEST 891 * - NUM_INTS 892 * Bits 15:8 893 * Purpose: indicate how many 32-bit integers follow the message header 894 * - NUM_CHARS 895 * Bits 31:16 896 * Purpose: indicate how many 8-bit charaters follow the series of integers 897 */ 898struct htt_rx_test { 899 u8 num_ints; 900 __le16 num_chars; 901 902 /* payload consists of 2 lists: 903 * a) num_ints * sizeof(__le32) 904 * b) num_chars * sizeof(u8) aligned to 4bytes */ 905 u8 payload[0]; 906} __packed; 907 908static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 909{ 910 return (__le32 *)rx_test->payload; 911} 912 913static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 914{ 915 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 916} 917 918/* 919 * target -> host packet log message 920 * 921 * The following field definitions describe the format of the packet log 922 * message sent from the target to the host. 923 * The message consists of a 4-octet header,followed by a variable number 924 * of 32-bit character values. 925 * 926 * |31 24|23 16|15 8|7 0| 927 * |-----------------------------------------------------------| 928 * | | | | msg type | 929 * |-----------------------------------------------------------| 930 * | payload | 931 * |-----------------------------------------------------------| 932 * - MSG_TYPE 933 * Bits 7:0 934 * Purpose: identifies this as a test message 935 * Value: HTT_MSG_TYPE_PACKETLOG 936 */ 937struct htt_pktlog_msg { 938 u8 pad[3]; 939 u8 payload[0]; 940} __packed; 941 942struct htt_dbg_stats_rx_reorder_stats { 943 /* Non QoS MPDUs received */ 944 __le32 deliver_non_qos; 945 946 /* MPDUs received in-order */ 947 __le32 deliver_in_order; 948 949 /* Flush due to reorder timer expired */ 950 __le32 deliver_flush_timeout; 951 952 /* Flush due to move out of window */ 953 __le32 deliver_flush_oow; 954 955 /* Flush due to DELBA */ 956 __le32 deliver_flush_delba; 957 958 /* MPDUs dropped due to FCS error */ 959 __le32 fcs_error; 960 961 /* MPDUs dropped due to monitor mode non-data packet */ 962 __le32 mgmt_ctrl; 963 964 /* MPDUs dropped due to invalid peer */ 965 __le32 invalid_peer; 966 967 /* MPDUs dropped due to duplication (non aggregation) */ 968 __le32 dup_non_aggr; 969 970 /* MPDUs dropped due to processed before */ 971 __le32 dup_past; 972 973 /* MPDUs dropped due to duplicate in reorder queue */ 974 __le32 dup_in_reorder; 975 976 /* Reorder timeout happened */ 977 __le32 reorder_timeout; 978 979 /* invalid bar ssn */ 980 __le32 invalid_bar_ssn; 981 982 /* reorder reset due to bar ssn */ 983 __le32 ssn_reset; 984}; 985 986struct htt_dbg_stats_wal_tx_stats { 987 /* Num HTT cookies queued to dispatch list */ 988 __le32 comp_queued; 989 990 /* Num HTT cookies dispatched */ 991 __le32 comp_delivered; 992 993 /* Num MSDU queued to WAL */ 994 __le32 msdu_enqued; 995 996 /* Num MPDU queue to WAL */ 997 __le32 mpdu_enqued; 998 999 /* Num MSDUs dropped by WMM limit */ 1000 __le32 wmm_drop; 1001 1002 /* Num Local frames queued */ 1003 __le32 local_enqued; 1004 1005 /* Num Local frames done */ 1006 __le32 local_freed; 1007 1008 /* Num queued to HW */ 1009 __le32 hw_queued; 1010 1011 /* Num PPDU reaped from HW */ 1012 __le32 hw_reaped; 1013 1014 /* Num underruns */ 1015 __le32 underrun; 1016 1017 /* Num PPDUs cleaned up in TX abort */ 1018 __le32 tx_abort; 1019 1020 /* Num MPDUs requed by SW */ 1021 __le32 mpdus_requed; 1022 1023 /* excessive retries */ 1024 __le32 tx_ko; 1025 1026 /* data hw rate code */ 1027 __le32 data_rc; 1028 1029 /* Scheduler self triggers */ 1030 __le32 self_triggers; 1031 1032 /* frames dropped due to excessive sw retries */ 1033 __le32 sw_retry_failure; 1034 1035 /* illegal rate phy errors */ 1036 __le32 illgl_rate_phy_err; 1037 1038 /* wal pdev continous xretry */ 1039 __le32 pdev_cont_xretry; 1040 1041 /* wal pdev continous xretry */ 1042 __le32 pdev_tx_timeout; 1043 1044 /* wal pdev resets */ 1045 __le32 pdev_resets; 1046 1047 __le32 phy_underrun; 1048 1049 /* MPDU is more than txop limit */ 1050 __le32 txop_ovf; 1051} __packed; 1052 1053struct htt_dbg_stats_wal_rx_stats { 1054 /* Cnts any change in ring routing mid-ppdu */ 1055 __le32 mid_ppdu_route_change; 1056 1057 /* Total number of statuses processed */ 1058 __le32 status_rcvd; 1059 1060 /* Extra frags on rings 0-3 */ 1061 __le32 r0_frags; 1062 __le32 r1_frags; 1063 __le32 r2_frags; 1064 __le32 r3_frags; 1065 1066 /* MSDUs / MPDUs delivered to HTT */ 1067 __le32 htt_msdus; 1068 __le32 htt_mpdus; 1069 1070 /* MSDUs / MPDUs delivered to local stack */ 1071 __le32 loc_msdus; 1072 __le32 loc_mpdus; 1073 1074 /* AMSDUs that have more MSDUs than the status ring size */ 1075 __le32 oversize_amsdu; 1076 1077 /* Number of PHY errors */ 1078 __le32 phy_errs; 1079 1080 /* Number of PHY errors drops */ 1081 __le32 phy_err_drop; 1082 1083 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 1084 __le32 mpdu_errs; 1085} __packed; 1086 1087struct htt_dbg_stats_wal_peer_stats { 1088 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 1089} __packed; 1090 1091struct htt_dbg_stats_wal_pdev_txrx { 1092 struct htt_dbg_stats_wal_tx_stats tx_stats; 1093 struct htt_dbg_stats_wal_rx_stats rx_stats; 1094 struct htt_dbg_stats_wal_peer_stats peer_stats; 1095} __packed; 1096 1097struct htt_dbg_stats_rx_rate_info { 1098 __le32 mcs[10]; 1099 __le32 sgi[10]; 1100 __le32 nss[4]; 1101 __le32 stbc[10]; 1102 __le32 bw[3]; 1103 __le32 pream[6]; 1104 __le32 ldpc; 1105 __le32 txbf; 1106}; 1107 1108/* 1109 * htt_dbg_stats_status - 1110 * present - The requested stats have been delivered in full. 1111 * This indicates that either the stats information was contained 1112 * in its entirety within this message, or else this message 1113 * completes the delivery of the requested stats info that was 1114 * partially delivered through earlier STATS_CONF messages. 1115 * partial - The requested stats have been delivered in part. 1116 * One or more subsequent STATS_CONF messages with the same 1117 * cookie value will be sent to deliver the remainder of the 1118 * information. 1119 * error - The requested stats could not be delivered, for example due 1120 * to a shortage of memory to construct a message holding the 1121 * requested stats. 1122 * invalid - The requested stat type is either not recognized, or the 1123 * target is configured to not gather the stats type in question. 1124 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1125 * series_done - This special value indicates that no further stats info 1126 * elements are present within a series of stats info elems 1127 * (within a stats upload confirmation message). 1128 */ 1129enum htt_dbg_stats_status { 1130 HTT_DBG_STATS_STATUS_PRESENT = 0, 1131 HTT_DBG_STATS_STATUS_PARTIAL = 1, 1132 HTT_DBG_STATS_STATUS_ERROR = 2, 1133 HTT_DBG_STATS_STATUS_INVALID = 3, 1134 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 1135}; 1136 1137/* 1138 * target -> host statistics upload 1139 * 1140 * The following field definitions describe the format of the HTT target 1141 * to host stats upload confirmation message. 1142 * The message contains a cookie echoed from the HTT host->target stats 1143 * upload request, which identifies which request the confirmation is 1144 * for, and a series of tag-length-value stats information elements. 1145 * The tag-length header for each stats info element also includes a 1146 * status field, to indicate whether the request for the stat type in 1147 * question was fully met, partially met, unable to be met, or invalid 1148 * (if the stat type in question is disabled in the target). 1149 * A special value of all 1's in this status field is used to indicate 1150 * the end of the series of stats info elements. 1151 * 1152 * 1153 * |31 16|15 8|7 5|4 0| 1154 * |------------------------------------------------------------| 1155 * | reserved | msg type | 1156 * |------------------------------------------------------------| 1157 * | cookie LSBs | 1158 * |------------------------------------------------------------| 1159 * | cookie MSBs | 1160 * |------------------------------------------------------------| 1161 * | stats entry length | reserved | S |stat type| 1162 * |------------------------------------------------------------| 1163 * | | 1164 * | type-specific stats info | 1165 * | | 1166 * |------------------------------------------------------------| 1167 * | stats entry length | reserved | S |stat type| 1168 * |------------------------------------------------------------| 1169 * | | 1170 * | type-specific stats info | 1171 * | | 1172 * |------------------------------------------------------------| 1173 * | n/a | reserved | 111 | n/a | 1174 * |------------------------------------------------------------| 1175 * Header fields: 1176 * - MSG_TYPE 1177 * Bits 7:0 1178 * Purpose: identifies this is a statistics upload confirmation message 1179 * Value: 0x9 1180 * - COOKIE_LSBS 1181 * Bits 31:0 1182 * Purpose: Provide a mechanism to match a target->host stats confirmation 1183 * message with its preceding host->target stats request message. 1184 * Value: LSBs of the opaque cookie specified by the host-side requestor 1185 * - COOKIE_MSBS 1186 * Bits 31:0 1187 * Purpose: Provide a mechanism to match a target->host stats confirmation 1188 * message with its preceding host->target stats request message. 1189 * Value: MSBs of the opaque cookie specified by the host-side requestor 1190 * 1191 * Stats Information Element tag-length header fields: 1192 * - STAT_TYPE 1193 * Bits 4:0 1194 * Purpose: identifies the type of statistics info held in the 1195 * following information element 1196 * Value: htt_dbg_stats_type 1197 * - STATUS 1198 * Bits 7:5 1199 * Purpose: indicate whether the requested stats are present 1200 * Value: htt_dbg_stats_status, including a special value (0x7) to mark 1201 * the completion of the stats entry series 1202 * - LENGTH 1203 * Bits 31:16 1204 * Purpose: indicate the stats information size 1205 * Value: This field specifies the number of bytes of stats information 1206 * that follows the element tag-length header. 1207 * It is expected but not required that this length is a multiple of 1208 * 4 bytes. Even if the length is not an integer multiple of 4, the 1209 * subsequent stats entry header will begin on a 4-byte aligned 1210 * boundary. 1211 */ 1212 1213#define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F 1214#define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0 1215#define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0 1216#define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5 1217 1218struct htt_stats_conf_item { 1219 union { 1220 u8 info; 1221 struct { 1222 u8 stat_type:5; /* %HTT_DBG_STATS_ */ 1223 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */ 1224 } __packed; 1225 } __packed; 1226 u8 pad; 1227 __le16 length; 1228 u8 payload[0]; /* roundup(length, 4) long */ 1229} __packed; 1230 1231struct htt_stats_conf { 1232 u8 pad[3]; 1233 __le32 cookie_lsb; 1234 __le32 cookie_msb; 1235 1236 /* each item has variable length! */ 1237 struct htt_stats_conf_item items[0]; 1238} __packed; 1239 1240static inline struct htt_stats_conf_item *htt_stats_conf_next_item( 1241 const struct htt_stats_conf_item *item) 1242{ 1243 return (void *)item + sizeof(*item) + roundup(item->length, 4); 1244} 1245 1246/* 1247 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1248 * 1249 * The following field definitions describe the format of the HTT host 1250 * to target frag_desc/msdu_ext bank configuration message. 1251 * The message contains the based address and the min and max id of the 1252 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1253 * MSDU_EXT/FRAG_DESC. 1254 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1255 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1256 * the hardware does the mapping/translation. 1257 * 1258 * Total banks that can be configured is configured to 16. 1259 * 1260 * This should be called before any TX has be initiated by the HTT 1261 * 1262 * |31 16|15 8|7 5|4 0| 1263 * |------------------------------------------------------------| 1264 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1265 * |------------------------------------------------------------| 1266 * | BANK0_BASE_ADDRESS | 1267 * |------------------------------------------------------------| 1268 * | ... | 1269 * |------------------------------------------------------------| 1270 * | BANK15_BASE_ADDRESS | 1271 * |------------------------------------------------------------| 1272 * | BANK0_MAX_ID | BANK0_MIN_ID | 1273 * |------------------------------------------------------------| 1274 * | ... | 1275 * |------------------------------------------------------------| 1276 * | BANK15_MAX_ID | BANK15_MIN_ID | 1277 * |------------------------------------------------------------| 1278 * Header fields: 1279 * - MSG_TYPE 1280 * Bits 7:0 1281 * Value: 0x6 1282 * - BANKx_BASE_ADDRESS 1283 * Bits 31:0 1284 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1285 * bank physical/bus address. 1286 * - BANKx_MIN_ID 1287 * Bits 15:0 1288 * Purpose: Provide a mechanism to specify the min index that needs to 1289 * mapped. 1290 * - BANKx_MAX_ID 1291 * Bits 31:16 1292 * Purpose: Provide a mechanism to specify the max index that needs to 1293 * 1294 */ 1295struct htt_frag_desc_bank_id { 1296 __le16 bank_min_id; 1297 __le16 bank_max_id; 1298} __packed; 1299 1300/* real is 16 but it wouldn't fit in the max htt message size 1301 * so we use a conservatively safe value for now */ 1302#define HTT_FRAG_DESC_BANK_MAX 4 1303 1304#define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1305#define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1306#define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP (1 << 2) 1307 1308struct htt_frag_desc_bank_cfg { 1309 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1310 u8 num_banks; 1311 u8 desc_size; 1312 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1313 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1314} __packed; 1315 1316union htt_rx_pn_t { 1317 /* WEP: 24-bit PN */ 1318 u32 pn24; 1319 1320 /* TKIP or CCMP: 48-bit PN */ 1321 u_int64_t pn48; 1322 1323 /* WAPI: 128-bit PN */ 1324 u_int64_t pn128[2]; 1325}; 1326 1327struct htt_cmd { 1328 struct htt_cmd_hdr hdr; 1329 union { 1330 struct htt_ver_req ver_req; 1331 struct htt_mgmt_tx_desc mgmt_tx; 1332 struct htt_data_tx_desc data_tx; 1333 struct htt_rx_ring_setup rx_setup; 1334 struct htt_stats_req stats_req; 1335 struct htt_oob_sync_req oob_sync_req; 1336 struct htt_aggr_conf aggr_conf; 1337 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg; 1338 }; 1339} __packed; 1340 1341struct htt_resp { 1342 struct htt_resp_hdr hdr; 1343 union { 1344 struct htt_ver_resp ver_resp; 1345 struct htt_mgmt_tx_completion mgmt_tx_completion; 1346 struct htt_data_tx_completion data_tx_completion; 1347 struct htt_rx_indication rx_ind; 1348 struct htt_rx_fragment_indication rx_frag_ind; 1349 struct htt_rx_peer_map peer_map; 1350 struct htt_rx_peer_unmap peer_unmap; 1351 struct htt_rx_flush rx_flush; 1352 struct htt_rx_addba rx_addba; 1353 struct htt_rx_delba rx_delba; 1354 struct htt_security_indication security_indication; 1355 struct htt_rc_update rc_update; 1356 struct htt_rx_test rx_test; 1357 struct htt_pktlog_msg pktlog_msg; 1358 struct htt_stats_conf stats_conf; 1359 struct htt_rx_pn_ind rx_pn_ind; 1360 struct htt_rx_offload_ind rx_offload_ind; 1361 struct htt_rx_in_ord_ind rx_in_ord_ind; 1362 }; 1363} __packed; 1364 1365/*** host side structures follow ***/ 1366 1367struct htt_tx_done { 1368 u32 msdu_id; 1369 bool discard; 1370 bool no_ack; 1371 bool success; 1372}; 1373 1374struct htt_peer_map_event { 1375 u8 vdev_id; 1376 u16 peer_id; 1377 u8 addr[ETH_ALEN]; 1378}; 1379 1380struct htt_peer_unmap_event { 1381 u16 peer_id; 1382}; 1383 1384struct ath10k_htt_txbuf { 1385 struct htt_data_tx_desc_frag frags[2]; 1386 struct ath10k_htc_hdr htc_hdr; 1387 struct htt_cmd_hdr cmd_hdr; 1388 struct htt_data_tx_desc cmd_tx; 1389} __packed; 1390 1391struct ath10k_htt { 1392 struct ath10k *ar; 1393 enum ath10k_htc_ep_id eid; 1394 1395 u8 target_version_major; 1396 u8 target_version_minor; 1397 struct completion target_version_received; 1398 enum ath10k_fw_htt_op_version op_version; 1399 u8 max_num_amsdu; 1400 u8 max_num_ampdu; 1401 1402 const enum htt_t2h_msg_type *t2h_msg_types; 1403 u32 t2h_msg_types_max; 1404 1405 struct { 1406 /* 1407 * Ring of network buffer objects - This ring is 1408 * used exclusively by the host SW. This ring 1409 * mirrors the dev_addrs_ring that is shared 1410 * between the host SW and the MAC HW. The host SW 1411 * uses this netbufs ring to locate the network 1412 * buffer objects whose data buffers the HW has 1413 * filled. 1414 */ 1415 struct sk_buff **netbufs_ring; 1416 1417 /* This is used only with firmware supporting IN_ORD_IND. 1418 * 1419 * With Full Rx Reorder the HTT Rx Ring is more of a temporary 1420 * buffer ring from which buffer addresses are copied by the 1421 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND 1422 * pointing to specific (re-ordered) buffers. 1423 * 1424 * FIXME: With kernel generic hashing functions there's a lot 1425 * of hash collisions for sk_buffs. 1426 */ 1427 bool in_ord_rx; 1428 DECLARE_HASHTABLE(skb_table, 4); 1429 1430 /* 1431 * Ring of buffer addresses - 1432 * This ring holds the "physical" device address of the 1433 * rx buffers the host SW provides for the MAC HW to 1434 * fill. 1435 */ 1436 __le32 *paddrs_ring; 1437 1438 /* 1439 * Base address of ring, as a "physical" device address 1440 * rather than a CPU address. 1441 */ 1442 dma_addr_t base_paddr; 1443 1444 /* how many elems in the ring (power of 2) */ 1445 int size; 1446 1447 /* size - 1 */ 1448 unsigned size_mask; 1449 1450 /* how many rx buffers to keep in the ring */ 1451 int fill_level; 1452 1453 /* how many rx buffers (full+empty) are in the ring */ 1454 int fill_cnt; 1455 1456 /* 1457 * alloc_idx - where HTT SW has deposited empty buffers 1458 * This is allocated in consistent mem, so that the FW can 1459 * read this variable, and program the HW's FW_IDX reg with 1460 * the value of this shadow register. 1461 */ 1462 struct { 1463 __le32 *vaddr; 1464 dma_addr_t paddr; 1465 } alloc_idx; 1466 1467 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1468 struct { 1469 unsigned msdu_payld; 1470 } sw_rd_idx; 1471 1472 /* 1473 * refill_retry_timer - timer triggered when the ring is 1474 * not refilled to the level expected 1475 */ 1476 struct timer_list refill_retry_timer; 1477 1478 /* Protects access to all rx ring buffer state variables */ 1479 spinlock_t lock; 1480 } rx_ring; 1481 1482 unsigned int prefetch_len; 1483 1484 /* Protects access to pending_tx, num_pending_tx */ 1485 spinlock_t tx_lock; 1486 int max_num_pending_tx; 1487 int num_pending_tx; 1488 int num_pending_mgmt_tx; 1489 struct idr pending_tx; 1490 wait_queue_head_t empty_tx_wq; 1491 1492 /* set if host-fw communication goes haywire 1493 * used to avoid further failures */ 1494 bool rx_confused; 1495 struct tasklet_struct rx_replenish_task; 1496 1497 /* This is used to group tx/rx completions separately and process them 1498 * in batches to reduce cache stalls */ 1499 struct tasklet_struct txrx_compl_task; 1500 struct sk_buff_head tx_compl_q; 1501 struct sk_buff_head rx_compl_q; 1502 struct sk_buff_head rx_in_ord_compl_q; 1503 1504 /* rx_status template */ 1505 struct ieee80211_rx_status rx_status; 1506 1507 struct { 1508 dma_addr_t paddr; 1509 struct htt_msdu_ext_desc *vaddr; 1510 } frag_desc; 1511 1512 struct { 1513 dma_addr_t paddr; 1514 struct ath10k_htt_txbuf *vaddr; 1515 } txbuf; 1516}; 1517 1518#define RX_HTT_HDR_STATUS_LEN 64 1519 1520/* This structure layout is programmed via rx ring setup 1521 * so that FW knows how to transfer the rx descriptor to the host. 1522 * Buffers like this are placed on the rx ring. */ 1523struct htt_rx_desc { 1524 union { 1525 /* This field is filled on the host using the msdu buffer 1526 * from htt_rx_indication */ 1527 struct fw_rx_desc_base fw_desc; 1528 u32 pad; 1529 } __packed; 1530 struct { 1531 struct rx_attention attention; 1532 struct rx_frag_info frag_info; 1533 struct rx_mpdu_start mpdu_start; 1534 struct rx_msdu_start msdu_start; 1535 struct rx_msdu_end msdu_end; 1536 struct rx_mpdu_end mpdu_end; 1537 struct rx_ppdu_start ppdu_start; 1538 struct rx_ppdu_end ppdu_end; 1539 } __packed; 1540 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 1541 u8 msdu_payload[0]; 1542}; 1543 1544#define HTT_RX_DESC_ALIGN 8 1545 1546#define HTT_MAC_ADDR_LEN 6 1547 1548/* 1549 * FIX THIS 1550 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 1551 * rounded up to a cache line size. 1552 */ 1553#define HTT_RX_BUF_SIZE 1920 1554#define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) 1555 1556/* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 1557 * aggregated traffic more nicely. */ 1558#define ATH10K_HTT_MAX_NUM_REFILL 16 1559 1560/* 1561 * DMA_MAP expects the buffer to be an integral number of cache lines. 1562 * Rather than checking the actual cache line size, this code makes a 1563 * conservative estimate of what the cache line size could be. 1564 */ 1565#define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 1566#define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 1567 1568/* These values are default in most firmware revisions and apparently are a 1569 * sweet spot performance wise. 1570 */ 1571#define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3 1572#define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64 1573 1574int ath10k_htt_connect(struct ath10k_htt *htt); 1575int ath10k_htt_init(struct ath10k *ar); 1576int ath10k_htt_setup(struct ath10k_htt *htt); 1577 1578int ath10k_htt_tx_alloc(struct ath10k_htt *htt); 1579void ath10k_htt_tx_free(struct ath10k_htt *htt); 1580 1581int ath10k_htt_rx_alloc(struct ath10k_htt *htt); 1582int ath10k_htt_rx_ring_refill(struct ath10k *ar); 1583void ath10k_htt_rx_free(struct ath10k_htt *htt); 1584 1585void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1586void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 1587int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 1588int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); 1589int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt); 1590int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt); 1591int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 1592 u8 max_subfrms_ampdu, 1593 u8 max_subfrms_amsdu); 1594void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb); 1595 1596void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt, bool limit_mgmt_desc); 1597int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb); 1598void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 1599int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *); 1600int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *); 1601 1602#endif 1603