1/* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#ifndef __CXGB4_H__ 36#define __CXGB4_H__ 37 38#include "t4_hw.h" 39 40#include <linux/bitops.h> 41#include <linux/cache.h> 42#include <linux/interrupt.h> 43#include <linux/list.h> 44#include <linux/netdevice.h> 45#include <linux/pci.h> 46#include <linux/spinlock.h> 47#include <linux/timer.h> 48#include <linux/vmalloc.h> 49#include <linux/etherdevice.h> 50#include <linux/net_tstamp.h> 51#include <asm/io.h> 52#include "t4_chip_type.h" 53#include "cxgb4_uld.h" 54 55#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 56 57enum { 58 MAX_NPORTS = 4, /* max # of ports */ 59 SERNUM_LEN = 24, /* Serial # length */ 60 EC_LEN = 16, /* E/C length */ 61 ID_LEN = 16, /* ID length */ 62 PN_LEN = 16, /* Part Number length */ 63 MACADDR_LEN = 12, /* MAC Address length */ 64}; 65 66enum { 67 T4_REGMAP_SIZE = (160 * 1024), 68 T5_REGMAP_SIZE = (332 * 1024), 69}; 70 71enum { 72 MEM_EDC0, 73 MEM_EDC1, 74 MEM_MC, 75 MEM_MC0 = MEM_MC, 76 MEM_MC1 77}; 78 79enum { 80 MEMWIN0_APERTURE = 2048, 81 MEMWIN0_BASE = 0x1b800, 82 MEMWIN1_APERTURE = 32768, 83 MEMWIN1_BASE = 0x28000, 84 MEMWIN1_BASE_T5 = 0x52000, 85 MEMWIN2_APERTURE = 65536, 86 MEMWIN2_BASE = 0x30000, 87 MEMWIN2_APERTURE_T5 = 131072, 88 MEMWIN2_BASE_T5 = 0x60000, 89}; 90 91enum dev_master { 92 MASTER_CANT, 93 MASTER_MAY, 94 MASTER_MUST 95}; 96 97enum dev_state { 98 DEV_STATE_UNINIT, 99 DEV_STATE_INIT, 100 DEV_STATE_ERR 101}; 102 103enum { 104 PAUSE_RX = 1 << 0, 105 PAUSE_TX = 1 << 1, 106 PAUSE_AUTONEG = 1 << 2 107}; 108 109struct port_stats { 110 u64 tx_octets; /* total # of octets in good frames */ 111 u64 tx_frames; /* all good frames */ 112 u64 tx_bcast_frames; /* all broadcast frames */ 113 u64 tx_mcast_frames; /* all multicast frames */ 114 u64 tx_ucast_frames; /* all unicast frames */ 115 u64 tx_error_frames; /* all error frames */ 116 117 u64 tx_frames_64; /* # of Tx frames in a particular range */ 118 u64 tx_frames_65_127; 119 u64 tx_frames_128_255; 120 u64 tx_frames_256_511; 121 u64 tx_frames_512_1023; 122 u64 tx_frames_1024_1518; 123 u64 tx_frames_1519_max; 124 125 u64 tx_drop; /* # of dropped Tx frames */ 126 u64 tx_pause; /* # of transmitted pause frames */ 127 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 128 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 129 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 130 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 131 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 132 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 133 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 134 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 135 136 u64 rx_octets; /* total # of octets in good frames */ 137 u64 rx_frames; /* all good frames */ 138 u64 rx_bcast_frames; /* all broadcast frames */ 139 u64 rx_mcast_frames; /* all multicast frames */ 140 u64 rx_ucast_frames; /* all unicast frames */ 141 u64 rx_too_long; /* # of frames exceeding MTU */ 142 u64 rx_jabber; /* # of jabber frames */ 143 u64 rx_fcs_err; /* # of received frames with bad FCS */ 144 u64 rx_len_err; /* # of received frames with length error */ 145 u64 rx_symbol_err; /* symbol errors */ 146 u64 rx_runt; /* # of short frames */ 147 148 u64 rx_frames_64; /* # of Rx frames in a particular range */ 149 u64 rx_frames_65_127; 150 u64 rx_frames_128_255; 151 u64 rx_frames_256_511; 152 u64 rx_frames_512_1023; 153 u64 rx_frames_1024_1518; 154 u64 rx_frames_1519_max; 155 156 u64 rx_pause; /* # of received pause frames */ 157 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 158 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 159 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 160 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 161 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 162 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 163 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 164 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 165 166 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 167 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 168 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 169 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 170 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 171 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 172 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 173 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 174}; 175 176struct lb_port_stats { 177 u64 octets; 178 u64 frames; 179 u64 bcast_frames; 180 u64 mcast_frames; 181 u64 ucast_frames; 182 u64 error_frames; 183 184 u64 frames_64; 185 u64 frames_65_127; 186 u64 frames_128_255; 187 u64 frames_256_511; 188 u64 frames_512_1023; 189 u64 frames_1024_1518; 190 u64 frames_1519_max; 191 192 u64 drop; 193 194 u64 ovflow0; 195 u64 ovflow1; 196 u64 ovflow2; 197 u64 ovflow3; 198 u64 trunc0; 199 u64 trunc1; 200 u64 trunc2; 201 u64 trunc3; 202}; 203 204struct tp_tcp_stats { 205 u32 tcp_out_rsts; 206 u64 tcp_in_segs; 207 u64 tcp_out_segs; 208 u64 tcp_retrans_segs; 209}; 210 211struct tp_usm_stats { 212 u32 frames; 213 u32 drops; 214 u64 octets; 215}; 216 217struct tp_fcoe_stats { 218 u32 frames_ddp; 219 u32 frames_drop; 220 u64 octets_ddp; 221}; 222 223struct tp_err_stats { 224 u32 mac_in_errs[4]; 225 u32 hdr_in_errs[4]; 226 u32 tcp_in_errs[4]; 227 u32 tnl_cong_drops[4]; 228 u32 ofld_chan_drops[4]; 229 u32 tnl_tx_drops[4]; 230 u32 ofld_vlan_drops[4]; 231 u32 tcp6_in_errs[4]; 232 u32 ofld_no_neigh; 233 u32 ofld_cong_defer; 234}; 235 236struct tp_cpl_stats { 237 u32 req[4]; 238 u32 rsp[4]; 239}; 240 241struct tp_rdma_stats { 242 u32 rqe_dfr_pkt; 243 u32 rqe_dfr_mod; 244}; 245 246struct sge_params { 247 u32 hps; /* host page size for our PF/VF */ 248 u32 eq_qpp; /* egress queues/page for our PF/VF */ 249 u32 iq_qpp; /* egress queues/page for our PF/VF */ 250}; 251 252struct tp_params { 253 unsigned int tre; /* log2 of core clocks per TP tick */ 254 unsigned int la_mask; /* what events are recorded by TP LA */ 255 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 256 /* channel map */ 257 258 uint32_t dack_re; /* DACK timer resolution */ 259 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 260 261 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 262 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 263 264 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 265 * subset of the set of fields which may be present in the Compressed 266 * Filter Tuple portion of filters and TCP TCB connections. The 267 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 268 * Since a variable number of fields may or may not be present, their 269 * shifted field positions within the Compressed Filter Tuple may 270 * vary, or not even be present if the field isn't selected in 271 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 272 * places we store their offsets here, or a -1 if the field isn't 273 * present. 274 */ 275 int vlan_shift; 276 int vnic_shift; 277 int port_shift; 278 int protocol_shift; 279}; 280 281struct vpd_params { 282 unsigned int cclk; 283 u8 ec[EC_LEN + 1]; 284 u8 sn[SERNUM_LEN + 1]; 285 u8 id[ID_LEN + 1]; 286 u8 pn[PN_LEN + 1]; 287 u8 na[MACADDR_LEN + 1]; 288}; 289 290struct pci_params { 291 unsigned char speed; 292 unsigned char width; 293}; 294 295struct devlog_params { 296 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 297 u32 start; /* start of log in firmware memory */ 298 u32 size; /* size of log */ 299}; 300 301/* Stores chip specific parameters */ 302struct arch_specific_params { 303 u8 nchan; 304 u16 mps_rplc_size; 305 u16 vfcount; 306 u32 sge_fl_db; 307 u16 mps_tcam_size; 308}; 309 310struct adapter_params { 311 struct sge_params sge; 312 struct tp_params tp; 313 struct vpd_params vpd; 314 struct pci_params pci; 315 struct devlog_params devlog; 316 enum pcie_memwin drv_memwin; 317 318 unsigned int cim_la_size; 319 320 unsigned int sf_size; /* serial flash size in bytes */ 321 unsigned int sf_nsec; /* # of flash sectors */ 322 unsigned int sf_fw_start; /* start of FW image in flash */ 323 324 unsigned int fw_vers; 325 unsigned int tp_vers; 326 u8 api_vers[7]; 327 328 unsigned short mtus[NMTUS]; 329 unsigned short a_wnd[NCCTRL_WIN]; 330 unsigned short b_wnd[NCCTRL_WIN]; 331 332 unsigned char nports; /* # of ethernet ports */ 333 unsigned char portvec; 334 enum chip_type chip; /* chip code */ 335 struct arch_specific_params arch; /* chip specific params */ 336 unsigned char offload; 337 338 unsigned char bypass; 339 340 unsigned int ofldq_wr_cred; 341 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 342 343 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 344 unsigned int max_ird_adapter; /* Max read depth per adapter */ 345}; 346 347/* State needed to monitor the forward progress of SGE Ingress DMA activities 348 * and possible hangs. 349 */ 350struct sge_idma_monitor_state { 351 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 352 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 353 unsigned int idma_state[2]; /* IDMA Hang detect state */ 354 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 355 unsigned int idma_warn[2]; /* time to warning in HZ */ 356}; 357 358#include "t4fw_api.h" 359 360#define FW_VERSION(chip) ( \ 361 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 362 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 363 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 364 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 365#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 366 367struct fw_info { 368 u8 chip; 369 char *fs_name; 370 char *fw_mod_name; 371 struct fw_hdr fw_hdr; 372}; 373 374 375struct trace_params { 376 u32 data[TRACE_LEN / 4]; 377 u32 mask[TRACE_LEN / 4]; 378 unsigned short snap_len; 379 unsigned short min_len; 380 unsigned char skip_ofst; 381 unsigned char skip_len; 382 unsigned char invert; 383 unsigned char port; 384}; 385 386struct link_config { 387 unsigned short supported; /* link capabilities */ 388 unsigned short advertising; /* advertised capabilities */ 389 unsigned short requested_speed; /* speed user has requested */ 390 unsigned short speed; /* actual link speed */ 391 unsigned char requested_fc; /* flow control user has requested */ 392 unsigned char fc; /* actual link flow control */ 393 unsigned char autoneg; /* autonegotiating? */ 394 unsigned char link_ok; /* link up? */ 395}; 396 397#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 398 399enum { 400 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 401 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */ 402 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 403 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 404 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */ 405 MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */ 406}; 407 408enum { 409 MAX_TXQ_ENTRIES = 16384, 410 MAX_CTRL_TXQ_ENTRIES = 1024, 411 MAX_RSPQ_ENTRIES = 16384, 412 MAX_RX_BUFFERS = 16384, 413 MIN_TXQ_ENTRIES = 32, 414 MIN_CTRL_TXQ_ENTRIES = 32, 415 MIN_RSPQ_ENTRIES = 128, 416 MIN_FL_ENTRIES = 16 417}; 418 419enum { 420 INGQ_EXTRAS = 2, /* firmware event queue and */ 421 /* forwarded interrupts */ 422 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES 423 + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS, 424}; 425 426struct adapter; 427struct sge_rspq; 428 429#include "cxgb4_dcb.h" 430 431#ifdef CONFIG_CHELSIO_T4_FCOE 432#include "cxgb4_fcoe.h" 433#endif /* CONFIG_CHELSIO_T4_FCOE */ 434 435struct port_info { 436 struct adapter *adapter; 437 u16 viid; 438 s16 xact_addr_filt; /* index of exact MAC address filter */ 439 u16 rss_size; /* size of VI's RSS table slice */ 440 s8 mdio_addr; 441 enum fw_port_type port_type; 442 u8 mod_type; 443 u8 port_id; 444 u8 tx_chan; 445 u8 lport; /* associated offload logical port */ 446 u8 nqsets; /* # of qsets */ 447 u8 first_qset; /* index of first qset */ 448 u8 rss_mode; 449 struct link_config link_cfg; 450 u16 *rss; 451 struct port_stats stats_base; 452#ifdef CONFIG_CHELSIO_T4_DCB 453 struct port_dcb_info dcb; /* Data Center Bridging support */ 454#endif 455#ifdef CONFIG_CHELSIO_T4_FCOE 456 struct cxgb_fcoe fcoe; 457#endif /* CONFIG_CHELSIO_T4_FCOE */ 458 bool rxtstamp; /* Enable TS */ 459 struct hwtstamp_config tstamp_config; 460}; 461 462struct dentry; 463struct work_struct; 464 465enum { /* adapter flags */ 466 FULL_INIT_DONE = (1 << 0), 467 DEV_ENABLED = (1 << 1), 468 USING_MSI = (1 << 2), 469 USING_MSIX = (1 << 3), 470 FW_OK = (1 << 4), 471 RSS_TNLALLLOOKUP = (1 << 5), 472 USING_SOFT_PARAMS = (1 << 6), 473 MASTER_PF = (1 << 7), 474 FW_OFLD_CONN = (1 << 9), 475}; 476 477struct rx_sw_desc; 478 479struct sge_fl { /* SGE free-buffer queue state */ 480 unsigned int avail; /* # of available Rx buffers */ 481 unsigned int pend_cred; /* new buffers since last FL DB ring */ 482 unsigned int cidx; /* consumer index */ 483 unsigned int pidx; /* producer index */ 484 unsigned long alloc_failed; /* # of times buffer allocation failed */ 485 unsigned long large_alloc_failed; 486 unsigned long starving; 487 /* RO fields */ 488 unsigned int cntxt_id; /* SGE context id for the free list */ 489 unsigned int size; /* capacity of free list */ 490 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 491 __be64 *desc; /* address of HW Rx descriptor ring */ 492 dma_addr_t addr; /* bus address of HW ring start */ 493 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 494 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 495}; 496 497/* A packet gather list */ 498struct pkt_gl { 499 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 500 struct page_frag frags[MAX_SKB_FRAGS]; 501 void *va; /* virtual address of first byte */ 502 unsigned int nfrags; /* # of fragments */ 503 unsigned int tot_len; /* total length of fragments */ 504}; 505 506typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 507 const struct pkt_gl *gl); 508 509struct sge_rspq { /* state for an SGE response queue */ 510 struct napi_struct napi; 511 const __be64 *cur_desc; /* current descriptor in queue */ 512 unsigned int cidx; /* consumer index */ 513 u8 gen; /* current generation bit */ 514 u8 intr_params; /* interrupt holdoff parameters */ 515 u8 next_intr_params; /* holdoff params for next interrupt */ 516 u8 adaptive_rx; 517 u8 pktcnt_idx; /* interrupt packet threshold */ 518 u8 uld; /* ULD handling this queue */ 519 u8 idx; /* queue index within its group */ 520 int offset; /* offset into current Rx buffer */ 521 u16 cntxt_id; /* SGE context id for the response q */ 522 u16 abs_id; /* absolute SGE id for the response q */ 523 __be64 *desc; /* address of HW response ring */ 524 dma_addr_t phys_addr; /* physical address of the ring */ 525 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 526 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 527 unsigned int iqe_len; /* entry size */ 528 unsigned int size; /* capacity of response queue */ 529 struct adapter *adap; 530 struct net_device *netdev; /* associated net device */ 531 rspq_handler_t handler; 532#ifdef CONFIG_NET_RX_BUSY_POLL 533#define CXGB_POLL_STATE_IDLE 0 534#define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */ 535#define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */ 536#define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */ 537#define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */ 538#define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \ 539 CXGB_POLL_STATE_POLL_YIELD) 540#define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \ 541 CXGB_POLL_STATE_POLL) 542#define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \ 543 CXGB_POLL_STATE_POLL_YIELD) 544 unsigned int bpoll_state; 545 spinlock_t bpoll_lock; /* lock for busy poll */ 546#endif /* CONFIG_NET_RX_BUSY_POLL */ 547 548}; 549 550struct sge_eth_stats { /* Ethernet queue statistics */ 551 unsigned long pkts; /* # of ethernet packets */ 552 unsigned long lro_pkts; /* # of LRO super packets */ 553 unsigned long lro_merged; /* # of wire packets merged by LRO */ 554 unsigned long rx_cso; /* # of Rx checksum offloads */ 555 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 556 unsigned long rx_drops; /* # of packets dropped due to no mem */ 557}; 558 559struct sge_eth_rxq { /* SW Ethernet Rx queue */ 560 struct sge_rspq rspq; 561 struct sge_fl fl; 562 struct sge_eth_stats stats; 563} ____cacheline_aligned_in_smp; 564 565struct sge_ofld_stats { /* offload queue statistics */ 566 unsigned long pkts; /* # of packets */ 567 unsigned long imm; /* # of immediate-data packets */ 568 unsigned long an; /* # of asynchronous notifications */ 569 unsigned long nomem; /* # of responses deferred due to no mem */ 570}; 571 572struct sge_ofld_rxq { /* SW offload Rx queue */ 573 struct sge_rspq rspq; 574 struct sge_fl fl; 575 struct sge_ofld_stats stats; 576} ____cacheline_aligned_in_smp; 577 578struct tx_desc { 579 __be64 flit[8]; 580}; 581 582struct tx_sw_desc; 583 584struct sge_txq { 585 unsigned int in_use; /* # of in-use Tx descriptors */ 586 unsigned int size; /* # of descriptors */ 587 unsigned int cidx; /* SW consumer index */ 588 unsigned int pidx; /* producer index */ 589 unsigned long stops; /* # of times q has been stopped */ 590 unsigned long restarts; /* # of queue restarts */ 591 unsigned int cntxt_id; /* SGE context id for the Tx q */ 592 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 593 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 594 struct sge_qstat *stat; /* queue status entry */ 595 dma_addr_t phys_addr; /* physical address of the ring */ 596 spinlock_t db_lock; 597 int db_disabled; 598 unsigned short db_pidx; 599 unsigned short db_pidx_inc; 600 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 601 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 602}; 603 604struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 605 struct sge_txq q; 606 struct netdev_queue *txq; /* associated netdev TX queue */ 607#ifdef CONFIG_CHELSIO_T4_DCB 608 u8 dcb_prio; /* DCB Priority bound to queue */ 609#endif 610 unsigned long tso; /* # of TSO requests */ 611 unsigned long tx_cso; /* # of Tx checksum offloads */ 612 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 613 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 614} ____cacheline_aligned_in_smp; 615 616struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 617 struct sge_txq q; 618 struct adapter *adap; 619 struct sk_buff_head sendq; /* list of backpressured packets */ 620 struct tasklet_struct qresume_tsk; /* restarts the queue */ 621 u8 full; /* the Tx ring is full */ 622 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 623} ____cacheline_aligned_in_smp; 624 625struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 626 struct sge_txq q; 627 struct adapter *adap; 628 struct sk_buff_head sendq; /* list of backpressured packets */ 629 struct tasklet_struct qresume_tsk; /* restarts the queue */ 630 u8 full; /* the Tx ring is full */ 631} ____cacheline_aligned_in_smp; 632 633struct sge { 634 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 635 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 636 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 637 638 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 639 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS]; 640 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 641 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; 642 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 643 644 struct sge_rspq intrq ____cacheline_aligned_in_smp; 645 spinlock_t intrq_lock; 646 647 u16 max_ethqsets; /* # of available Ethernet queue sets */ 648 u16 ethqsets; /* # of active Ethernet queue sets */ 649 u16 ethtxq_rover; /* Tx queue to clean up next */ 650 u16 ofldqsets; /* # of active offload queue sets */ 651 u16 rdmaqs; /* # of available RDMA Rx queues */ 652 u16 rdmaciqs; /* # of available RDMA concentrator IQs */ 653 u16 ofld_rxq[MAX_OFLD_QSETS]; 654 u16 rdma_rxq[MAX_RDMA_QUEUES]; 655 u16 rdma_ciq[MAX_RDMA_CIQS]; 656 u16 timer_val[SGE_NTIMERS]; 657 u8 counter_val[SGE_NCOUNTERS]; 658 u32 fl_pg_order; /* large page allocation size */ 659 u32 stat_len; /* length of status page at ring end */ 660 u32 pktshift; /* padding between CPL & packet data */ 661 u32 fl_align; /* response queue message alignment */ 662 u32 fl_starve_thres; /* Free List starvation threshold */ 663 664 struct sge_idma_monitor_state idma_monitor; 665 unsigned int egr_start; 666 unsigned int egr_sz; 667 unsigned int ingr_start; 668 unsigned int ingr_sz; 669 void **egr_map; /* qid->queue egress queue map */ 670 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 671 unsigned long *starving_fl; 672 unsigned long *txq_maperr; 673 unsigned long *blocked_fl; 674 struct timer_list rx_timer; /* refills starving FLs */ 675 struct timer_list tx_timer; /* checks Tx queues */ 676}; 677 678#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 679#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 680#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 681#define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) 682 683struct l2t_data; 684 685#ifdef CONFIG_PCI_IOV 686 687/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 688 * Configuration initialization for T5 only has SR-IOV functionality enabled 689 * on PF0-3 in order to simplify everything. 690 */ 691#define NUM_OF_PF_WITH_SRIOV 4 692 693#endif 694 695struct doorbell_stats { 696 u32 db_drop; 697 u32 db_empty; 698 u32 db_full; 699}; 700 701struct adapter { 702 void __iomem *regs; 703 void __iomem *bar2; 704 u32 t4_bar0; 705 struct pci_dev *pdev; 706 struct device *pdev_dev; 707 unsigned int mbox; 708 unsigned int pf; 709 unsigned int flags; 710 enum chip_type chip; 711 712 int msg_enable; 713 714 struct adapter_params params; 715 struct cxgb4_virt_res vres; 716 unsigned int swintr; 717 718 struct { 719 unsigned short vec; 720 char desc[IFNAMSIZ + 10]; 721 } msix_info[MAX_INGQ + 1]; 722 723 struct doorbell_stats db_stats; 724 struct sge sge; 725 726 struct net_device *port[MAX_NPORTS]; 727 u8 chan_map[NCHAN]; /* channel -> port map */ 728 729 u32 filter_mode; 730 unsigned int l2t_start; 731 unsigned int l2t_end; 732 struct l2t_data *l2t; 733 unsigned int clipt_start; 734 unsigned int clipt_end; 735 struct clip_tbl *clipt; 736 void *uld_handle[CXGB4_ULD_MAX]; 737 struct list_head list_node; 738 struct list_head rcu_node; 739 740 struct tid_info tids; 741 void **tid_release_head; 742 spinlock_t tid_release_lock; 743 struct workqueue_struct *workq; 744 struct work_struct tid_release_task; 745 struct work_struct db_full_task; 746 struct work_struct db_drop_task; 747 bool tid_release_task_busy; 748 749 struct dentry *debugfs_root; 750 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 751 bool trace_rss; /* 1 implies that different RSS flit per filter is 752 * used per filter else if 0 default RSS flit is 753 * used for all 4 filters. 754 */ 755 756 spinlock_t stats_lock; 757 spinlock_t win0_lock ____cacheline_aligned_in_smp; 758}; 759 760/* Defined bit width of user definable filter tuples 761 */ 762#define ETHTYPE_BITWIDTH 16 763#define FRAG_BITWIDTH 1 764#define MACIDX_BITWIDTH 9 765#define FCOE_BITWIDTH 1 766#define IPORT_BITWIDTH 3 767#define MATCHTYPE_BITWIDTH 3 768#define PROTO_BITWIDTH 8 769#define TOS_BITWIDTH 8 770#define PF_BITWIDTH 8 771#define VF_BITWIDTH 8 772#define IVLAN_BITWIDTH 16 773#define OVLAN_BITWIDTH 16 774 775/* Filter matching rules. These consist of a set of ingress packet field 776 * (value, mask) tuples. The associated ingress packet field matches the 777 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 778 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 779 * matches an ingress packet when all of the individual individual field 780 * matching rules are true. 781 * 782 * Partial field masks are always valid, however, while it may be easy to 783 * understand their meanings for some fields (e.g. IP address to match a 784 * subnet), for others making sensible partial masks is less intuitive (e.g. 785 * MPS match type) ... 786 * 787 * Most of the following data structures are modeled on T4 capabilities. 788 * Drivers for earlier chips use the subsets which make sense for those chips. 789 * We really need to come up with a hardware-independent mechanism to 790 * represent hardware filter capabilities ... 791 */ 792struct ch_filter_tuple { 793 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 794 * register selects which of these fields will participate in the 795 * filter match rules -- up to a maximum of 36 bits. Because 796 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 797 * set of fields. 798 */ 799 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 800 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 801 uint32_t ivlan_vld:1; /* inner VLAN valid */ 802 uint32_t ovlan_vld:1; /* outer VLAN valid */ 803 uint32_t pfvf_vld:1; /* PF/VF valid */ 804 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 805 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 806 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 807 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 808 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 809 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 810 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 811 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 812 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 813 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 814 815 /* Uncompressed header matching field rules. These are always 816 * available for field rules. 817 */ 818 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 819 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 820 uint16_t lport; /* local port */ 821 uint16_t fport; /* foreign port */ 822}; 823 824/* A filter ioctl command. 825 */ 826struct ch_filter_specification { 827 /* Administrative fields for filter. 828 */ 829 uint32_t hitcnts:1; /* count filter hits in TCB */ 830 uint32_t prio:1; /* filter has priority over active/server */ 831 832 /* Fundamental filter typing. This is the one element of filter 833 * matching that doesn't exist as a (value, mask) tuple. 834 */ 835 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 836 837 /* Packet dispatch information. Ingress packets which match the 838 * filter rules will be dropped, passed to the host or switched back 839 * out as egress packets. 840 */ 841 uint32_t action:2; /* drop, pass, switch */ 842 843 uint32_t rpttid:1; /* report TID in RSS hash field */ 844 845 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 846 uint32_t iq:10; /* ingress queue */ 847 848 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 849 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 850 /* 1 => TCB contains IQ ID */ 851 852 /* Switch proxy/rewrite fields. An ingress packet which matches a 853 * filter with "switch" set will be looped back out as an egress 854 * packet -- potentially with some Ethernet header rewriting. 855 */ 856 uint32_t eport:2; /* egress port to switch packet out */ 857 uint32_t newdmac:1; /* rewrite destination MAC address */ 858 uint32_t newsmac:1; /* rewrite source MAC address */ 859 uint32_t newvlan:2; /* rewrite VLAN Tag */ 860 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 861 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 862 uint16_t vlan; /* VLAN Tag to insert */ 863 864 /* Filter rule value/mask pairs. 865 */ 866 struct ch_filter_tuple val; 867 struct ch_filter_tuple mask; 868}; 869 870enum { 871 FILTER_PASS = 0, /* default */ 872 FILTER_DROP, 873 FILTER_SWITCH 874}; 875 876enum { 877 VLAN_NOCHANGE = 0, /* default */ 878 VLAN_REMOVE, 879 VLAN_INSERT, 880 VLAN_REWRITE 881}; 882 883static inline int is_offload(const struct adapter *adap) 884{ 885 return adap->params.offload; 886} 887 888static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 889{ 890 return readl(adap->regs + reg_addr); 891} 892 893static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 894{ 895 writel(val, adap->regs + reg_addr); 896} 897 898#ifndef readq 899static inline u64 readq(const volatile void __iomem *addr) 900{ 901 return readl(addr) + ((u64)readl(addr + 4) << 32); 902} 903 904static inline void writeq(u64 val, volatile void __iomem *addr) 905{ 906 writel(val, addr); 907 writel(val >> 32, addr + 4); 908} 909#endif 910 911static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 912{ 913 return readq(adap->regs + reg_addr); 914} 915 916static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 917{ 918 writeq(val, adap->regs + reg_addr); 919} 920 921/** 922 * t4_set_hw_addr - store a port's MAC address in SW 923 * @adapter: the adapter 924 * @port_idx: the port index 925 * @hw_addr: the Ethernet address 926 * 927 * Store the Ethernet address of the given port in SW. Called by the common 928 * code when it retrieves a port's Ethernet address from EEPROM. 929 */ 930static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 931 u8 hw_addr[]) 932{ 933 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 934 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 935} 936 937/** 938 * netdev2pinfo - return the port_info structure associated with a net_device 939 * @dev: the netdev 940 * 941 * Return the struct port_info associated with a net_device 942 */ 943static inline struct port_info *netdev2pinfo(const struct net_device *dev) 944{ 945 return netdev_priv(dev); 946} 947 948/** 949 * adap2pinfo - return the port_info of a port 950 * @adap: the adapter 951 * @idx: the port index 952 * 953 * Return the port_info structure for the port of the given index. 954 */ 955static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 956{ 957 return netdev_priv(adap->port[idx]); 958} 959 960/** 961 * netdev2adap - return the adapter structure associated with a net_device 962 * @dev: the netdev 963 * 964 * Return the struct adapter associated with a net_device 965 */ 966static inline struct adapter *netdev2adap(const struct net_device *dev) 967{ 968 return netdev2pinfo(dev)->adapter; 969} 970 971#ifdef CONFIG_NET_RX_BUSY_POLL 972static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 973{ 974 spin_lock_init(&q->bpoll_lock); 975 q->bpoll_state = CXGB_POLL_STATE_IDLE; 976} 977 978static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 979{ 980 bool rc = true; 981 982 spin_lock(&q->bpoll_lock); 983 if (q->bpoll_state & CXGB_POLL_LOCKED) { 984 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD; 985 rc = false; 986 } else { 987 q->bpoll_state = CXGB_POLL_STATE_NAPI; 988 } 989 spin_unlock(&q->bpoll_lock); 990 return rc; 991} 992 993static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 994{ 995 bool rc = false; 996 997 spin_lock(&q->bpoll_lock); 998 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 999 rc = true; 1000 q->bpoll_state = CXGB_POLL_STATE_IDLE; 1001 spin_unlock(&q->bpoll_lock); 1002 return rc; 1003} 1004 1005static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 1006{ 1007 bool rc = true; 1008 1009 spin_lock_bh(&q->bpoll_lock); 1010 if (q->bpoll_state & CXGB_POLL_LOCKED) { 1011 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD; 1012 rc = false; 1013 } else { 1014 q->bpoll_state |= CXGB_POLL_STATE_POLL; 1015 } 1016 spin_unlock_bh(&q->bpoll_lock); 1017 return rc; 1018} 1019 1020static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 1021{ 1022 bool rc = false; 1023 1024 spin_lock_bh(&q->bpoll_lock); 1025 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 1026 rc = true; 1027 q->bpoll_state = CXGB_POLL_STATE_IDLE; 1028 spin_unlock_bh(&q->bpoll_lock); 1029 return rc; 1030} 1031 1032static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 1033{ 1034 return q->bpoll_state & CXGB_POLL_USER_PEND; 1035} 1036#else 1037static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 1038{ 1039} 1040 1041static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 1042{ 1043 return true; 1044} 1045 1046static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 1047{ 1048 return false; 1049} 1050 1051static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 1052{ 1053 return false; 1054} 1055 1056static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 1057{ 1058 return false; 1059} 1060 1061static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 1062{ 1063 return false; 1064} 1065#endif /* CONFIG_NET_RX_BUSY_POLL */ 1066 1067/* Return a version number to identify the type of adapter. The scheme is: 1068 * - bits 0..9: chip version 1069 * - bits 10..15: chip revision 1070 * - bits 16..23: register dump version 1071 */ 1072static inline unsigned int mk_adap_vers(struct adapter *ap) 1073{ 1074 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1075 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1076} 1077 1078/* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1079static inline unsigned int qtimer_val(const struct adapter *adap, 1080 const struct sge_rspq *q) 1081{ 1082 unsigned int idx = q->intr_params >> 1; 1083 1084 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1085} 1086 1087/* driver version & name used for ethtool_drvinfo */ 1088extern char cxgb4_driver_name[]; 1089extern const char cxgb4_driver_version[]; 1090 1091void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1092void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1093 1094void *t4_alloc_mem(size_t size); 1095 1096void t4_free_sge_resources(struct adapter *adap); 1097void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1098irq_handler_t t4_intr_handler(struct adapter *adap); 1099netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1100int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1101 const struct pkt_gl *gl); 1102int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1103int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1104int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1105 struct net_device *dev, int intr_idx, 1106 struct sge_fl *fl, rspq_handler_t hnd, int cong); 1107int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1108 struct net_device *dev, struct netdev_queue *netdevq, 1109 unsigned int iqid); 1110int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1111 struct net_device *dev, unsigned int iqid, 1112 unsigned int cmplqid); 1113int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 1114 struct net_device *dev, unsigned int iqid); 1115irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1116int t4_sge_init(struct adapter *adap); 1117void t4_sge_start(struct adapter *adap); 1118void t4_sge_stop(struct adapter *adap); 1119int cxgb_busy_poll(struct napi_struct *napi); 1120int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1121 unsigned int cnt); 1122void cxgb4_set_ethtool_ops(struct net_device *netdev); 1123int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1124extern int dbfifo_int_thresh; 1125 1126#define for_each_port(adapter, iter) \ 1127 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1128 1129static inline int is_bypass(struct adapter *adap) 1130{ 1131 return adap->params.bypass; 1132} 1133 1134static inline int is_bypass_device(int device) 1135{ 1136 /* this should be set based upon device capabilities */ 1137 switch (device) { 1138 case 0x440b: 1139 case 0x440c: 1140 return 1; 1141 default: 1142 return 0; 1143 } 1144} 1145 1146static inline int is_10gbt_device(int device) 1147{ 1148 /* this should be set based upon device capabilities */ 1149 switch (device) { 1150 case 0x4409: 1151 case 0x4486: 1152 return 1; 1153 1154 default: 1155 return 0; 1156 } 1157} 1158 1159static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1160{ 1161 return adap->params.vpd.cclk / 1000; 1162} 1163 1164static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1165 unsigned int us) 1166{ 1167 return (us * adap->params.vpd.cclk) / 1000; 1168} 1169 1170static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1171 unsigned int ticks) 1172{ 1173 /* add Core Clock / 2 to round ticks to nearest uS */ 1174 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1175 adapter->params.vpd.cclk); 1176} 1177 1178void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1179 u32 val); 1180 1181int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1182 int size, void *rpl, bool sleep_ok, int timeout); 1183int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1184 void *rpl, bool sleep_ok); 1185 1186static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1187 const void *cmd, int size, void *rpl, 1188 int timeout) 1189{ 1190 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1191 timeout); 1192} 1193 1194static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1195 int size, void *rpl) 1196{ 1197 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1198} 1199 1200static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1201 int size, void *rpl) 1202{ 1203 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1204} 1205 1206void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1207 unsigned int data_reg, const u32 *vals, 1208 unsigned int nregs, unsigned int start_idx); 1209void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1210 unsigned int data_reg, u32 *vals, unsigned int nregs, 1211 unsigned int start_idx); 1212void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1213 1214struct fw_filter_wr; 1215 1216void t4_intr_enable(struct adapter *adapter); 1217void t4_intr_disable(struct adapter *adapter); 1218int t4_slow_intr_handler(struct adapter *adapter); 1219 1220int t4_wait_dev_ready(void __iomem *regs); 1221int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1222 struct link_config *lc); 1223int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1224 1225u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1226u32 t4_get_util_window(struct adapter *adap); 1227void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1228 1229#define T4_MEMORY_WRITE 0 1230#define T4_MEMORY_READ 1 1231int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1232 void *buf, int dir); 1233static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1234 u32 len, __be32 *buf) 1235{ 1236 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1237} 1238 1239unsigned int t4_get_regs_len(struct adapter *adapter); 1240void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1241 1242int t4_seeprom_wp(struct adapter *adapter, bool enable); 1243int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1244int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1245int t4_read_flash(struct adapter *adapter, unsigned int addr, 1246 unsigned int nwords, u32 *data, int byte_oriented); 1247int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1248int t4_load_phy_fw(struct adapter *adap, 1249 int win, spinlock_t *lock, 1250 int (*phy_fw_version)(const u8 *, size_t), 1251 const u8 *phy_fw_data, size_t phy_fw_size); 1252int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1253int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1254int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1255 const u8 *fw_data, unsigned int size, int force); 1256unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1257int t4_check_fw_version(struct adapter *adap); 1258int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1259int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1260int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1261int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1262 const u8 *fw_data, unsigned int fw_size, 1263 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1264int t4_prep_adapter(struct adapter *adapter); 1265 1266enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1267int t4_bar2_sge_qregs(struct adapter *adapter, 1268 unsigned int qid, 1269 enum t4_bar2_qtype qtype, 1270 int user, 1271 u64 *pbar2_qoffset, 1272 unsigned int *pbar2_qid); 1273 1274unsigned int qtimer_val(const struct adapter *adap, 1275 const struct sge_rspq *q); 1276 1277int t4_init_devlog_params(struct adapter *adapter); 1278int t4_init_sge_params(struct adapter *adapter); 1279int t4_init_tp_params(struct adapter *adap); 1280int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1281int t4_init_rss_mode(struct adapter *adap, int mbox); 1282int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1283void t4_fatal_err(struct adapter *adapter); 1284int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1285 int start, int n, const u16 *rspq, unsigned int nrspq); 1286int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1287 unsigned int flags); 1288int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1289 unsigned int flags, unsigned int defq); 1290int t4_read_rss(struct adapter *adapter, u16 *entries); 1291void t4_read_rss_key(struct adapter *adapter, u32 *key); 1292void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1293void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1294 u32 *valp); 1295void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1296 u32 *vfl, u32 *vfh); 1297u32 t4_read_rss_pf_map(struct adapter *adapter); 1298u32 t4_read_rss_pf_mask(struct adapter *adapter); 1299 1300unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1301void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1302void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1303int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1304 size_t n); 1305int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1306 size_t n); 1307int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1308 unsigned int *valp); 1309int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1310 const unsigned int *valp); 1311int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1312void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1313 unsigned int *pif_req_wrptr, 1314 unsigned int *pif_rsp_wrptr); 1315void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1316void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1317const char *t4_get_port_type_description(enum fw_port_type port_type); 1318void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1319void t4_get_port_stats_offset(struct adapter *adap, int idx, 1320 struct port_stats *stats, 1321 struct port_stats *offset); 1322void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1323void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1324void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1325void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1326 unsigned int mask, unsigned int val); 1327void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1328void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1329void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1330void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1331void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1332void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1333 struct tp_tcp_stats *v6); 1334void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1335 struct tp_fcoe_stats *st); 1336void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1337 const unsigned short *alpha, const unsigned short *beta); 1338 1339void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1340 1341void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1342void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1343 1344void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1345 const u8 *addr); 1346int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1347 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1348 1349int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1350 enum dev_master master, enum dev_state *state); 1351int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1352int t4_early_init(struct adapter *adap, unsigned int mbox); 1353int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1354int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1355 unsigned int cache_line_size); 1356int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1357int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1358 unsigned int vf, unsigned int nparams, const u32 *params, 1359 u32 *val); 1360int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1361 unsigned int vf, unsigned int nparams, const u32 *params, 1362 u32 *val, int rw); 1363int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1364 unsigned int pf, unsigned int vf, 1365 unsigned int nparams, const u32 *params, 1366 const u32 *val, int timeout); 1367int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1368 unsigned int vf, unsigned int nparams, const u32 *params, 1369 const u32 *val); 1370int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1371 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1372 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1373 unsigned int vi, unsigned int cmask, unsigned int pmask, 1374 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1375int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1376 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1377 unsigned int *rss_size); 1378int t4_free_vi(struct adapter *adap, unsigned int mbox, 1379 unsigned int pf, unsigned int vf, 1380 unsigned int viid); 1381int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1382 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1383 bool sleep_ok); 1384int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1385 unsigned int viid, bool free, unsigned int naddr, 1386 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1387int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1388 int idx, const u8 *addr, bool persist, bool add_smt); 1389int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1390 bool ucast, u64 vec, bool sleep_ok); 1391int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1392 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1393int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1394 bool rx_en, bool tx_en); 1395int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1396 unsigned int nblinks); 1397int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1398 unsigned int mmd, unsigned int reg, u16 *valp); 1399int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1400 unsigned int mmd, unsigned int reg, u16 val); 1401int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1402 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1403 unsigned int fl0id, unsigned int fl1id); 1404int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1405 unsigned int vf, unsigned int eqid); 1406int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1407 unsigned int vf, unsigned int eqid); 1408int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1409 unsigned int vf, unsigned int eqid); 1410int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1411int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1412void t4_db_full(struct adapter *adapter); 1413void t4_db_dropped(struct adapter *adapter); 1414int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1415 int filter_index, int enable); 1416void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1417 int filter_index, int *enabled); 1418int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1419 u32 addr, u32 val); 1420void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1421void t4_free_mem(void *addr); 1422void t4_idma_monitor_init(struct adapter *adapter, 1423 struct sge_idma_monitor_state *idma); 1424void t4_idma_monitor(struct adapter *adapter, 1425 struct sge_idma_monitor_state *idma, 1426 int hz, int ticks); 1427#endif /* __CXGB4_H__ */ 1428