1#ifndef __CARD_DDCB_H__
2#define __CARD_DDCB_H__
3
4/**
5 * IBM Accelerator Family 'GenWQE'
6 *
7 * (C) Copyright IBM Corp. 2013
8 *
9 * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
10 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
11 * Author: Michael Jung <mijung@gmx.net>
12 * Author: Michael Ruettger <michael@ibmra.de>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2, or (at your option)
17 * any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 */
24
25#include <linux/types.h>
26#include <asm/byteorder.h>
27
28#include "genwqe_driver.h"
29#include "card_base.h"
30
31/**
32 * struct ddcb - Device Driver Control Block DDCB
33 * @hsi:        Hardware software interlock
34 * @shi:        Software hardware interlock. Hsi and shi are used to interlock
35 *              software and hardware activities. We are using a compare and
36 *              swap operation to ensure that there are no races when
37 *              activating new DDCBs on the queue, or when we need to
38 *              purge a DDCB from a running queue.
39 * @acfunc:     Accelerator function addresses a unit within the chip
40 * @cmd:        Command to work on
41 * @cmdopts_16: Options for the command
42 * @asiv:       Input data
43 * @asv:        Output data
44 *
45 * The DDCB data format is big endian. Multiple consequtive DDBCs form
46 * a DDCB queue.
47 */
48#define ASIV_LENGTH		104 /* Old specification without ATS field */
49#define ASIV_LENGTH_ATS		96  /* New specification with ATS field */
50#define ASV_LENGTH		64
51
52struct ddcb {
53	union {
54		__be32 icrc_hsi_shi_32;	/* iCRC, Hardware/SW interlock */
55		struct {
56			__be16	icrc_16;
57			u8	hsi;
58			u8	shi;
59		};
60	};
61	u8  pre;		/* Preamble */
62	u8  xdir;		/* Execution Directives */
63	__be16 seqnum_16;	/* Sequence Number */
64
65	u8  acfunc;		/* Accelerator Function.. */
66	u8  cmd;		/* Command. */
67	__be16 cmdopts_16;	/* Command Options */
68	u8  sur;		/* Status Update Rate */
69	u8  psp;		/* Protection Section Pointer */
70	__be16 rsvd_0e_16;	/* Reserved invariant */
71
72	__be64 fwiv_64;		/* Firmware Invariant. */
73
74	union {
75		struct {
76			__be64 ats_64;  /* Address Translation Spec */
77			u8     asiv[ASIV_LENGTH_ATS]; /* New ASIV */
78		} n;
79		u8  __asiv[ASIV_LENGTH];	/* obsolete */
80	};
81	u8     asv[ASV_LENGTH];	/* Appl Spec Variant */
82
83	__be16 rsvd_c0_16;	/* Reserved Variant */
84	__be16 vcrc_16;		/* Variant CRC */
85	__be32 rsvd_32;		/* Reserved unprotected */
86
87	__be64 deque_ts_64;	/* Deque Time Stamp. */
88
89	__be16 retc_16;		/* Return Code */
90	__be16 attn_16;		/* Attention/Extended Error Codes */
91	__be32 progress_32;	/* Progress indicator. */
92
93	__be64 cmplt_ts_64;	/* Completion Time Stamp. */
94
95	/* The following layout matches the new service layer format */
96	__be32 ibdc_32;		/* Inbound Data Count  (* 256) */
97	__be32 obdc_32;		/* Outbound Data Count (* 256) */
98
99	__be64 rsvd_SLH_64;	/* Reserved for hardware */
100	union {			/* private data for driver */
101		u8	priv[8];
102		__be64	priv_64;
103	};
104	__be64 disp_ts_64;	/* Dispatch TimeStamp */
105} __attribute__((__packed__));
106
107/* CRC polynomials for DDCB */
108#define CRC16_POLYNOMIAL	0x1021
109
110/*
111 * SHI: Software to Hardware Interlock
112 *   This 1 byte field is written by software to interlock the
113 *   movement of one queue entry to another with the hardware in the
114 *   chip.
115 */
116#define DDCB_SHI_INTR		0x04 /* Bit 2 */
117#define DDCB_SHI_PURGE		0x02 /* Bit 1 */
118#define DDCB_SHI_NEXT		0x01 /* Bit 0 */
119
120/*
121 * HSI: Hardware to Software interlock
122 * This 1 byte field is written by hardware to interlock the movement
123 * of one queue entry to another with the software in the chip.
124 */
125#define DDCB_HSI_COMPLETED	0x40 /* Bit 6 */
126#define DDCB_HSI_FETCHED	0x04 /* Bit 2 */
127
128/*
129 * Accessing HSI/SHI is done 32-bit wide
130 *   Normally 16-bit access would work too, but on some platforms the
131 *   16 compare and swap operation is not supported. Therefore
132 *   switching to 32-bit such that those platforms will work too.
133 *
134 *                                         iCRC HSI/SHI
135 */
136#define DDCB_INTR_BE32		cpu_to_be32(0x00000004)
137#define DDCB_PURGE_BE32		cpu_to_be32(0x00000002)
138#define DDCB_NEXT_BE32		cpu_to_be32(0x00000001)
139#define DDCB_COMPLETED_BE32	cpu_to_be32(0x00004000)
140#define DDCB_FETCHED_BE32	cpu_to_be32(0x00000400)
141
142/* Definitions of DDCB presets */
143#define DDCB_PRESET_PRE		0x80
144#define ICRC_LENGTH(n)		((n) + 8 + 8 + 8)  /* used ASIV + hdr fields */
145#define VCRC_LENGTH(n)		((n))		   /* used ASV */
146
147/*
148 * Genwqe Scatter Gather list
149 *   Each element has up to 8 entries.
150 *   The chaining element is element 0 cause of prefetching needs.
151 */
152
153/*
154 * 0b0110 Chained descriptor. The descriptor is describing the next
155 * descriptor list.
156 */
157#define SG_CHAINED		(0x6)
158
159/*
160 * 0b0010 First entry of a descriptor list. Start from a Buffer-Empty
161 * condition.
162 */
163#define SG_DATA			(0x2)
164
165/*
166 * 0b0000 Early terminator. This is the last entry on the list
167 * irregardless of the length indicated.
168 */
169#define SG_END_LIST		(0x0)
170
171/**
172 * struct sglist - Scatter gather list
173 * @target_addr:       Either a dma addr of memory to work on or a
174 *                     dma addr or a subsequent sglist block.
175 * @len:               Length of the data block.
176 * @flags:             See above.
177 *
178 * Depending on the command the GenWQE card can use a scatter gather
179 * list to describe the memory it works on. Always 8 sg_entry's form
180 * a block.
181 */
182struct sg_entry {
183	__be64 target_addr;
184	__be32 len;
185	__be32 flags;
186};
187
188#endif /* __CARD_DDCB_H__ */
189