Searched refs:div (Results 1 - 200 of 590) sorted by relevance

123

/linux-4.1.27/arch/arm/mach-omap2/
H A Dclock_common_data.c23 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_3XXX },
24 { .div = 0 }
28 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
29 { .div = 0 }
33 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_3XXX },
34 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_3XXX },
35 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_3XXX },
36 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_3XXX },
37 { .div = 0 }
41 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
42 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
43 { .div = 3, .val = 3, .flags = RATE_IN_243X },
44 { .div = 0 },
51 { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
52 { .div = 0 },
56 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
57 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
58 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
59 { .div = 0 },
63 { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
64 { .div = 0 },
68 { .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
69 { .div = 0 },
73 { .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
74 { .div = 0 },
78 { .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
79 { .div = 0 },
83 { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
84 { .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
85 { .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
86 { .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
87 { .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
88 { .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
89 { .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
90 { .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
91 { .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
92 { .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
93 { .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
94 { .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
95 { .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
96 { .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
97 { .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
98 { .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
99 { .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
100 { .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
101 { .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
102 { .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
103 { .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
104 { .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
105 { .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
106 { .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
107 { .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
108 { .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
109 { .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
110 { .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
111 { .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
112 { .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
113 { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
114 { .div = 0 },
H A Dclkt_clksel.c131 for (clkr = clks->rates; clkr->div; clkr++) { _clksel_to_divisor()
139 if (!clkr->div) { _clksel_to_divisor()
147 return clkr->div; _clksel_to_divisor()
153 * @div: integer divisor to search for
160 static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) _divisor_to_clksel() argument
167 WARN_ON(div == 0); _divisor_to_clksel()
174 for (clkr = clks->rates; clkr->div; clkr++) { _divisor_to_clksel()
178 if (clkr->div == div) _divisor_to_clksel()
182 if (!clkr->div) { _divisor_to_clksel()
184 __clk_get_name(clk->hw.clk), div, _divisor_to_clksel()
256 for (clkr = clks->rates; clkr->div; clkr++) { omap2_clksel_round_rate_div()
261 if (clkr->div <= last_div) omap2_clksel_round_rate_div()
265 last_div = clkr->div; omap2_clksel_round_rate_div()
267 test_rate = parent_rate / clkr->div; omap2_clksel_round_rate_div()
273 if (!clkr->div) { omap2_clksel_round_rate_div()
279 *new_div = clkr->div; omap2_clksel_round_rate_div()
282 (parent_rate / clkr->div)); omap2_clksel_round_rate_div()
284 return parent_rate / clkr->div; omap2_clksel_round_rate_div()
327 for (clkr = clks->rates; clkr->div && !found; clkr++) { omap2_clksel_find_parent_index()
359 u32 div = 0; omap2_clksel_recalc() local
365 div = _read_divisor(clk); omap2_clksel_recalc()
366 if (!div) omap2_clksel_recalc()
369 rate = parent_rate / div; omap2_clksel_recalc()
371 pr_debug("%s: recalc'd %s's rate to %lu (div %d)\n", __func__, omap2_clksel_recalc()
372 __clk_get_name(hw->clk), rate, div); omap2_clksel_recalc()
H A Dclkt2xxx_dpllcore.c115 u32 cur_rate, low, mult, div, valid_rate, done_rate; omap2_reprogram_dpllcore() local
144 div = ((curr_prcm_set->xtal_speed / 1000000) - 1); omap2_reprogram_dpllcore()
156 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); omap2_reprogram_dpllcore()
/linux-4.1.27/drivers/clk/berlin/
H A Dberlin2-div.c26 #include "berlin2-div.h"
46 * (D) constant div-by-3 clock divider
48 * (F) constant div-by-3 clock mux controlled by <D3Switch>
56 * Also, clock gate and pll mux is not available on every div cell, so
77 struct berlin2_div *div = to_berlin2_div(hw); berlin2_div_is_enabled() local
78 struct berlin2_div_map *map = &div->map; berlin2_div_is_enabled()
81 if (div->lock) berlin2_div_is_enabled()
82 spin_lock(div->lock); berlin2_div_is_enabled()
84 reg = readl_relaxed(div->base + map->gate_offs); berlin2_div_is_enabled()
87 if (div->lock) berlin2_div_is_enabled()
88 spin_unlock(div->lock); berlin2_div_is_enabled()
95 struct berlin2_div *div = to_berlin2_div(hw); berlin2_div_enable() local
96 struct berlin2_div_map *map = &div->map; berlin2_div_enable()
99 if (div->lock) berlin2_div_enable()
100 spin_lock(div->lock); berlin2_div_enable()
102 reg = readl_relaxed(div->base + map->gate_offs); berlin2_div_enable()
104 writel_relaxed(reg, div->base + map->gate_offs); berlin2_div_enable()
106 if (div->lock) berlin2_div_enable()
107 spin_unlock(div->lock); berlin2_div_enable()
114 struct berlin2_div *div = to_berlin2_div(hw); berlin2_div_disable() local
115 struct berlin2_div_map *map = &div->map; berlin2_div_disable()
118 if (div->lock) berlin2_div_disable()
119 spin_lock(div->lock); berlin2_div_disable()
121 reg = readl_relaxed(div->base + map->gate_offs); berlin2_div_disable()
123 writel_relaxed(reg, div->base + map->gate_offs); berlin2_div_disable()
125 if (div->lock) berlin2_div_disable()
126 spin_unlock(div->lock); berlin2_div_disable()
131 struct berlin2_div *div = to_berlin2_div(hw); berlin2_div_set_parent() local
132 struct berlin2_div_map *map = &div->map; berlin2_div_set_parent()
135 if (div->lock) berlin2_div_set_parent()
136 spin_lock(div->lock); berlin2_div_set_parent()
139 reg = readl_relaxed(div->base + map->pll_switch_offs); berlin2_div_set_parent()
144 writel_relaxed(reg, div->base + map->pll_switch_offs); berlin2_div_set_parent()
148 reg = readl_relaxed(div->base + map->pll_select_offs); berlin2_div_set_parent()
151 writel_relaxed(reg, div->base + map->pll_select_offs); berlin2_div_set_parent()
154 if (div->lock) berlin2_div_set_parent()
155 spin_unlock(div->lock); berlin2_div_set_parent()
162 struct berlin2_div *div = to_berlin2_div(hw); berlin2_div_get_parent() local
163 struct berlin2_div_map *map = &div->map; berlin2_div_get_parent()
167 if (div->lock) berlin2_div_get_parent()
168 spin_lock(div->lock); berlin2_div_get_parent()
171 reg = readl_relaxed(div->base + map->pll_switch_offs); berlin2_div_get_parent()
174 reg = readl_relaxed(div->base + map->pll_select_offs); berlin2_div_get_parent()
180 if (div->lock) berlin2_div_get_parent()
181 spin_unlock(div->lock); berlin2_div_get_parent()
189 struct berlin2_div *div = to_berlin2_div(hw); berlin2_div_recalc_rate() local
190 struct berlin2_div_map *map = &div->map; berlin2_div_recalc_rate()
193 if (div->lock) berlin2_div_recalc_rate()
194 spin_lock(div->lock); berlin2_div_recalc_rate()
196 divsw = readl_relaxed(div->base + map->div_switch_offs) & berlin2_div_recalc_rate()
198 div3sw = readl_relaxed(div->base + map->div3_switch_offs) & berlin2_div_recalc_rate()
210 reg = readl_relaxed(div->base + map->div_select_offs); berlin2_div_recalc_rate()
216 if (div->lock) berlin2_div_recalc_rate()
217 spin_unlock(div->lock); berlin2_div_recalc_rate()
246 struct berlin2_div *div; berlin2_div_register() local
248 div = kzalloc(sizeof(*div), GFP_KERNEL); berlin2_div_register()
249 if (!div) berlin2_div_register()
253 memcpy(&div->map, map, sizeof(*map)); berlin2_div_register()
254 div->base = base; berlin2_div_register()
255 div->lock = lock; berlin2_div_register()
263 &div->hw, mux_ops, &div->hw, rate_ops, berlin2_div_register()
264 &div->hw, gate_ops, flags); berlin2_div_register()
/linux-4.1.27/drivers/clk/mxs/
H A Dclk-div.c45 struct clk_div *div = to_clk_div(hw); clk_div_recalc_rate() local
47 return div->ops->recalc_rate(&div->divider.hw, parent_rate); clk_div_recalc_rate()
53 struct clk_div *div = to_clk_div(hw); clk_div_round_rate() local
55 return div->ops->round_rate(&div->divider.hw, rate, prate); clk_div_round_rate()
61 struct clk_div *div = to_clk_div(hw); clk_div_set_rate() local
64 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); clk_div_set_rate()
66 ret = mxs_clk_wait(div->reg, div->busy); clk_div_set_rate()
80 struct clk_div *div; mxs_clk_div() local
84 div = kzalloc(sizeof(*div), GFP_KERNEL); mxs_clk_div()
85 if (!div) mxs_clk_div()
94 div->reg = reg; mxs_clk_div()
95 div->busy = busy; mxs_clk_div()
97 div->divider.reg = reg; mxs_clk_div()
98 div->divider.shift = shift; mxs_clk_div()
99 div->divider.width = width; mxs_clk_div()
100 div->divider.flags = CLK_DIVIDER_ONE_BASED; mxs_clk_div()
101 div->divider.lock = &mxs_lock; mxs_clk_div()
102 div->divider.hw.init = &init; mxs_clk_div()
103 div->ops = &clk_divider_ops; mxs_clk_div()
105 clk = clk_register(NULL, &div->divider.hw); mxs_clk_div()
107 kfree(div); mxs_clk_div()
H A Dclk-frac.c44 u32 div; clk_frac_recalc_rate() local
46 div = readl_relaxed(frac->reg) >> frac->shift; clk_frac_recalc_rate()
47 div &= (1 << frac->width) - 1; clk_frac_recalc_rate()
49 return (parent_rate >> frac->width) * div; clk_frac_recalc_rate()
57 u32 div; clk_frac_round_rate() local
66 div = tmp; clk_frac_round_rate()
68 if (!div) clk_frac_round_rate()
71 return (parent_rate >> frac->width) * div; clk_frac_round_rate()
79 u32 div, val; clk_frac_set_rate() local
88 div = tmp; clk_frac_set_rate()
90 if (!div) clk_frac_set_rate()
97 val |= div << frac->shift; clk_frac_set_rate()
H A Dclk.h60 const char *parent_name, unsigned int mult, unsigned int div) mxs_clk_fixed_factor()
63 CLK_SET_RATE_PARENT, mult, div); mxs_clk_fixed_factor()
59 mxs_clk_fixed_factor(const char *name, const char *parent_name, unsigned int mult, unsigned int div) mxs_clk_fixed_factor() argument
/linux-4.1.27/drivers/clk/ti/
H A Ddivider.c38 for (clkt = table; clkt->div; clkt++) _get_table_maxdiv()
39 if (clkt->div > maxdiv) _get_table_maxdiv()
40 maxdiv = clkt->div; _get_table_maxdiv()
60 for (clkt = table; clkt->div; clkt++) _get_table_div()
62 return clkt->div; _get_table_div()
78 unsigned int div) _get_table_val()
82 for (clkt = table; clkt->div; clkt++) _get_table_val()
83 if (clkt->div == div) _get_table_val()
88 static unsigned int _get_val(struct clk_divider *divider, u8 div) _get_val() argument
91 return div; _get_val()
93 return __ffs(div); _get_val()
95 return _get_table_val(divider->table, div); _get_val()
96 return div - 1; _get_val()
103 unsigned int div, val; ti_clk_divider_recalc_rate() local
108 div = _get_div(divider, val); ti_clk_divider_recalc_rate()
109 if (!div) { ti_clk_divider_recalc_rate()
116 return DIV_ROUND_UP(parent_rate, div); ti_clk_divider_recalc_rate()
126 unsigned int div) _is_valid_table_div()
130 for (clkt = table; clkt->div; clkt++) _is_valid_table_div()
131 if (clkt->div == div) _is_valid_table_div()
136 static bool _is_valid_div(struct clk_divider *divider, unsigned int div) _is_valid_div() argument
139 return is_power_of_2(div); _is_valid_div()
141 return _is_valid_table_div(divider->table, div); _is_valid_div()
206 int div; ti_clk_divider_round_rate() local
207 div = ti_clk_divider_bestdiv(hw, rate, prate); ti_clk_divider_round_rate()
209 return DIV_ROUND_UP(*prate, div); ti_clk_divider_round_rate()
216 unsigned int div, value; ti_clk_divider_set_rate() local
225 div = DIV_ROUND_UP(parent_rate, rate); ti_clk_divider_set_rate()
226 value = _get_val(divider, div); ti_clk_divider_set_rate()
262 struct clk_divider *div; _register_divider() local
274 div = kzalloc(sizeof(*div), GFP_KERNEL); _register_divider()
275 if (!div) { _register_divider()
287 div->reg = reg; _register_divider()
288 div->shift = shift; _register_divider()
289 div->width = width; _register_divider()
290 div->flags = clk_divider_flags; _register_divider()
291 div->lock = lock; _register_divider()
292 div->hw.init = &init; _register_divider()
293 div->table = table; _register_divider()
296 clk = clk_register(dev, &div->hw); _register_divider()
299 kfree(div); _register_divider()
310 int div; _get_div_table_from_setup() local
323 div = 1; _get_div_table_from_setup()
325 while (div < setup->max_div) { _get_div_table_from_setup()
327 div <<= 1; _get_div_table_from_setup()
329 div++; _get_div_table_from_setup()
351 table[valid_div].div = setup->dividers[i]; _get_div_table_from_setup()
364 struct clk_divider *div; ti_clk_build_component_div() local
370 div = kzalloc(sizeof(*div), GFP_KERNEL); ti_clk_build_component_div()
371 if (!div) ti_clk_build_component_div()
374 reg = (struct clk_omap_reg *)&div->reg; ti_clk_build_component_div()
379 div->flags |= CLK_DIVIDER_ONE_BASED; ti_clk_build_component_div()
382 div->flags |= CLK_DIVIDER_POWER_OF_TWO; ti_clk_build_component_div()
384 div->table = _get_div_table_from_setup(setup, &div->width); ti_clk_build_component_div()
386 div->shift = setup->bit_shift; ti_clk_build_component_div()
388 return &div->hw; ti_clk_build_component_div()
393 struct ti_clk_divider *div; ti_clk_register_divider() local
402 div = setup->data; ti_clk_register_divider()
406 reg_setup->index = div->module; ti_clk_register_divider()
407 reg_setup->offset = div->reg; ti_clk_register_divider()
409 if (div->flags & CLKF_INDEX_STARTS_AT_ONE) ti_clk_register_divider()
412 if (div->flags & CLKF_INDEX_POWER_OF_TWO) ti_clk_register_divider()
415 if (div->flags & CLKF_SET_RATE_PARENT) ti_clk_register_divider()
418 table = _get_div_table_from_setup(div, &width); ti_clk_register_divider()
422 clk = _register_divider(NULL, setup->name, div->parent, ti_clk_register_divider()
423 flags, (void __iomem *)reg, div->bit_shift, ti_clk_register_divider()
473 table[valid_div].div = val; ti_clk_get_div_table()
489 u32 div; _get_divider_width() local
493 if (of_property_read_u32(node, "ti,min-div", &min_div)) _get_divider_width()
496 if (of_property_read_u32(node, "ti,max-div", &max_div)) { _get_divider_width()
497 pr_err("no max-div for %s!\n", node->name); _get_divider_width()
505 div = min_div; _get_divider_width()
507 while (div < max_div) { _get_divider_width()
509 div <<= 1; _get_divider_width()
511 div++; _get_divider_width()
515 div = 0; _get_divider_width()
517 while (table[div].div) { _get_divider_width()
518 val = table[div].val; _get_divider_width()
519 div++; _get_divider_width()
564 * of_ti_divider_clk_setup - Setup function for simple div rate clock
603 struct clk_divider *div; of_ti_composite_divider_clk_setup() local
606 div = kzalloc(sizeof(*div), GFP_KERNEL); of_ti_composite_divider_clk_setup()
607 if (!div) of_ti_composite_divider_clk_setup()
610 if (ti_clk_divider_populate(node, &div->reg, &div->table, &val, of_ti_composite_divider_clk_setup()
611 &div->flags, &div->width, &div->shift) < 0) of_ti_composite_divider_clk_setup()
614 if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER)) of_ti_composite_divider_clk_setup()
618 kfree(div->table); of_ti_composite_divider_clk_setup()
619 kfree(div); of_ti_composite_divider_clk_setup()
77 _get_table_val(const struct clk_div_table *table, unsigned int div) _get_table_val() argument
125 _is_valid_table_div(const struct clk_div_table *table, unsigned int div) _is_valid_table_div() argument
H A Dfixed-factor.c39 u32 div, mult; of_ti_fixed_factor_clk_setup() local
42 if (of_property_read_u32(node, "ti,clock-div", &div)) { of_ti_fixed_factor_clk_setup()
43 pr_err("%s must have a clock-div property\n", node->name); of_ti_fixed_factor_clk_setup()
58 mult, div); of_ti_fixed_factor_clk_setup()
H A Dfapll.c79 void __iomem *div; member in struct:fapll_synth
319 if (!synth->div) ti_fapll_synth_recalc_rate()
350 synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M; ti_fapll_synth_recalc_rate()
363 post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M; ti_fapll_synth_get_frac_rate()
414 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate) ti_fapll_synth_round_rate()
449 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate) ti_fapll_synth_set_rate()
471 v = readl_relaxed(synth->div); ti_fapll_synth_set_rate()
475 writel_relaxed(v, synth->div); ti_fapll_synth_set_rate()
491 void __iomem *div, ti_fapll_synth_setup()
516 synth->div = div; ti_fapll_synth_setup()
606 void __iomem *freq, *div; ti_fapll_setup() local
620 div = freq + 4; ti_fapll_setup()
625 div = 0; ti_fapll_setup()
632 synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance, ti_fapll_setup()
489 ti_fapll_synth_setup(struct fapll_data *fd, void __iomem *freq, void __iomem *div, int index, const char *name, const char *parent, struct clk *pll_clk) ti_fapll_synth_setup() argument
H A Dclk-3xxx-legacy.c172 .div = 1,
198 .div = 1,
210 .div = 1,
266 .div = 1,
343 .div = 1,
369 .div = 1,
381 .div = 1,
412 .div = 1,
469 .div = 1,
558 .div = 2,
599 .div = 1,
628 .div = 1,
664 .div = 1,
676 .div = 1,
728 .div = 2,
750 .div = 1,
866 .div = 1,
878 .div = 8,
904 .div = 1,
1035 .div = 1,
1087 .div = 1,
1114 .div = 1,
1141 .div = 10,
1160 .div = 1,
1202 .div = 1,
1334 .div = 1,
1458 .div = 1,
1840 .div = 1,
1866 .div = 1,
1891 .div = 3,
1934 .div = 6,
1975 .div = 1,
2002 .div = 1,
2028 .div = 1,
2040 .div = 1,
2557 .div = 1,
2582 .div = 1,
2594 .div = 20,
2748 .div = 4,
2760 .div = 1,
2772 .div = 2,
2784 .div = 3,
2796 .div = 5,
2954 .div = 1,
3039 .div = 4,
3172 .div = 4,
3184 .div = 2,
3196 .div = 2,
3208 .div = 8,
3220 .div = 16,
3327 .div = 4,
3339 .div = 1,
3425 .div = 1,
3452 .div = 1,
3709 .div = 1,
3851 .div = 2,
3961 .div = 1,
H A Dcomposite.c127 struct clk_hw *div; ti_clk_register_composite() local
134 div = ti_clk_build_component_div(comp->divider); ti_clk_register_composite()
138 if (div) ti_clk_register_composite()
151 &ti_clk_mux_ops, div, ti_clk_register_composite()
/linux-4.1.27/drivers/clk/
H A Dclk-divider.c40 for (clkt = table; clkt->div; clkt++) _get_table_maxdiv()
41 if (clkt->div > maxdiv) _get_table_maxdiv()
42 maxdiv = clkt->div; _get_table_maxdiv()
51 for (clkt = table; clkt->div; clkt++) _get_table_mindiv()
52 if (clkt->div < mindiv) _get_table_mindiv()
53 mindiv = clkt->div; _get_table_mindiv()
74 for (clkt = table; clkt->div; clkt++) _get_table_div()
76 return clkt->div; _get_table_div()
93 unsigned int div) _get_table_val()
97 for (clkt = table; clkt->div; clkt++) _get_table_val()
98 if (clkt->div == div) _get_table_val()
104 unsigned int div, unsigned long flags) _get_val()
107 return div; _get_val()
109 return __ffs(div); _get_val()
111 return _get_table_val(table, div); _get_val()
112 return div - 1; _get_val()
120 unsigned int div; divider_recalc_rate() local
122 div = _get_div(table, val, flags); divider_recalc_rate()
123 if (!div) { divider_recalc_rate()
130 return DIV_ROUND_UP(parent_rate, div); divider_recalc_rate()
148 unsigned int div) _is_valid_table_div()
152 for (clkt = table; clkt->div; clkt++) _is_valid_table_div()
153 if (clkt->div == div) _is_valid_table_div()
158 static bool _is_valid_div(const struct clk_div_table *table, unsigned int div, _is_valid_div() argument
162 return is_power_of_2(div); _is_valid_div()
164 return _is_valid_table_div(table, div); _is_valid_div()
168 static int _round_up_table(const struct clk_div_table *table, int div) _round_up_table() argument
173 for (clkt = table; clkt->div; clkt++) { _round_up_table()
174 if (clkt->div == div) _round_up_table()
175 return clkt->div; _round_up_table()
176 else if (clkt->div < div) _round_up_table()
179 if ((clkt->div - div) < (up - div)) _round_up_table()
180 up = clkt->div; _round_up_table()
186 static int _round_down_table(const struct clk_div_table *table, int div) _round_down_table() argument
191 for (clkt = table; clkt->div; clkt++) { _round_down_table()
192 if (clkt->div == div) _round_down_table()
193 return clkt->div; _round_down_table()
194 else if (clkt->div > div) _round_down_table()
197 if ((div - clkt->div) < (div - down)) _round_down_table()
198 down = clkt->div; _round_down_table()
208 int div = DIV_ROUND_UP(parent_rate, rate); _div_round_up() local
211 div = __roundup_pow_of_two(div); _div_round_up()
213 div = _round_up_table(table, div); _div_round_up()
215 return div; _div_round_up()
261 static int _next_div(const struct clk_div_table *table, int div, _next_div() argument
264 div++; _next_div()
267 return __roundup_pow_of_two(div); _next_div()
269 return _round_up_table(table, div); _next_div()
271 return div; _next_div()
336 int div; divider_round_rate() local
338 div = clk_divider_bestdiv(hw, rate, prate, table, width, flags); divider_round_rate()
340 return DIV_ROUND_UP(*prate, div); divider_round_rate()
366 unsigned int div, value; divider_get_val() local
368 div = DIV_ROUND_UP(parent_rate, rate); divider_get_val()
370 if (!_is_valid_div(table, div, flags)) divider_get_val()
373 value = _get_val(table, div, flags); divider_get_val()
421 struct clk_divider *div; _register_divider() local
433 div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL); _register_divider()
434 if (!div) { _register_divider()
446 div->reg = reg; _register_divider()
447 div->shift = shift; _register_divider()
448 div->width = width; _register_divider()
449 div->flags = clk_divider_flags; _register_divider()
450 div->lock = lock; _register_divider()
451 div->hw.init = &init; _register_divider()
452 div->table = table; _register_divider()
455 clk = clk_register(dev, &div->hw); _register_divider()
458 kfree(div); _register_divider()
496 * @table: array of divider/value pairs ending with a div set to 0
512 struct clk_divider *div; clk_unregister_divider() local
519 div = to_clk_divider(hw); clk_unregister_divider()
522 kfree(div); clk_unregister_divider()
92 _get_table_val(const struct clk_div_table *table, unsigned int div) _get_table_val() argument
103 _get_val(const struct clk_div_table *table, unsigned int div, unsigned long flags) _get_val() argument
147 _is_valid_table_div(const struct clk_div_table *table, unsigned int div) _is_valid_table_div() argument
H A Dclk-cdce706.c31 #define CDCE706_DIVIDER(div) (13 + (div))
52 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4))
53 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1))
54 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div))
75 unsigned div; member in struct:cdce706_hw_data
173 "%s, pll: %d, mux: %d, mul: %u, div: %u\n", cdce706_pll_recalc_rate()
174 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); cdce706_pll_recalc_rate()
177 if (hwd->div && hwd->mul) { cdce706_pll_recalc_rate()
180 do_div(res, hwd->div); cdce706_pll_recalc_rate()
184 if (hwd->div) cdce706_pll_recalc_rate()
185 return parent_rate / hwd->div; cdce706_pll_recalc_rate()
194 unsigned long mul, div; cdce706_pll_round_rate() local
203 &mul, &div); cdce706_pll_round_rate()
205 hwd->div = div; cdce706_pll_round_rate()
208 "%s, pll: %d, mul: %lu, div: %lu\n", cdce706_pll_round_rate()
209 __func__, hwd->idx, mul, div); cdce706_pll_round_rate()
212 do_div(res, hwd->div); cdce706_pll_round_rate()
220 unsigned long mul = hwd->mul, div = hwd->div; cdce706_pll_set_rate() local
224 "%s, pll: %d, mul: %lu, div: %lu\n", cdce706_pll_set_rate()
225 __func__, hwd->idx, mul, div); cdce706_pll_set_rate()
230 ((div >> 8) & CDCE706_PLL_HI_M_MASK) | cdce706_pll_set_rate()
238 div & CDCE706_PLL_LOW_M_MASK); cdce706_pll_set_rate()
288 "%s, divider: %d, div: %u\n", cdce706_divider_recalc_rate()
289 __func__, hwd->idx, hwd->div); cdce706_divider_recalc_rate()
290 if (hwd->div) cdce706_divider_recalc_rate()
291 return parent_rate / hwd->div; cdce706_divider_recalc_rate()
300 unsigned long mul, div; cdce706_divider_round_rate() local
308 &mul, &div); cdce706_divider_round_rate()
310 div = CDCE706_DIVIDER_DIVIDER_MAX; cdce706_divider_round_rate()
318 for (div = CDCE706_PLL_FREQ_MIN / rate; best_diff && cdce706_divider_round_rate()
319 div <= CDCE706_PLL_FREQ_MAX / rate; ++div) { cdce706_divider_round_rate()
325 if (rate * div < CDCE706_PLL_FREQ_MIN) cdce706_divider_round_rate()
328 rational_best_approximation(rate * div, gp_rate, cdce706_divider_round_rate()
334 do_div(div_rate64, div); cdce706_divider_round_rate()
340 best_div = div; cdce706_divider_round_rate()
343 __func__, gp_rate, n, m, div, div_rate); cdce706_divider_round_rate()
347 div = best_div; cdce706_divider_round_rate()
351 __func__, *parent_rate, rate * div); cdce706_divider_round_rate()
352 *parent_rate = rate * div; cdce706_divider_round_rate()
354 hwd->div = div; cdce706_divider_round_rate()
357 "%s, divider: %d, div: %lu\n", cdce706_divider_round_rate()
358 __func__, hwd->idx, div); cdce706_divider_round_rate()
360 return *parent_rate / div; cdce706_divider_round_rate()
369 "%s, divider: %d, div: %u\n", cdce706_divider_set_rate()
370 __func__, hwd->idx, hwd->div); cdce706_divider_set_rate()
375 hwd->div); cdce706_divider_set_rate()
541 cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8); cdce706_register_plls()
546 "%s: i: %u, div: %u, mul: %u, mux: %d\n", __func__, i, cdce706_register_plls()
547 cdce->pll[i].div, cdce->pll[i].mul, cdce->pll[i].mux); cdce706_register_plls()
580 cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK; cdce706_register_dividers()
582 "%s: i: %u, parent: %u, div: %u\n", __func__, i, cdce706_register_dividers()
583 cdce->divider[i].parent, cdce->divider[i].div); cdce706_register_dividers()
H A Dclk-fixed-factor.c22 * rate - rate is fixed. clk->rate = parent->rate / div * mult
35 do_div(rate, fix->div); clk_factor_recalc_rate()
47 best_parent = (rate / fix->mult) * fix->div; clk_factor_round_rate()
52 return (*prate / fix->div) * fix->mult; clk_factor_round_rate()
70 unsigned int mult, unsigned int div) clk_register_fixed_factor()
84 fix->div = div; clk_register_fixed_factor()
111 u32 div, mult; of_fixed_factor_clk_setup() local
113 if (of_property_read_u32(node, "clock-div", &div)) { of_fixed_factor_clk_setup()
114 pr_err("%s Fixed factor clock <%s> must have a clock-div property\n", of_fixed_factor_clk_setup()
129 mult, div); of_fixed_factor_clk_setup()
68 clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) clk_register_fixed_factor() argument
H A Dclk-fractional-divider.c53 unsigned div; clk_fd_round_rate() local
58 div = gcd(*prate, rate); clk_fd_round_rate()
60 while ((*prate / div) > maxn) { clk_fd_round_rate()
61 div <<= 1; clk_fd_round_rate()
73 unsigned long div; clk_fd_set_rate() local
77 div = gcd(parent_rate, rate); clk_fd_set_rate()
78 m = rate / div; clk_fd_set_rate()
79 n = parent_rate / div; clk_fd_set_rate()
H A Dclk-highbank.c208 u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4; clk_cpu_periphclk_recalc_rate() local
209 return parent_rate / div; clk_cpu_periphclk_recalc_rate()
220 u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT; clk_cpu_a9bclk_recalc_rate() local
222 return parent_rate / (div + 2); clk_cpu_a9bclk_recalc_rate()
233 u32 div; clk_periclk_recalc_rate() local
235 div = readl(hbclk->reg) & 0x1f; clk_periclk_recalc_rate()
236 div++; clk_periclk_recalc_rate()
237 div *= 2; clk_periclk_recalc_rate()
239 return parent_rate / div; clk_periclk_recalc_rate()
245 u32 div; clk_periclk_round_rate() local
247 div = *parent_rate / rate; clk_periclk_round_rate()
248 div++; clk_periclk_round_rate()
249 div &= ~0x1; clk_periclk_round_rate()
251 return *parent_rate / div; clk_periclk_round_rate()
258 u32 div; clk_periclk_set_rate() local
260 div = parent_rate / rate; clk_periclk_set_rate()
261 if (div & 0x1) clk_periclk_set_rate()
264 writel(div >> 1, hbclk->reg); clk_periclk_set_rate()
H A Dclk-clps711x.c32 { .val = 0, .div = 32, },
33 { .val = 1, .div = 8, },
34 { .val = 2, .div = 2, },
35 { .val = 3, .div = 1, },
39 { .val = 0, .div = 256, },
40 { .val = 1, .div = 1, },
H A Dclk-moxart.c60 unsigned int div, val; moxart_of_apb_clk_init() local
79 div = div_idx[val] * 2; moxart_of_apb_clk_init()
87 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, 1, div); moxart_of_apb_clk_init()
/linux-4.1.27/drivers/mmc/host/
H A Dsdhci-cns3xxx.c29 int div = 1; sdhci_cns3xxx_set_clock() local
40 while (host->max_clk / div > clock) { sdhci_cns3xxx_set_clock()
45 if (div < 4) sdhci_cns3xxx_set_clock()
46 div += 1; sdhci_cns3xxx_set_clock()
47 else if (div < 256) sdhci_cns3xxx_set_clock()
48 div *= 2; sdhci_cns3xxx_set_clock()
54 clock, host->max_clk / div); sdhci_cns3xxx_set_clock()
57 if (div != 3) sdhci_cns3xxx_set_clock()
58 div >>= 1; sdhci_cns3xxx_set_clock()
60 clk = div << SDHCI_DIVIDER_SHIFT; sdhci_cns3xxx_set_clock()
H A Ddw_mmc-rockchip.c47 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) dw_mci_rk3288_set_ios()
49 * Note: div can only be 0 or 1 dw_mci_rk3288_set_ios()
51 * div must be set 1 dw_mci_rk3288_set_ios()
H A Dsdhci-of-arasan.c41 u32 div; sdhci_arasan_get_timeout_clock() local
45 div = readl(host->ioaddr + SDHCI_ARASAN_CLK_CTRL_OFFSET); sdhci_arasan_get_timeout_clock()
46 div = (div & CLK_CTRL_TIMEOUT_MASK) >> CLK_CTRL_TIMEOUT_SHIFT; sdhci_arasan_get_timeout_clock()
49 freq /= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP + div); sdhci_arasan_get_timeout_clock()
H A Ddw_mmc-exynos.c255 u8 div; dw_mci_exynos_adjust_clock() local
271 div = dw_mci_exynos_get_ciu_div(host); dw_mci_exynos_adjust_clock()
272 ret = clk_set_rate(host->ciu_clk, wanted * div); dw_mci_exynos_adjust_clock()
276 wanted * div, ret); dw_mci_exynos_adjust_clock()
278 host->bus_hz = actual / div; dw_mci_exynos_adjust_clock()
321 u32 div = 0; dw_mci_exynos_parse_dt() local
339 of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div); dw_mci_exynos_parse_dt()
340 priv->ciu_div = div; dw_mci_exynos_parse_dt()
348 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); dw_mci_exynos_parse_dt()
355 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); dw_mci_exynos_parse_dt()
H A Dsdhci-of-esdhc.c203 int div = 1; esdhc_of_set_clock() local
227 while (host->max_clk / pre_div / div > clock && div < 16) esdhc_of_set_clock()
228 div++; esdhc_of_set_clock()
231 clock, host->max_clk / pre_div / div); esdhc_of_set_clock()
234 div--; esdhc_of_set_clock()
238 | (div << ESDHC_DIVIDER_SHIFT) esdhc_of_set_clock()
/linux-4.1.27/arch/arm/mach-shmobile/
H A Dclock.h13 int div; member in struct:clk_ratio
19 .div = d, \
39 (p)->div = d; \
H A Dclock.c31 return clk->parent->rate / p->div * p->mul; shmobile_fixed_ratio_clk_recalc()
H A Dtimer.c22 unsigned int mult, unsigned int div) shmobile_setup_delay_hz()
32 unsigned int value = HZ * div / mult; shmobile_setup_delay_hz()
21 shmobile_setup_delay_hz(unsigned int max_cpu_core_hz, unsigned int mult, unsigned int div) shmobile_setup_delay_hz() argument
/linux-4.1.27/arch/mips/jz4740/
H A Dclock.c243 int div; jz_clk_main_round_rate() local
245 div = parent_rate / rate; jz_clk_main_round_rate()
246 if (div > 32) jz_clk_main_round_rate()
248 else if (div < 1) jz_clk_main_round_rate()
251 div &= (0x3 << (ffs(div) - 1)); jz_clk_main_round_rate()
253 return parent_rate / div; jz_clk_main_round_rate()
259 uint32_t div; jz_clk_main_get_rate() local
261 div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); jz_clk_main_get_rate()
263 div >>= mclk->div_offset; jz_clk_main_get_rate()
264 div &= 0xf; jz_clk_main_get_rate()
266 if (div >= ARRAY_SIZE(jz_clk_main_divs)) jz_clk_main_get_rate()
267 div = ARRAY_SIZE(jz_clk_main_divs) - 1; jz_clk_main_get_rate()
269 return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div]; jz_clk_main_get_rate()
276 int div; jz_clk_main_set_rate() local
281 div = parent_rate / rate; jz_clk_main_set_rate()
283 i = (ffs(div) - 1) << 1; jz_clk_main_set_rate()
284 if (i > 0 && !(div & BIT(i-1))) jz_clk_main_set_rate()
449 int div; jz_clk_udc_set_rate() local
454 div = clk_get_rate(clk->parent) / rate - 1; jz_clk_udc_set_rate()
456 if (div < 0) jz_clk_udc_set_rate()
457 div = 0; jz_clk_udc_set_rate()
458 else if (div > 63) jz_clk_udc_set_rate()
459 div = 63; jz_clk_udc_set_rate()
461 jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET, jz_clk_udc_set_rate()
468 int div; jz_clk_udc_get_rate() local
473 div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK); jz_clk_udc_get_rate()
474 div >>= JZ_CLOCK_CTRL_UDIV_OFFSET; jz_clk_udc_get_rate()
475 div += 1; jz_clk_udc_get_rate()
477 return clk_get_rate(clk->parent) / div; jz_clk_udc_get_rate()
483 int div; jz_clk_divided_get_rate() local
488 div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1; jz_clk_divided_get_rate()
490 return clk_get_rate(clk->parent) / div; jz_clk_divided_get_rate()
496 int div; jz_clk_divided_set_rate() local
501 div = clk_get_rate(clk->parent) / rate - 1; jz_clk_divided_set_rate()
503 if (div < 0) jz_clk_divided_set_rate()
504 div = 0; jz_clk_divided_set_rate()
505 else if (div > dclk->mask) jz_clk_divided_set_rate()
506 div = dclk->mask; jz_clk_divided_set_rate()
508 jz_clk_reg_write_mask(dclk->reg, div, dclk->mask); jz_clk_divided_set_rate()
515 int div; jz_clk_ldclk_round_rate() local
521 div = parent_rate / rate; jz_clk_ldclk_round_rate()
522 if (div < 1) jz_clk_ldclk_round_rate()
523 div = 1; jz_clk_ldclk_round_rate()
524 else if (div > 32) jz_clk_ldclk_round_rate()
525 div = 32; jz_clk_ldclk_round_rate()
527 return parent_rate / div; jz_clk_ldclk_round_rate()
532 int div; jz_clk_ldclk_set_rate() local
537 div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1; jz_clk_ldclk_set_rate()
538 if (div < 0) jz_clk_ldclk_set_rate()
539 div = 0; jz_clk_ldclk_set_rate()
540 else if (div > 31) jz_clk_ldclk_set_rate()
541 div = 31; jz_clk_ldclk_set_rate()
543 jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET, jz_clk_ldclk_set_rate()
551 int div; jz_clk_ldclk_get_rate() local
553 div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK; jz_clk_ldclk_get_rate()
554 div >>= JZ_CLOCK_CTRL_LDIV_OFFSET; jz_clk_ldclk_get_rate()
556 return jz_clk_pll_half_get_rate(clk->parent) / (div + 1); jz_clk_ldclk_get_rate()
/linux-4.1.27/drivers/clk/qcom/
H A Dclk-regmap-divider.c40 u32 div; div_set_rate() local
42 div = divider_get_val(rate, parent_rate, NULL, divider->width, div_set_rate()
47 div << divider->shift); div_set_rate()
55 u32 div; div_recalc_rate() local
57 regmap_read(clkr->regmap, divider->reg, &div); div_recalc_rate()
58 div >>= divider->shift; div_recalc_rate()
59 div &= BIT(divider->width) - 1; div_recalc_rate()
61 return divider_recalc_rate(hw, parent_rate, div, NULL, div_recalc_rate()
H A Dclk-rcg2.c438 unsigned long parent_rate, div; clk_byte_determine_rate() local
449 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; clk_byte_determine_rate()
450 div = min_t(u32, div, mask); clk_byte_determine_rate()
452 return calc_rate(parent_rate, 0, 0, 0, div); clk_byte_determine_rate()
460 unsigned long div; clk_byte_set_rate() local
463 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; clk_byte_set_rate()
464 div = min_t(u32, div, mask); clk_byte_set_rate()
466 f.pre_div = div; clk_byte_set_rate()
/linux-4.1.27/drivers/clk/spear/
H A Dclk-frac-synth.c27 * Fout= Fin/2*div (division factor)
28 * div is 17 bits:-
31 * div is (16-14 bits).(13-0 bits) (in binary)
33 * Fout = Fin/(2 * div)
34 * Fout = ((Fin / 10000)/(2 * div)) * 10000
35 * Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
36 * Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000
38 * div << 14 simply 17 bit value written at register.
52 prate /= (2 * rtbl[index].div); frac_calc_rate()
73 unsigned int div = 1, val; clk_frac_recalc_rate() local
83 div = val & DIV_FACTOR_MASK; clk_frac_recalc_rate()
85 if (!div) clk_frac_recalc_rate()
90 parent_rate = (parent_rate << 14) / (2 * div); clk_frac_recalc_rate()
110 val |= rtbl[i].div & DIV_FACTOR_MASK; clk_frac_set_rate()
H A Dspear1340_clock.c192 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
193 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
194 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
195 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
196 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
197 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
210 * vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div
244 {.div = 0x08000},
245 {.div = 0x06a38},
246 {.div = 0x06666},
247 {.div = 0x06000},
248 {.div = 0x054FD},
249 {.div = 0x05000},
250 {.div = 0x04D18},
251 {.div = 0x04CCE},
252 {.div = 0x04000},
253 {.div = 0x039D5},
254 {.div = 0x0351E},
255 {.div = 0x03333},
256 {.div = 0x03031},
257 {.div = 0x03000},
258 {.div = 0x02A7E},
259 {.div = 0x02800},
260 {.div = 0x0268D},
261 {.div = 0x02666},
262 {.div = 0x02000},
304 {.div = 0x18000}, /* 25 Mhz , for vc01div4 = 300 MHz*/
305 {.div = 0x1638E}, /* 27 Mhz , for vc01div4 = 300 MHz*/
306 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
307 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
308 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
309 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
310 {.div = 0x0A584}, /* 58 Mhz , for vco1div4 = 300 MHz */
311 {.div = 0x093B1}, /* 65 Mhz , for vc01div4 = 300 MHz*/
312 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
313 {.div = 0x081BA}, /* 74 Mhz , for vc01div4 = 300 MHz*/
314 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
315 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
316 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
317 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
318 {.div = 0x058E3}, /* 108 Mhz , for vc01div4 = 300 MHz*/
319 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
320 {.div = 0x040A5}, /* 148.5 Mhz , for vc01div4 = 300 MHz*/
321 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
322 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
323 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
389 {.div = 0x1A92B}, /* 22.5792 MHz for vco1div4=300 MHz*/
390 {.div = 0x186A0}, /* 24.576 MHz for vco1div4=300 MHz*/
391 {.div = 0x18000}, /* 25 MHz for vco1div4=300 MHz*/
392 {.div = 0x1624E}, /* 22.5792 MHz for vco1div4=250 MHz*/
393 {.div = 0x14585}, /* 24.576 MHz for vco1div4=250 MHz*/
394 {.div = 0x14000}, /* 25 MHz for vco1div4=250 MHz*/
395 {.div = 0x0D495}, /* 45.1584 MHz for vco1div4=300 MHz*/
396 {.div = 0x0C000}, /* 50 MHz for vco1div4=300 MHz*/
397 {.div = 0x0B127}, /* 45.1584 MHz for vco1div4=250 MHz*/
398 {.div = 0x0A000}, /* 50 MHz for vco1div4=250 MHz*/
399 {.div = 0x07530}, /* 81.92 MHz for vco1div4=300 MHz*/
400 {.div = 0x061A8}, /* 81.92 MHz for vco1div4=250 MHz*/
401 {.div = 0x06000}, /* 100 MHz for vco1div4=300 MHz*/
402 {.div = 0x05000}, /* 100 MHz for vco1div4=250 MHz*/
403 {.div = 0x03000}, /* 200 MHz for vco1div4=300 MHz*/
404 {.div = 0x02DB6}, /* 210 MHz for vco1div4=300 MHz*/
405 {.div = 0x02BA2}, /* 220 MHz for vco1div4=300 MHz*/
406 {.div = 0x029BD}, /* 230 MHz for vco1div4=300 MHz*/
407 {.div = 0x02800}, /* 200 MHz for vco1div4=250 MHz*/
408 {.div = 0x02666}, /* 250 MHz for vco1div4=300 MHz*/
409 {.div = 0x02620}, /* 210 MHz for vco1div4=250 MHz*/
410 {.div = 0x02460}, /* 220 MHz for vco1div4=250 MHz*/
411 {.div = 0x022C0}, /* 230 MHz for vco1div4=250 MHz*/
412 {.div = 0x02160}, /* 240 MHz for vco1div4=250 MHz*/
413 {.div = 0x02000}, /* 250 MHz for vco1div4=250 MHz*/
522 /* vco div n clocks */ spear1340_clk_init()
H A Dclk-gpt-synth.c60 unsigned int div = 1, val; clk_gpt_recalc_rate() local
70 div += val & GPT_MSCALE_MASK; clk_gpt_recalc_rate()
71 div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1); clk_gpt_recalc_rate()
73 if (!div) clk_gpt_recalc_rate()
76 return parent_rate / div; clk_gpt_recalc_rate()
/linux-4.1.27/drivers/clk/tegra/
H A Dclk-divider.c72 int div, mul; clk_frac_div_recalc_rate() local
76 div = reg & div_mask(divider); clk_frac_div_recalc_rate()
79 div += mul; clk_frac_div_recalc_rate()
82 rate += div - 1; clk_frac_div_recalc_rate()
83 do_div(rate, div); clk_frac_div_recalc_rate()
92 int div, mul; clk_frac_div_round_rate() local
98 div = get_div(divider, rate, output_rate); clk_frac_div_round_rate()
99 if (div < 0) clk_frac_div_round_rate()
104 return DIV_ROUND_UP(output_rate * mul, div + mul); clk_frac_div_round_rate()
111 int div; clk_frac_div_set_rate() local
115 div = get_div(divider, rate, parent_rate); clk_frac_div_set_rate()
116 if (div < 0) clk_frac_div_set_rate()
117 return div; clk_frac_div_set_rate()
124 val |= div << divider->shift; clk_frac_div_set_rate()
127 if (div) clk_frac_div_set_rate()
190 { .val = 0, .div = 2 },
191 { .val = 1, .div = 1 },
192 { .val = 0, .div = 0 },
H A Dclk-periph.c150 bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV); _tegra_clk_register_periph() local
173 periph->divider.reg = div ? (clk_base + offset) : NULL; _tegra_clk_register_periph()
183 periph->divider.hw.clk = div ? clk : NULL; _tegra_clk_register_periph()
/linux-4.1.27/lib/mpi/
H A DMakefile19 mpih-div.o \
/linux-4.1.27/drivers/clk/mvebu/
H A Dorion.c60 int *mult, int *div) mv88f5182_get_clk_ratio()
66 *div = 2; mv88f5182_get_clk_ratio()
69 *div = 3; mv88f5182_get_clk_ratio()
72 *div = 1; mv88f5182_get_clk_ratio()
117 int *mult, int *div) mv88f5281_get_clk_ratio()
123 *div = 2; mv88f5281_get_clk_ratio()
126 *div = 3; mv88f5281_get_clk_ratio()
129 *div = 1; mv88f5281_get_clk_ratio()
183 int *mult, int *div) mv88f6183_get_clk_ratio()
189 *div = 2; mv88f6183_get_clk_ratio()
192 *div = 1; mv88f6183_get_clk_ratio()
59 mv88f5182_get_clk_ratio(void __iomem *sar, int id, int *mult, int *div) mv88f5182_get_clk_ratio() argument
116 mv88f5281_get_clk_ratio(void __iomem *sar, int id, int *mult, int *div) mv88f5281_get_clk_ratio() argument
182 mv88f6183_get_clk_ratio(void __iomem *sar, int id, int *mult, int *div) mv88f6183_get_clk_ratio() argument
H A Dclk-cpu.c53 u32 reg, div; clk_cpu_recalc_rate() local
56 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; clk_cpu_recalc_rate()
57 return parent_rate / div; clk_cpu_recalc_rate()
64 u32 div; clk_cpu_round_rate() local
66 div = *parent_rate / rate; clk_cpu_round_rate()
67 if (div == 0) clk_cpu_round_rate()
68 div = 1; clk_cpu_round_rate()
69 else if (div > 3) clk_cpu_round_rate()
70 div = 3; clk_cpu_round_rate()
72 return *parent_rate / div; clk_cpu_round_rate()
80 u32 reg, div; clk_cpu_off_set_rate() local
83 div = parent_rate / rate; clk_cpu_off_set_rate()
86 | (div << (cpuclk->cpu * 8)); clk_cpu_off_set_rate()
H A Dclk-corediv.c128 u32 reg, div; clk_corediv_recalc_rate() local
131 div = (reg >> desc->offset) & desc->mask; clk_corediv_recalc_rate()
132 return parent_rate / div; clk_corediv_recalc_rate()
139 u32 div; clk_corediv_round_rate() local
141 div = *parent_rate / rate; clk_corediv_round_rate()
142 if (div < 4) clk_corediv_round_rate()
143 div = 4; clk_corediv_round_rate()
144 else if (div > 6) clk_corediv_round_rate()
145 div = 8; clk_corediv_round_rate()
147 return *parent_rate / div; clk_corediv_round_rate()
157 u32 reg, div; clk_corediv_set_rate() local
159 div = parent_rate / rate; clk_corediv_set_rate()
166 reg |= (div & desc->mask) << desc->offset; clk_corediv_set_rate()
H A Darmada-370.c116 void __iomem *sar, int id, int *mult, int *div) a370_get_clk_ratio()
124 *div = a370_nbclk_ratios[opt][1]; a370_get_clk_ratio()
128 *div = a370_hclk_ratios[opt][1]; a370_get_clk_ratio()
132 *div = a370_dramclk_ratios[opt][1]; a370_get_clk_ratio()
115 a370_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) a370_get_clk_ratio() argument
H A Darmada-39x.c94 void __iomem *sar, int id, int *mult, int *div) armada_39x_get_clk_ratio()
99 *div = 2; armada_39x_get_clk_ratio()
103 *div = 4; armada_39x_get_clk_ratio()
107 *div = 2; armada_39x_get_clk_ratio()
93 armada_39x_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) armada_39x_get_clk_ratio() argument
H A Darmada-38x.c100 void __iomem *sar, int id, int *mult, int *div) armada_38x_get_clk_ratio()
108 *div = armada_38x_cpu_l2_ratios[opt][1]; armada_38x_get_clk_ratio()
112 *div = armada_38x_cpu_ddr_ratios[opt][1]; armada_38x_get_clk_ratio()
99 armada_38x_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) armada_38x_get_clk_ratio() argument
H A Darmada-xp.c126 void __iomem *sar, int id, int *mult, int *div) axp_get_clk_ratio()
140 *div = axp_nbclk_ratios[opt][1]; axp_get_clk_ratio()
144 *div = axp_hclk_ratios[opt][1]; axp_get_clk_ratio()
148 *div = axp_dramclk_ratios[opt][1]; axp_get_clk_ratio()
125 axp_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) axp_get_clk_ratio() argument
H A Darmada-375.c117 void __iomem *sar, int id, int *mult, int *div) armada_375_get_clk_ratio()
125 *div = armada_375_cpu_l2_ratios[opt][1]; armada_375_get_clk_ratio()
129 *div = armada_375_cpu_ddr_ratios[opt][1]; armada_375_get_clk_ratio()
116 armada_375_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) armada_375_get_clk_ratio() argument
H A Ddove.c127 void __iomem *sar, int id, int *mult, int *div) dove_get_clk_ratio()
135 *div = dove_cpu_l2_ratios[opt][1]; dove_get_clk_ratio()
143 *div = dove_cpu_ddr_ratios[opt][1]; dove_get_clk_ratio()
126 dove_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) dove_get_clk_ratio() argument
H A Dkirkwood.c129 void __iomem *sar, int id, int *mult, int *div) kirkwood_get_clk_ratio()
136 *div = kirkwood_cpu_l2_ratios[opt][1]; kirkwood_get_clk_ratio()
144 *div = kirkwood_cpu_ddr_ratios[opt][1]; kirkwood_get_clk_ratio()
169 void __iomem *sar, int id, int *mult, int *div) mv88f6180_get_clk_ratio()
176 *div = 2; mv88f6180_get_clk_ratio()
184 *div = mv88f6180_cpu_ddr_ratios[opt][1]; mv88f6180_get_clk_ratio()
128 kirkwood_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) kirkwood_get_clk_ratio() argument
168 mv88f6180_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) mv88f6180_get_clk_ratio() argument
/linux-4.1.27/drivers/clk/pistachio/
H A Dclk.c94 struct pistachio_div *div, pistachio_clk_register_div()
101 clk = clk_register_divider(NULL, div[i].name, div[i].parent, pistachio_clk_register_div()
102 0, p->base + div[i].reg, 0, pistachio_clk_register_div()
103 div[i].width, div[i].div_flags, pistachio_clk_register_div()
105 p->clk_data.clks[div[i].id] = clk; pistachio_clk_register_div()
118 0, 1, ff[i].div); pistachio_clk_register_fixed_factor()
93 pistachio_clk_register_div(struct pistachio_clk_provider *p, struct pistachio_div *div, unsigned int num) pistachio_clk_register_div() argument
H A Dclk.h84 unsigned int div; member in struct:pistachio_fixed_factor
92 .div = _div, \
161 struct pistachio_div *div,
/linux-4.1.27/drivers/clk/sunxi/
H A Dclk-sun8i-mbus.c32 u8 div; sun8i_a23_get_mbus_factors() local
41 div = DIV_ROUND_UP(parent_rate, *freq); sun8i_a23_get_mbus_factors()
43 if (div > 8) sun8i_a23_get_mbus_factors()
44 div = 8; sun8i_a23_get_mbus_factors()
46 *freq = parent_rate / div; sun8i_a23_get_mbus_factors()
52 *m = div - 1; sun8i_a23_get_mbus_factors()
H A Dclk-sunxi.c45 #define SUN6I_AHB1_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_DIV_MASK) | \
46 (div << SUN6I_AHB1_DIV_SHIFT))
51 #define SUN6I_AHB1_PLL6_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_PLL6_DIV_MASK) | \
52 (div << SUN6I_AHB1_PLL6_DIV_SHIFT))
84 u8 div, calcp, calcm = 1; sun6i_ahb1_clk_round() local
93 div = DIV_ROUND_UP(parent_rate, rate); sun6i_ahb1_clk_round()
97 if (div < 4) sun6i_ahb1_clk_round()
99 else if (div / 2 < 4) sun6i_ahb1_clk_round()
101 else if (div / 4 < 4) sun6i_ahb1_clk_round()
106 calcm = DIV_ROUND_UP(div, 1 << calcp); sun6i_ahb1_clk_round()
108 calcp = __roundup_pow_of_two(div); sun6i_ahb1_clk_round()
164 u8 div, pre_div, parent; sun6i_ahb1_clk_set_rate() local
173 sun6i_ahb1_clk_round(rate, &div, &pre_div, parent, parent_rate); sun6i_ahb1_clk_set_rate()
175 reg = SUN6I_AHB1_DIV_SET(reg, div); sun6i_ahb1_clk_set_rate()
251 u8 div; sun4i_get_pll1_factors() local
254 div = *freq / 6000000; sun4i_get_pll1_factors()
255 *freq = 6000000 * div; sun4i_get_pll1_factors()
271 if (div < 10) sun4i_get_pll1_factors()
275 else if (div < 20 || (div < 32 && (div & 1))) sun4i_get_pll1_factors()
280 else if (div < 40 || (div < 64 && (div & 2))) sun4i_get_pll1_factors()
288 div <<= *p; sun4i_get_pll1_factors()
289 div /= (*k + 1); sun4i_get_pll1_factors()
290 *n = div / 4; sun4i_get_pll1_factors()
387 u8 div; sun8i_a23_get_pll1_factors() local
390 div = *freq / 6000000; sun8i_a23_get_pll1_factors()
391 *freq = 6000000 * div; sun8i_a23_get_pll1_factors()
407 if (div < 20 || (div < 32 && (div & 1))) sun8i_a23_get_pll1_factors()
412 else if (div < 40 || (div < 64 && (div & 2))) sun8i_a23_get_pll1_factors()
420 div <<= *p; sun8i_a23_get_pll1_factors()
421 div /= (*k + 1); sun8i_a23_get_pll1_factors()
422 *n = div / 4 - 1; sun8i_a23_get_pll1_factors()
435 u8 div; sun4i_get_pll5_factors() local
438 div = *freq / parent_rate; sun4i_get_pll5_factors()
439 *freq = parent_rate * div; sun4i_get_pll5_factors()
445 if (div < 31) sun4i_get_pll5_factors()
447 else if (div / 2 < 31) sun4i_get_pll5_factors()
449 else if (div / 3 < 31) sun4i_get_pll5_factors()
454 *n = DIV_ROUND_UP(div, (*k+1)); sun4i_get_pll5_factors()
467 u8 div; sun6i_a31_get_pll6_factors() local
470 div = *freq / parent_rate; sun6i_a31_get_pll6_factors()
471 *freq = parent_rate * div; sun6i_a31_get_pll6_factors()
477 *k = div / 32; sun6i_a31_get_pll6_factors()
481 *n = DIV_ROUND_UP(div, (*k+1)) - 1; sun6i_a31_get_pll6_factors()
493 u32 div; sun5i_a13_get_ahb_factors() local
508 div = order_base_2(DIV_ROUND_UP(parent_rate, *freq)); sun5i_a13_get_ahb_factors()
511 if (div > 3) sun5i_a13_get_ahb_factors()
512 div = 3; sun5i_a13_get_ahb_factors()
514 *freq = parent_rate >> div; sun5i_a13_get_ahb_factors()
520 *p = div; sun5i_a13_get_ahb_factors()
576 u8 div, calcm, calcp; sun7i_a20_get_out_factors() local
583 div = DIV_ROUND_UP(parent_rate, *freq); sun7i_a20_get_out_factors()
585 if (div < 32) sun7i_a20_get_out_factors()
587 else if (div / 2 < 32) sun7i_a20_get_out_factors()
589 else if (div / 4 < 32) sun7i_a20_get_out_factors()
594 calcm = DIV_ROUND_UP(div, 1 << calcp); sun7i_a20_get_out_factors()
828 { .val = 0, .div = 1 },
829 { .val = 1, .div = 2 },
830 { .val = 2, .div = 3 },
831 { .val = 3, .div = 4 },
832 { .val = 4, .div = 4 },
833 { .val = 5, .div = 4 },
834 { .val = 6, .div = 4 },
835 { .val = 7, .div = 4 },
851 { .val = 0, .div = 2 },
852 { .val = 1, .div = 2 },
853 { .val = 2, .div = 4 },
854 { .val = 3, .div = 8 },
1068 } div[SUNXI_DIVS_MAX_QTY]; member in struct:divs_data
1072 { .val = 0, .div = 6, },
1073 { .val = 1, .div = 12, },
1074 { .val = 2, .div = 18, },
1075 { .val = 3, .div = 24, },
1082 .div = {
1092 .div = {
1103 .div = {
1166 if (data->div[i].self) { sunxi_divs_clk_setup()
1176 if (data->div[i].gate) { sunxi_divs_clk_setup()
1182 gate->bit_idx = data->div[i].gate; sunxi_divs_clk_setup()
1189 if (data->div[i].fixed) { sunxi_divs_clk_setup()
1195 fix_factor->div = data->div[i].fixed; sunxi_divs_clk_setup()
1204 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0; sunxi_divs_clk_setup()
1207 divider->shift = data->div[i].shift; sunxi_divs_clk_setup()
1211 divider->table = data->div[i].table; sunxi_divs_clk_setup()
H A Dclk-sun6i-ar100.c42 int div = (val >> SUN6I_AR100_DIV_SHIFT) & SUN6I_AR100_DIV_MASK; ar100_recalc_rate() local
44 return (parent_rate >> shift) / (div + 1); ar100_recalc_rate()
63 unsigned long div; ar100_determine_rate() local
68 div = DIV_ROUND_UP(parent_rate, rate); ar100_determine_rate()
78 shift = ffs(div) - 1; ar100_determine_rate()
82 div >>= shift; ar100_determine_rate()
89 while (div > SUN6I_AR100_DIV_MAX) { ar100_determine_rate()
91 div >>= 1; ar100_determine_rate()
103 tmp_rate = (parent_rate >> shift) / div; ar100_determine_rate()
139 unsigned long div = parent_rate / rate; ar100_set_rate() local
147 shift = ffs(div) - 1; ar100_set_rate()
151 div >>= shift; ar100_set_rate()
153 if (div > SUN6I_AR100_DIV_MAX) ar100_set_rate()
159 (div << SUN6I_AR100_DIV_SHIFT); ar100_set_rate()
H A Dclk-sun6i-apb0.c24 { .val = 0, .div = 2, },
25 { .val = 1, .div = 2, },
26 { .val = 2, .div = 4, },
27 { .val = 3, .div = 8, },
H A Dclk-sun9i-core.c117 u32 div; sun9i_a80_get_gt_factors() local
122 div = DIV_ROUND_UP(parent_rate, *freq); sun9i_a80_get_gt_factors()
125 if (div > 4) sun9i_a80_get_gt_factors()
126 div = 4; sun9i_a80_get_gt_factors()
128 *freq = parent_rate / div; sun9i_a80_get_gt_factors()
134 *m = div; sun9i_a80_get_gt_factors()
268 u32 div; sun9i_a80_get_apb1_factors() local
274 div = DIV_ROUND_UP(parent_rate, *freq); sun9i_a80_get_apb1_factors()
277 if (div > 256) sun9i_a80_get_apb1_factors()
278 div = 256; sun9i_a80_get_apb1_factors()
280 calcp = order_base_2(div); sun9i_a80_get_apb1_factors()
H A Dclk-mod0.c33 u8 div, calcm, calcp; sun4i_a10_get_mod0_factors() local
40 div = DIV_ROUND_UP(parent_rate, *freq); sun4i_a10_get_mod0_factors()
42 if (div < 16) sun4i_a10_get_mod0_factors()
44 else if (div / 2 < 16) sun4i_a10_get_mod0_factors()
46 else if (div / 4 < 16) sun4i_a10_get_mod0_factors()
51 calcm = DIV_ROUND_UP(div, 1 << calcp); sun4i_a10_get_mod0_factors()
/linux-4.1.27/drivers/clk/rockchip/
H A Dclk.c52 struct clk_divider *div = NULL; rockchip_clk_register_branch() local
83 div = kzalloc(sizeof(*div), GFP_KERNEL); rockchip_clk_register_branch()
84 if (!div) rockchip_clk_register_branch()
87 div->flags = div_flags; rockchip_clk_register_branch()
88 div->reg = base + muxdiv_offset; rockchip_clk_register_branch()
89 div->shift = div_shift; rockchip_clk_register_branch()
90 div->width = div_width; rockchip_clk_register_branch()
91 div->lock = lock; rockchip_clk_register_branch()
92 div->table = div_table; rockchip_clk_register_branch()
98 div ? &div->hw : NULL, div_ops, rockchip_clk_register_branch()
113 struct clk_fractional_divider *div = NULL; rockchip_clk_register_frac_branch() local
131 div = kzalloc(sizeof(*div), GFP_KERNEL); rockchip_clk_register_frac_branch()
132 if (!div) rockchip_clk_register_frac_branch()
135 div->flags = div_flags; rockchip_clk_register_frac_branch()
136 div->reg = base + muxdiv_offset; rockchip_clk_register_frac_branch()
137 div->mshift = 16; rockchip_clk_register_frac_branch()
138 div->mmask = 0xffff0000; rockchip_clk_register_frac_branch()
139 div->nshift = 0; rockchip_clk_register_frac_branch()
140 div->nmask = 0xffff; rockchip_clk_register_frac_branch()
141 div->lock = lock; rockchip_clk_register_frac_branch()
146 &div->hw, div_ops, rockchip_clk_register_frac_branch()
H A Dclk-rk3188.c241 { .val = 0, .div = 2 },
242 { .val = 1, .div = 4 },
243 { .val = 2, .div = 8 },
244 { .val = 3, .div = 16 },
512 { .val = 0, .div = 1 },
513 { .val = 1, .div = 2 },
514 { .val = 2, .div = 3 },
515 { .val = 3, .div = 4 },
516 { .val = 4, .div = 8 },
622 { .val = 0, .div = 1 },
623 { .val = 1, .div = 2 },
624 { .val = 2, .div = 3 },
625 { .val = 3, .div = 4 },
626 { .val = 4, .div = 8 },
/linux-4.1.27/arch/arm/mach-imx/
H A Dclk-pllv3.c102 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; clk_pllv3_recalc_rate() local
104 return (div == 1) ? parent_rate * 22 : parent_rate * 20; clk_pllv3_recalc_rate()
120 u32 val, div; clk_pllv3_set_rate() local
123 div = 1; clk_pllv3_set_rate()
125 div = 0; clk_pllv3_set_rate()
131 val |= (div << pll->div_shift); clk_pllv3_set_rate()
149 u32 div = readl_relaxed(pll->base) & pll->div_mask; clk_pllv3_sys_recalc_rate() local
151 return parent_rate * div / 2; clk_pllv3_sys_recalc_rate()
160 u32 div; clk_pllv3_sys_round_rate() local
166 div = rate * 2 / parent_rate; clk_pllv3_sys_round_rate()
168 return parent_rate * div / 2; clk_pllv3_sys_round_rate()
177 u32 val, div; clk_pllv3_sys_set_rate() local
182 div = rate * 2 / parent_rate; clk_pllv3_sys_set_rate()
185 val |= div; clk_pllv3_sys_set_rate()
205 u32 div = readl_relaxed(pll->base) & pll->div_mask; clk_pllv3_av_recalc_rate() local
207 return (parent_rate * div) + ((parent_rate / mfd) * mfn); clk_pllv3_av_recalc_rate()
216 u32 div; clk_pllv3_av_round_rate() local
225 div = rate / parent_rate; clk_pllv3_av_round_rate()
226 temp64 = (u64) (rate - div * parent_rate); clk_pllv3_av_round_rate()
231 return parent_rate * div + parent_rate / mfd * mfn; clk_pllv3_av_round_rate()
240 u32 val, div; clk_pllv3_av_set_rate() local
247 div = rate / parent_rate; clk_pllv3_av_set_rate()
248 temp64 = (u64) (rate - div * parent_rate); clk_pllv3_av_set_rate()
255 val |= div; clk_pllv3_av_set_rate()
H A Dclk-fixup-div.c63 struct clk_divider *div = to_clk_div(hw); clk_fixup_div_set_rate() local
73 if (value > div_mask(div)) clk_fixup_div_set_rate()
74 value = div_mask(div); clk_fixup_div_set_rate()
76 spin_lock_irqsave(div->lock, flags); clk_fixup_div_set_rate()
78 val = readl(div->reg); clk_fixup_div_set_rate()
79 val &= ~(div_mask(div) << div->shift); clk_fixup_div_set_rate()
80 val |= value << div->shift; clk_fixup_div_set_rate()
82 writel(val, div->reg); clk_fixup_div_set_rate()
84 spin_unlock_irqrestore(div->lock, flags); clk_fixup_div_set_rate()
H A Dclk-busy.c33 struct clk_divider div; member in struct:clk_busy_divider
41 struct clk_divider *div = container_of(hw, struct clk_divider, hw); to_clk_busy_divider() local
43 return container_of(div, struct clk_busy_divider, div); to_clk_busy_divider()
51 return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate); clk_busy_divider_recalc_rate()
59 return busy->div_ops->round_rate(&busy->div.hw, rate, prate); clk_busy_divider_round_rate()
68 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); clk_busy_divider_set_rate()
96 busy->div.reg = reg; imx_clk_busy_divider()
97 busy->div.shift = shift; imx_clk_busy_divider()
98 busy->div.width = width; imx_clk_busy_divider()
99 busy->div.lock = &imx_ccm_lock; imx_clk_busy_divider()
108 busy->div.hw.init = &init; imx_clk_busy_divider()
110 clk = clk_register(NULL, &busy->div.hw); imx_clk_busy_divider()
H A Dclk-cpu.c18 struct clk *div; member in struct:clk_cpu
34 return clk_get_rate(cpu->div); clk_cpu_recalc_rate()
66 clk_set_rate(cpu->div, rate); clk_cpu_set_rate()
78 struct clk *div, struct clk *mux, struct clk *pll, imx_clk_cpu()
89 cpu->div = div; imx_clk_cpu()
77 imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step) imx_clk_cpu() argument
H A Dclk-imx6sl.c76 { .val = 0, .div = 20, },
77 { .val = 1, .div = 10, },
78 { .val = 2, .div = 5, },
79 { .val = 3, .div = 4, },
84 { .val = 2, .div = 1, },
85 { .val = 1, .div = 2, },
86 { .val = 0, .div = 4, },
91 { .val = 0, .div = 1, },
92 { .val = 1, .div = 2, },
93 { .val = 2, .div = 1, },
94 { .val = 3, .div = 4, },
264 /* dev name parent_name flags reg shift width div: flags, div_table lock */ imx6sl_clocks_init()
280 /* name parent_name mult div */ imx6sl_clocks_init()
H A Dclk.h129 const char *parent, unsigned int mult, unsigned int div) imx_clk_fixed_factor()
132 CLK_SET_RATE_PARENT, mult, div); imx_clk_fixed_factor()
136 struct clk *div, struct clk *mux, struct clk *pll,
128 imx_clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div) imx_clk_fixed_factor() argument
/linux-4.1.27/arch/c6x/platforms/
H A Dplldata.c178 sysclks[2].div = 3; c6455_setup_clocks()
180 sysclks[3].div = 6; c6455_setup_clocks()
181 sysclks[4].div = PLLDIV4; c6455_setup_clocks()
182 sysclks[5].div = PLLDIV5; c6455_setup_clocks()
216 sysclks[1].div = 1; c6457_setup_clocks()
218 sysclks[2].div = 3; c6457_setup_clocks()
220 sysclks[3].div = 6; c6457_setup_clocks()
221 sysclks[4].div = PLLDIV4; c6457_setup_clocks()
222 sysclks[5].div = PLLDIV5; c6457_setup_clocks()
268 sysclks[i].div = 1; c6472_setup_clocks()
272 sysclks[7].div = 3; c6472_setup_clocks()
274 sysclks[8].div = 6; c6472_setup_clocks()
276 sysclks[9].div = 2; c6472_setup_clocks()
277 sysclks[10].div = PLLDIV10; c6472_setup_clocks()
315 sysclks[7].div = 1; c6474_setup_clocks()
317 sysclks[9].div = 3; c6474_setup_clocks()
319 sysclks[10].div = 6; c6474_setup_clocks()
321 sysclks[11].div = PLLDIV11; c6474_setup_clocks()
324 sysclks[12].div = 2; c6474_setup_clocks()
326 sysclks[13].div = PLLDIV13; c6474_setup_clocks()
364 sysclks[1].div = 1; c6678_setup_clocks()
366 sysclks[2].div = PLLDIV2; c6678_setup_clocks()
369 sysclks[3].div = 2; c6678_setup_clocks()
372 sysclks[4].div = 3; c6678_setup_clocks()
374 sysclks[5].div = PLLDIV5; c6678_setup_clocks()
377 sysclks[6].div = 64; c6678_setup_clocks()
380 sysclks[7].div = 6; c6678_setup_clocks()
382 sysclks[8].div = PLLDIV8; c6678_setup_clocks()
385 sysclks[9].div = 12; c6678_setup_clocks()
388 sysclks[10].div = 3; c6678_setup_clocks()
391 sysclks[11].div = 6; c6678_setup_clocks()
/linux-4.1.27/drivers/media/i2c/
H A Daptina-pll.c38 unsigned int div; aptina_pll_calculate() local
55 div = gcd(pll->pix_clock, pll->ext_clock); aptina_pll_calculate()
56 pll->m = pll->pix_clock / div; aptina_pll_calculate()
57 div = pll->ext_clock / div; aptina_pll_calculate()
72 mf_min = max(mf_min, limits->n_min * limits->p1_min / div); aptina_pll_calculate()
76 mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div)); aptina_pll_calculate()
91 * 3. div * mf is a multiple of p1, in order to compute aptina_pll_calculate()
92 * n = div * mf / p1 aptina_pll_calculate()
108 * mf_inc = p1 / gcd(div, p1) (6) aptina_pll_calculate()
117 * ext_clock / (div * mf / p1) * m * mf >= out_clock_min aptina_pll_calculate()
118 * ext_clock / (div * mf / p1) * m * mf <= out_clock_max aptina_pll_calculate()
122 * p1 >= out_clock_min * div / (ext_clock * m) (7) aptina_pll_calculate()
123 * p1 <= out_clock_max * div / (ext_clock * m) aptina_pll_calculate()
127 * mf >= ext_clock * p1 / (int_clock_max * div) (8) aptina_pll_calculate()
128 * mf <= ext_clock * p1 / (int_clock_min * div) aptina_pll_calculate()
141 p1_min = max(limits->p1_min, DIV_ROUND_UP(limits->out_clock_min * div, aptina_pll_calculate()
143 p1_max = min(limits->p1_max, limits->out_clock_max * div / aptina_pll_calculate()
147 unsigned int mf_inc = p1 / gcd(div, p1); aptina_pll_calculate()
152 limits->int_clock_max * div)), mf_inc); aptina_pll_calculate()
154 (limits->int_clock_min * div)); aptina_pll_calculate()
159 pll->n = div * mf_low / p1; aptina_pll_calculate()
H A Dsmiapp-pll.c153 * @mul is the PLL multiplier and @div is the common divisor
163 uint32_t div, uint32_t lane_op_clock_ratio) __smiapp_pll_calculate()
201 / div); __smiapp_pll_calculate()
228 more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div; __smiapp_pll_calculate()
244 op_pll->sys_clk_div = div * i / pll->pre_pll_clk_div; __smiapp_pll_calculate()
349 * into a value which is not smaller than div, the desired __smiapp_pll_calculate()
403 uint32_t mul, div; smiapp_pll_calculate() local
458 div = pll->ext_clk_freq_hz / i; smiapp_pll_calculate()
459 dev_dbg(dev, "mul %u / div %u\n", mul, div); smiapp_pll_calculate()
473 op_pll, mul, div, smiapp_pll_calculate()
159 __smiapp_pll_calculate( struct device *dev, const struct smiapp_pll_limits *limits, const struct smiapp_pll_branch_limits *op_limits, struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul, uint32_t div, uint32_t lane_op_clock_ratio) __smiapp_pll_calculate() argument
/linux-4.1.27/sound/aoa/soundbus/i2sbus/
H A Dinterface.h90 # define I2S_SF_MCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_MCLKDIV_SHIFT)&I2S_SF_MCLKDIV_MASK) i2s_sf_mclkdiv()
91 static inline int i2s_sf_mclkdiv(int div, int *out) i2s_sf_mclkdiv() argument
95 switch(div) { i2s_sf_mclkdiv()
101 if (div%2) return -1; i2s_sf_mclkdiv()
102 d = div/2-1; i2s_sf_mclkdiv()
105 *out |= I2S_SF_MCLKDIV_OTHER(div); i2s_sf_mclkdiv()
117 # define I2S_SF_SCLKDIV_OTHER(div) (((div/2-1)<<I2S_SF_SCLKDIV_SHIFT)&I2S_SF_SCLKDIV_MASK) i2s_sf_sclkdiv()
118 static inline int i2s_sf_sclkdiv(int div, int *out) i2s_sf_sclkdiv() argument
122 switch(div) { i2s_sf_sclkdiv()
126 if (div%2) return -1; i2s_sf_sclkdiv()
127 d = div/2-1; i2s_sf_sclkdiv()
129 *out |= I2S_SF_SCLKDIV_OTHER(div); i2s_sf_sclkdiv()
/linux-4.1.27/drivers/clk/at91/
H A Dclk-smd.c49 unsigned long div; at91sam9x5_clk_smd_round_rate() local
56 div = *parent_rate / rate; at91sam9x5_clk_smd_round_rate()
57 if (div > SMD_MAX_DIV) at91sam9x5_clk_smd_round_rate()
60 bestrate = *parent_rate / div; at91sam9x5_clk_smd_round_rate()
61 tmp = *parent_rate / (div + 1); at91sam9x5_clk_smd_round_rate()
97 unsigned long div = parent_rate / rate; at91sam9x5_clk_smd_set_rate() local
99 if (parent_rate % rate || div < 1 || div > (SMD_MAX_DIV + 1)) at91sam9x5_clk_smd_set_rate()
102 tmp |= (div - 1) << SMD_DIV_SHIFT; at91sam9x5_clk_smd_set_rate()
H A Dclk-h32mx.c55 unsigned long div; clk_sama5d4_h32mx_round_rate() local
59 div = *parent_rate / 2; clk_sama5d4_h32mx_round_rate()
60 if (rate < div) clk_sama5d4_h32mx_round_rate()
61 return div; clk_sama5d4_h32mx_round_rate()
63 if (rate - div < *parent_rate - rate) clk_sama5d4_h32mx_round_rate()
64 return div; clk_sama5d4_h32mx_round_rate()
H A Dclk-plldiv.c42 unsigned long div; clk_plldiv_round_rate() local
46 div = *parent_rate / 2; clk_plldiv_round_rate()
47 if (rate < div) clk_plldiv_round_rate()
48 return div; clk_plldiv_round_rate()
50 if (rate - div < *parent_rate - rate) clk_plldiv_round_rate()
51 return div; clk_plldiv_round_rate()
H A Dclk-usb.c74 int div; at91sam9x5_clk_usb_determine_rate() local
80 for (div = 1; div < SAM9X5_USB_MAX_DIV + 2; div++) { at91sam9x5_clk_usb_determine_rate()
83 tmp_parent_rate = rate * div; at91sam9x5_clk_usb_determine_rate()
86 tmp_rate = DIV_ROUND_CLOSEST(tmp_parent_rate, div); at91sam9x5_clk_usb_determine_rate()
139 unsigned long div; at91sam9x5_clk_usb_set_rate() local
144 div = DIV_ROUND_CLOSEST(parent_rate, rate); at91sam9x5_clk_usb_set_rate()
145 if (div > SAM9X5_USB_MAX_DIV + 1 || !div) at91sam9x5_clk_usb_set_rate()
149 tmp |= (div - 1) << SAM9X5_USB_DIV_SHIFT; at91sam9x5_clk_usb_set_rate()
317 unsigned long div; at91rm9200_clk_usb_set_rate() local
322 div = DIV_ROUND_CLOSEST(parent_rate, rate); at91rm9200_clk_usb_set_rate()
325 if (usb->divisors[i] == div) { at91rm9200_clk_usb_set_rate()
H A Dclk-pll.c65 u8 div; member in struct:clk_pll
94 u8 div; clk_pll_prepare() local
98 div = PLL_DIV(pllr); clk_pll_prepare()
102 (div == pll->div && mul == pll->mul)) clk_pll_prepare()
116 (pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) | clk_pll_prepare()
155 if (!pll->div || !pll->mul) clk_pll_recalc_rate()
158 return (parent_rate / pll->div) * (pll->mul + 1); clk_pll_recalc_rate()
163 u32 *div, u32 *mul, clk_pll_get_best_div_mul()
261 if (div) clk_pll_get_best_div_mul()
262 *div = bestdiv; clk_pll_get_best_div_mul()
285 u32 div; clk_pll_set_rate() local
290 &div, &mul, &index); clk_pll_set_rate()
295 pll->div = div; clk_pll_set_rate()
343 pll->div = PLL_DIV(tmp); at91_clk_register_pll()
161 clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate, unsigned long parent_rate, u32 *div, u32 *mul, u32 *index) clk_pll_get_best_div_mul() argument
H A Dclk-peripheral.c47 u32 div; member in struct:clk_sam9x5_peripheral
157 periph->div = shift; clk_sam9x5_peripheral_autodiv()
170 AT91_PMC_PCR_DIV(periph->div) | clk_sam9x5_peripheral_enable()
221 periph->div = PERIPHERAL_RSHIFT(tmp); clk_sam9x5_peripheral_recalc_rate()
227 return parent_rate >> periph->div; clk_sam9x5_peripheral_recalc_rate()
295 periph->div = shift; clk_sam9x5_peripheral_set_rate()
336 periph->div = 0; at91_clk_register_sam9x5_peripheral()
H A Dclk-master.c88 u8 div; clk_master_recalc_rate() local
102 div = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; clk_master_recalc_rate()
109 rate /= characteristics->divisors[div]; clk_master_recalc_rate()
H A Dclk-programmable.c144 unsigned long div = parent_rate / rate; clk_programmable_set_rate() local
149 if (!div) clk_programmable_set_rate()
152 shift = fls(div) - 1; clk_programmable_set_rate()
154 if (div != (1<<shift)) clk_programmable_set_rate()
/linux-4.1.27/arch/mn10300/include/asm/
H A Ddiv64.h79 unsigned __muldiv64u(unsigned val, unsigned mult, unsigned div) __muldiv64u() argument
84 "divu %3,%0 \n" /* val = MDR:val/div; __muldiv64u()
85 * MDR = MDR:val%div */ __muldiv64u()
87 : "0"(val), "ir"(mult), "r"(div) __muldiv64u()
100 signed __muldiv64s(signed val, signed mult, signed div) __muldiv64s() argument
105 "div %3,%0 \n" /* val = MDR:val/div; __muldiv64s()
106 * MDR = MDR:val%div */ __muldiv64s()
108 : "0"(val), "ir"(mult), "r"(div) __muldiv64s()
/linux-4.1.27/drivers/gpu/drm/armada/
H A Darmada_510.c64 uint32_t rate, ref, div; armada510_crtc_compute_clock() local
68 div = DIV_ROUND_UP(ref, rate); armada510_crtc_compute_clock()
69 if (div < 1) armada510_crtc_compute_clock()
70 div = 1; armada510_crtc_compute_clock()
73 *sclk = div | SCLK_510_EXTCLK1; armada510_crtc_compute_clock()
/linux-4.1.27/drivers/clk/mmp/
H A Dclk-mix.c2 * mmp mix(div and mux) clock operation source file
20 * The mix clock is a clock combined mux and div type clock.
21 * Because the div field and mux field need to be set at same
38 for (clkt = mix->div_table; clkt->div; clkt++) _get_maxdiv()
39 if (clkt->div > maxdiv) _get_maxdiv()
40 maxdiv = clkt->div; _get_maxdiv()
55 for (clkt = mix->div_table; clkt->div; clkt++) _get_div()
57 return clkt->div; _get_div()
58 if (clkt->div == 0) _get_div()
83 static unsigned int _get_div_val(struct mmp_clk_mix *mix, unsigned int div) _get_div_val() argument
88 return div; _get_div_val()
90 return __ffs(div); _get_div_val()
92 for (clkt = mix->div_table; clkt->div; clkt++) _get_div_val()
93 if (clkt->div == div) _get_div_val()
95 if (clkt->div == 0) _get_div_val()
99 return div - 1; _get_div_val()
216 unsigned int div; mmp_clk_mix_determine_rate() local
252 div = _get_div(mix, j); mmp_clk_mix_determine_rate()
253 mix_rate = parent_rate / div; mmp_clk_mix_determine_rate()
280 unsigned int div; mmp_clk_mix_set_rate_and_parent() local
283 div = parent_rate / rate; mmp_clk_mix_set_rate_and_parent()
284 div_val = _get_div_val(mix, div); mmp_clk_mix_set_rate_and_parent()
327 unsigned int div; mmp_clk_mix_recalc_rate() local
344 div = _get_div(mix, MMP_CLK_BITS_GET_VAL(mux_div, width, shift)); mmp_clk_mix_recalc_rate()
346 return parent_rate / div; mmp_clk_mix_recalc_rate()
/linux-4.1.27/arch/mips/ath79/
H A Dclock.c59 u32 div; ar71xx_clocks_init() local
65 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; ar71xx_clocks_init()
66 freq = div * ref_rate; ar71xx_clocks_init()
68 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; ar71xx_clocks_init()
69 cpu_rate = freq / div; ar71xx_clocks_init()
71 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; ar71xx_clocks_init()
72 ddr_rate = freq / div; ar71xx_clocks_init()
74 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; ar71xx_clocks_init()
75 ahb_rate = cpu_rate / div; ar71xx_clocks_init()
94 u32 div; ar724x_clocks_init() local
99 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); ar724x_clocks_init()
100 freq = div * ref_rate; ar724x_clocks_init()
102 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); ar724x_clocks_init()
103 freq *= div; ar724x_clocks_init()
107 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; ar724x_clocks_init()
108 ddr_rate = freq / div; ar724x_clocks_init()
110 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; ar724x_clocks_init()
111 ahb_rate = cpu_rate / div; ar724x_clocks_init()
130 u32 div; ar913x_clocks_init() local
135 div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK); ar913x_clocks_init()
136 freq = div * ref_rate; ar913x_clocks_init()
140 div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1; ar913x_clocks_init()
141 ddr_rate = freq / div; ar913x_clocks_init()
143 div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2; ar913x_clocks_init()
144 ahb_rate = cpu_rate / div; ar913x_clocks_init()
/linux-4.1.27/arch/arm/mach-rpc/include/mach/
H A Dacornfb.h85 u_int div; acornfb_vidc20_find_rates() local
88 div = var->pixclock / 9090; /*9921*/ acornfb_vidc20_find_rates()
91 if (div == 0) acornfb_vidc20_find_rates()
92 div = 1; acornfb_vidc20_find_rates()
93 if (div > 8) acornfb_vidc20_find_rates()
94 div = 8; acornfb_vidc20_find_rates()
97 switch (div) { acornfb_vidc20_find_rates()
136 vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div); acornfb_vidc20_find_rates()
/linux-4.1.27/include/linux/
H A Djz4740-adc.h30 #define JZ_ADC_CONFIG_CLKDIV(div) ((div) << 5)
H A Dktime.h169 extern s64 __ktime_divns(const ktime_t kt, s64 div); ktime_divns()
170 static inline s64 ktime_divns(const ktime_t kt, s64 div) ktime_divns() argument
176 BUG_ON(div < 0); ktime_divns()
177 if (__builtin_constant_p(div) && !(div >> 32)) { ktime_divns()
181 do_div(tmp, div); ktime_divns()
184 return __ktime_divns(kt, div); ktime_divns()
188 static inline s64 ktime_divns(const ktime_t kt, s64 div)
194 WARN_ON(div < 0);
195 return kt.tv64 / div;
/linux-4.1.27/drivers/clk/shmobile/
H A Dclk-r8a73a4.c70 unsigned int div = 1; r8a73a4_cpg_register_clock() local
82 div = 2; r8a73a4_cpg_register_clock()
89 div = 2; r8a73a4_cpg_register_clock()
103 div = 2; r8a73a4_cpg_register_clock()
111 div = 2; r8a73a4_cpg_register_clock()
132 div = 2; r8a73a4_cpg_register_clock()
136 div = 2; r8a73a4_cpg_register_clock()
140 div = 4; r8a73a4_cpg_register_clock()
160 div = 2; r8a73a4_cpg_register_clock()
163 div *= 32; r8a73a4_cpg_register_clock()
184 mult, div); r8a73a4_cpg_register_clock()
H A Dclk-r8a7779.c100 unsigned int div = 1; r8a7779_cpg_register_clock() local
106 div = config->z_div; r8a7779_cpg_register_clock()
109 div = config->zs_and_s_div; r8a7779_cpg_register_clock()
111 div = config->s1_div; r8a7779_cpg_register_clock()
113 div = config->p_div; r8a7779_cpg_register_clock()
115 div = config->b_and_out_div; r8a7779_cpg_register_clock()
120 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div); r8a7779_cpg_register_clock()
H A Dclk-div6.c29 * @div: divisor value (1-64)
34 unsigned int div; member in struct:div6_clock
48 | CPG_DIV6_DIV(clock->div - 1); cpg_div6_clock_enable()
83 unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; cpg_div6_clock_recalc_rate() local
85 return parent_rate / div; cpg_div6_clock_recalc_rate()
91 unsigned int div; cpg_div6_clock_calc_div() local
96 div = DIV_ROUND_CLOSEST(parent_rate, rate); cpg_div6_clock_calc_div()
97 return clamp_t(unsigned int, div, 1, 64); cpg_div6_clock_calc_div()
103 unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate); cpg_div6_clock_round_rate() local
105 return *parent_rate / div; cpg_div6_clock_round_rate()
112 unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate); cpg_div6_clock_set_rate() local
115 clock->div = div; cpg_div6_clock_set_rate()
120 clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg); cpg_div6_clock_set_rate()
215 clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; cpg_div6_clock_init()
H A Dclk-rcar-gen2.c179 fixed->div = 6; cpg_rcan_clk_register()
213 struct clk_divider *div; cpg_adsp_clk_register() local
217 div = kzalloc(sizeof(*div), GFP_KERNEL); cpg_adsp_clk_register()
218 if (!div) cpg_adsp_clk_register()
221 div->reg = cpg->reg + CPG_ADSPCKCR; cpg_adsp_clk_register()
222 div->width = 4; cpg_adsp_clk_register()
223 div->table = cpg_adsp_div_table; cpg_adsp_clk_register()
224 div->lock = &cpg->lock; cpg_adsp_clk_register()
228 kfree(div); cpg_adsp_clk_register()
238 &div->hw, &clk_divider_ops, cpg_adsp_clk_register()
242 kfree(div); cpg_adsp_clk_register()
309 unsigned int div = 1; rcar_gen2_cpg_register_clock() local
313 div = config->extal_div; rcar_gen2_cpg_register_clock()
331 div = cpg_mode & BIT(18) ? 36 : 24; rcar_gen2_cpg_register_clock()
334 div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) rcar_gen2_cpg_register_clock()
360 mult, div); rcar_gen2_cpg_register_clock()
H A Dclk-r8a7740.c72 unsigned int div = 1; r8a7740_cpg_register_clock() local
79 div = 2048; r8a7740_cpg_register_clock()
84 div = 1024; r8a7740_cpg_register_clock()
94 div = 2; r8a7740_cpg_register_clock()
108 div = 2; r8a7740_cpg_register_clock()
121 div = 2; r8a7740_cpg_register_clock()
139 mult, div); r8a7740_cpg_register_clock()
H A Dclk-r8a7778.c39 unsigned int div[4]; member in struct:__anon3755
71 r8a7778_divs[i].div[cpg_mode_divs]); r8a7778_cpg_register_clock()
H A Dclk-sh73a0.c84 unsigned int div = 1; sh73a0_cpg_register_clock() local
91 div = (parent_idx & 1) + 1; sh73a0_cpg_register_clock()
156 mult, div); sh73a0_cpg_register_clock()
/linux-4.1.27/drivers/clk/bcm/
H A Dclk-bcm281xx.c26 .div = FRAC_DIVIDER(0x0e00, 0, 22, 16),
56 .div = DIVIDER(0x0a04, 3, 4),
64 .div = DIVIDER(0x0a00, 4, 5),
110 .div = DIVIDER(0x0a28, 4, 14),
122 .div = DIVIDER(0x0a2c, 4, 14),
134 .div = DIVIDER(0x0a34, 4, 14),
146 .div = DIVIDER(0x0a30, 4, 14),
155 .div = FIXED_DIVIDER(2),
167 .div = FIXED_DIVIDER(2),
174 .div = DIVIDER(0x0a38, 12, 2),
212 .div = FRAC_DIVIDER(0x0a10, 4, 12, 8),
222 .div = FRAC_DIVIDER(0x0a14, 4, 12, 8),
232 .div = FRAC_DIVIDER(0x0a18, 4, 12, 8),
242 .div = FRAC_DIVIDER(0x0a1c, 4, 12, 8),
254 .div = DIVIDER(0x0a20, 4, 14),
266 .div = DIVIDER(0x0a28, 4, 14),
308 .div = DIVIDER(0x0a70, 4, 3),
H A Dclk-kona.c56 static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div) scaled_div_value() argument
58 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); scaled_div_value()
66 u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths) scaled_div_build() argument
74 combined <<= div->u.s.frac_width; scaled_div_build()
81 scaled_div_min(struct bcm_clk_div *div) scaled_div_min() argument
83 if (divider_is_fixed(div)) scaled_div_min()
84 return (u64)div->u.fixed; scaled_div_min()
86 return scaled_div_value(div, 0); scaled_div_min()
90 u64 scaled_div_max(struct bcm_clk_div *div) scaled_div_max() argument
94 if (divider_is_fixed(div)) scaled_div_max()
95 return (u64)div->u.fixed; scaled_div_max()
97 reg_div = ((u32)1 << div->u.s.width) - 1; scaled_div_max()
99 return scaled_div_value(div, reg_div); scaled_div_max()
107 divider(struct bcm_clk_div *div, u64 scaled_div) divider() argument
109 BUG_ON(scaled_div < scaled_div_min(div)); divider()
110 BUG_ON(scaled_div > scaled_div_max(div)); divider()
112 return (u32)(scaled_div - ((u64)1 << div->u.s.frac_width)); divider()
117 scale_rate(struct bcm_clk_div *div, u32 rate) scale_rate() argument
119 if (divider_is_fixed(div)) scale_rate()
122 return (u64)rate << div->u.s.frac_width; scale_rate()
562 static u64 divider_read_scaled(struct ccu_data *ccu, struct bcm_clk_div *div) divider_read_scaled() argument
568 if (divider_is_fixed(div)) divider_read_scaled()
569 return (u64)div->u.fixed; divider_read_scaled()
572 reg_val = __ccu_read(ccu, div->u.s.offset); divider_read_scaled()
576 reg_div = bitfield_extract(reg_val, div->u.s.shift, div->u.s.width); divider_read_scaled()
579 return scaled_div_value(div, reg_div); divider_read_scaled()
590 struct bcm_clk_div *div, struct bcm_clk_trig *trig) __div_commit()
597 BUG_ON(divider_is_fixed(div)); __div_commit()
604 if (div->u.s.scaled_div == BAD_SCALED_DIV_VALUE) { __div_commit()
605 reg_val = __ccu_read(ccu, div->u.s.offset); __div_commit()
606 reg_div = bitfield_extract(reg_val, div->u.s.shift, __div_commit()
607 div->u.s.width); __div_commit()
608 div->u.s.scaled_div = scaled_div_value(div, reg_div); __div_commit()
614 reg_div = divider(div, div->u.s.scaled_div); __div_commit()
624 reg_val = __ccu_read(ccu, div->u.s.offset); __div_commit()
625 reg_val = bitfield_replace(reg_val, div->u.s.shift, div->u.s.width, __div_commit()
627 __ccu_write(ccu, div->u.s.offset, reg_val); __div_commit()
646 struct bcm_clk_div *div, struct bcm_clk_trig *trig) div_init()
648 if (!divider_exists(div) || divider_is_fixed(div)) div_init()
650 return !__div_commit(ccu, gate, div, trig); div_init()
654 struct bcm_clk_div *div, struct bcm_clk_trig *trig, divider_write()
661 BUG_ON(divider_is_fixed(div)); divider_write()
663 previous = div->u.s.scaled_div; divider_write()
667 div->u.s.scaled_div = scaled_div; divider_write()
672 ret = __div_commit(ccu, gate, div, trig); divider_write()
678 div->u.s.scaled_div = previous; /* Revert the change */ divider_write()
692 struct bcm_clk_div *div, struct bcm_clk_div *pre_div, clk_recalc_rate()
699 if (!divider_exists(div)) clk_recalc_rate()
718 scaled_rate = scale_rate(div, scaled_rate); clk_recalc_rate()
723 scaled_parent_rate = scale_rate(div, parent_rate); clk_recalc_rate()
731 scaled_div = divider_read_scaled(ccu, div); clk_recalc_rate()
746 static long round_rate(struct ccu_data *ccu, struct bcm_clk_div *div, round_rate() argument
757 BUG_ON(!divider_exists(div)); round_rate()
777 scaled_rate = scale_rate(div, scaled_rate); round_rate()
782 scaled_parent_rate = scale_rate(div, parent_rate); round_rate()
790 if (!divider_is_fixed(div)) { round_rate()
793 min_scaled_div = scaled_div_min(div); round_rate()
794 max_scaled_div = scaled_div_max(div); round_rate()
800 best_scaled_div = divider_read_scaled(ccu, div); round_rate()
1002 return clk_recalc_rate(bcm_clk->ccu, &data->div, &data->pre_div, kona_peri_clk_recalc_rate()
1010 struct bcm_clk_div *div = &bcm_clk->u.peri->div; kona_peri_clk_round_rate() local
1012 if (!divider_exists(div)) kona_peri_clk_round_rate()
1016 return round_rate(bcm_clk->ccu, div, &bcm_clk->u.peri->pre_div, kona_peri_clk_round_rate()
1126 struct bcm_clk_div *div = &data->div; kona_peri_clk_set_rate() local
1136 if (!divider_exists(div)) kona_peri_clk_set_rate()
1144 if (divider_is_fixed(&data->div)) kona_peri_clk_set_rate()
1152 (void)round_rate(bcm_clk->ccu, div, &data->pre_div, kona_peri_clk_set_rate()
1159 ret = divider_write(bcm_clk->ccu, &data->gate, &data->div, kona_peri_clk_set_rate()
1207 if (!div_init(ccu, &peri->gate, &peri->div, &peri->trig)) { __peri_clk_init()
589 __div_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate, struct bcm_clk_div *div, struct bcm_clk_trig *trig) __div_commit() argument
645 div_init(struct ccu_data *ccu, struct bcm_clk_gate *gate, struct bcm_clk_div *div, struct bcm_clk_trig *trig) div_init() argument
653 divider_write(struct ccu_data *ccu, struct bcm_clk_gate *gate, struct bcm_clk_div *div, struct bcm_clk_trig *trig, u64 scaled_div) divider_write() argument
691 clk_recalc_rate(struct ccu_data *ccu, struct bcm_clk_div *div, struct bcm_clk_div *pre_div, unsigned long parent_rate) clk_recalc_rate() argument
H A Dclk-bcm21664.c73 .div = DIVIDER(0x0a28, 4, 14),
85 .div = DIVIDER(0x0a2c, 4, 14),
97 .div = DIVIDER(0x0a34, 4, 14),
109 .div = DIVIDER(0x0a30, 4, 14),
168 .div = FRAC_DIVIDER(0x0a10, 4, 12, 8),
178 .div = FRAC_DIVIDER(0x0a14, 4, 12, 8),
188 .div = FRAC_DIVIDER(0x0a18, 4, 12, 8),
H A Dclk-kona-setup.c57 struct bcm_clk_div *div; clk_requires_trigger() local
66 div = &peri->div; clk_requires_trigger()
67 if (!divider_exists(div)) clk_requires_trigger()
71 if (!divider_is_fixed(div)) clk_requires_trigger()
74 div = &peri->pre_div; clk_requires_trigger()
76 return divider_exists(div) && !divider_is_fixed(div); clk_requires_trigger()
85 struct bcm_clk_div *div; peri_clk_data_offsets_valid() local
131 div = &peri->div; peri_clk_data_offsets_valid()
132 if (divider_exists(div)) { peri_clk_data_offsets_valid()
133 if (div->u.s.offset > limit) { peri_clk_data_offsets_valid()
135 __func__, name, div->u.s.offset, limit); peri_clk_data_offsets_valid()
140 div = &peri->pre_div; peri_clk_data_offsets_valid()
141 if (divider_exists(div)) { peri_clk_data_offsets_valid()
142 if (div->u.s.offset > limit) { peri_clk_data_offsets_valid()
145 __func__, name, div->u.s.offset, limit); peri_clk_data_offsets_valid()
337 static bool div_valid(struct bcm_clk_div *div, const char *field_name, div_valid() argument
340 if (divider_is_fixed(div)) { div_valid()
342 if (div->u.fixed == 0) { div_valid()
349 if (!bitfield_valid(div->u.s.shift, div->u.s.width, div_valid()
353 if (divider_has_fraction(div)) div_valid()
354 if (div->u.s.frac_width > div->u.s.width) { div_valid()
357 div->u.s.frac_width, div->u.s.width); div_valid()
373 struct bcm_clk_div *div; kona_dividers_valid() local
379 if (!divider_exists(&peri->div) || !divider_exists(&peri->pre_div)) kona_dividers_valid()
382 div = &peri->div; kona_dividers_valid()
384 if (divider_is_fixed(div) || divider_is_fixed(pre_div)) kona_dividers_valid()
389 return div->u.s.frac_width + pre_div->u.s.frac_width <= limit; kona_dividers_valid()
409 struct bcm_clk_div *div; peri_clk_data_valid() local
451 div = &peri->div; peri_clk_data_valid()
453 if (divider_exists(div)) { peri_clk_data_valid()
454 if (!div_valid(div, "divider", name)) peri_clk_data_valid()
/linux-4.1.27/drivers/media/tuners/
H A Dtea5767.c60 /* if on, div=4*(Frf+Fif)/Fref otherwise, div=4*(Frf-Fif)/Freq) */
136 unsigned int div, frq; tea5767_status_dump() local
148 div = ((buffer[0] & 0x3f) << 8) | buffer[1]; tea5767_status_dump()
152 frq = (div * 50000 - 700000 - 225000) / 4; /* Freq in KHz */ tea5767_status_dump()
155 frq = (div * 50000 + 700000 + 225000) / 4; /* Freq in KHz */ tea5767_status_dump()
158 frq = (div * 32768 + 700000 + 225000) / 4; /* Freq in KHz */ tea5767_status_dump()
162 frq = (div * 32768 - 700000 - 225000) / 4; /* Freq in KHz */ tea5767_status_dump()
165 buffer[0] = (div >> 8) & 0x3f; tea5767_status_dump()
166 buffer[1] = div & 0xff; tea5767_status_dump()
169 frq / 1000, frq % 1000, div); tea5767_status_dump()
194 unsigned div; set_radio_freq() local
245 div = (frq * (4000 / 16) + 700000 + 225000 + 25000) / 50000; set_radio_freq()
250 div = (frq * (4000 / 16) - 700000 - 225000 + 25000) / 50000; set_radio_freq()
256 div = ((frq * (4000 / 16) - 700000 - 225000) + 16384) >> 15; set_radio_freq()
264 div = ((frq * (4000 / 16) + 700000 + 225000) + 16384) >> 15; set_radio_freq()
267 buffer[0] = (div >> 8) & 0x3f; set_radio_freq()
268 buffer[1] = div & 0xff; set_radio_freq()
353 unsigned div, rc; tea5767_standby() local
355 div = (87500 * 4 + 700 + 225 + 25) / 50; /* Set frequency to 87.5 MHz */ tea5767_standby()
356 buffer[0] = (div >> 8) & 0x3f; tea5767_standby()
357 buffer[1] = div & 0xff; tea5767_standby()
H A Dtea5761.c128 unsigned int div, frq; tea5761_status_dump() local
130 div = ((buffer[2] & 0x3f) << 8) | buffer[3]; tea5761_status_dump()
132 frq = 1000 * (div * 32768 / 1000 + FREQ_OFFSET + 225) / 4; /* Freq in KHz */ tea5761_status_dump()
135 frq / 1000, frq % 1000, div); tea5761_status_dump()
146 unsigned div; __set_radio_freq() local
166 div = (1000 * (frq * 4 / 16 + 700 + 225) ) >> 15; __set_radio_freq()
167 buffer[1] = (div >> 8) & 0x3f; __set_radio_freq()
168 buffer[2] = div & 0xff; __set_radio_freq()
H A Dtuner-simple.c441 u16 div, u8 config, u8 cb) simple_post_tune()
477 buffer[0] = (div>>8) & 0x7f; simple_post_tune()
478 buffer[1] = div & 0xff; simple_post_tune()
549 u16 div; simple_set_tv_freq() local
587 div = params->frequency + IFPCoff + offset; simple_set_tv_freq()
590 "Offset=%d.%02d MHz, div=%0d\n", simple_set_tv_freq()
593 offset / 16, offset % 16 * 100 / 16, div); simple_set_tv_freq()
598 if (t_params->cb_first_if_lower_freq && div < priv->last_div) { simple_set_tv_freq()
601 buffer[2] = (div>>8) & 0x7f; simple_set_tv_freq()
602 buffer[3] = div & 0xff; simple_set_tv_freq()
604 buffer[0] = (div>>8) & 0x7f; simple_set_tv_freq()
605 buffer[1] = div & 0xff; simple_set_tv_freq()
609 priv->last_div = div; simple_set_tv_freq()
661 simple_post_tune(fe, &buffer[0], div, config, cb); simple_set_tv_freq()
672 u16 div; simple_set_radio_freq() local
711 div = (freq + 400) / 800; simple_set_radio_freq()
713 if (t_params->cb_first_if_lower_freq && div < priv->last_div) { simple_set_radio_freq()
716 buffer[2] = (div>>8) & 0x7f; simple_set_radio_freq()
717 buffer[3] = div & 0xff; simple_set_radio_freq()
719 buffer[0] = (div>>8) & 0x7f; simple_set_radio_freq()
720 buffer[1] = div & 0xff; simple_set_radio_freq()
725 priv->last_div = div; simple_set_radio_freq()
854 u32 div; simple_dvb_configure() local
872 div = ((frequency + t_params->iffreq) * 62500 + offset + simple_dvb_configure()
875 buf[0] = div >> 8; simple_dvb_configure()
876 buf[1] = div & 0xff; simple_dvb_configure()
882 tuner_dbg("%s: div=%d | buf=0x%02x,0x%02x,0x%02x,0x%02x\n", simple_dvb_configure()
883 tun->name, div, buf[0], buf[1], buf[2], buf[3]); simple_dvb_configure()
886 return (div * tun->stepsize) - t_params->iffreq; simple_dvb_configure()
440 simple_post_tune(struct dvb_frontend *fe, u8 *buffer, u16 div, u8 config, u8 cb) simple_post_tune() argument
H A Dm88rs6000t.c40 u32 div, ts_mclk; m88rs6000t_set_demod_mclk() local
69 div = 36000 * pll_div_fb; m88rs6000t_set_demod_mclk()
70 div /= ts_mclk; m88rs6000t_set_demod_mclk()
72 if (div <= 32) { m88rs6000t_set_demod_mclk()
75 f1 = div / 2; m88rs6000t_set_demod_mclk()
76 f2 = div - f1; m88rs6000t_set_demod_mclk()
78 } else if (div <= 48) { m88rs6000t_set_demod_mclk()
80 f0 = div / 3; m88rs6000t_set_demod_mclk()
81 f1 = (div - f0) / 2; m88rs6000t_set_demod_mclk()
82 f2 = div - f0 - f1; m88rs6000t_set_demod_mclk()
84 } else if (div <= 64) { m88rs6000t_set_demod_mclk()
86 f0 = div / 4; m88rs6000t_set_demod_mclk()
87 f1 = (div - f0) / 3; m88rs6000t_set_demod_mclk()
88 f2 = (div - f0 - f1) / 2; m88rs6000t_set_demod_mclk()
89 f3 = div - f0 - f1 - f2; m88rs6000t_set_demod_mclk()
H A Dmxl301rf.c183 u32 tmp, div; mxl301rf_set_params() local
206 div = 1000000; mxl301rf_set_params()
209 div >>= 1; mxl301rf_set_params()
210 if (tmp > div) { mxl301rf_set_params()
211 tmp -= div; mxl301rf_set_params()
/linux-4.1.27/drivers/media/dvb-frontends/
H A Dtdhd1.h49 u32 div; alps_tdhd1_204a_tuner_set_params() local
51 div = (p->frequency + 36166666) / 166666; alps_tdhd1_204a_tuner_set_params()
53 data[0] = (div >> 8) & 0x7f; alps_tdhd1_204a_tuner_set_params()
54 data[1] = div & 0xff; alps_tdhd1_204a_tuner_set_params()
H A Dbsbe1.h77 u32 div; alps_bsbe1_tuner_set_params() local
84 div = p->frequency / 1000; alps_bsbe1_tuner_set_params()
85 data[0] = (div >> 8) & 0x7f; alps_bsbe1_tuner_set_params()
86 data[1] = div & 0xff; alps_bsbe1_tuner_set_params()
87 data[2] = 0x80 | ((div & 0x18000) >> 10) | 0x1; alps_bsbe1_tuner_set_params()
H A Dtua6100.c74 u32 div; tua6100_set_params() local
119 div = prediv / _P; tua6100_set_params()
120 reg1[1] |= (div >> 9) & 0x03; tua6100_set_params()
121 reg1[2] = div >> 1; tua6100_set_params()
122 reg1[3] = (div << 7); tua6100_set_params()
123 priv->frequency = ((div * _P) * (_ri / 1000)) / _R; tua6100_set_params()
126 reg1[3] |= (prediv - (div*_P)) & 0x7f; tua6100_set_params()
H A Dbsru6.h108 u32 div; alps_bsru6_tuner_set_params() local
115 div = (p->frequency + (125 - 1)) / 125; /* round correctly */ alps_bsru6_tuner_set_params()
116 buf[0] = (div >> 8) & 0x7f; alps_bsru6_tuner_set_params()
117 buf[1] = div & 0xff; alps_bsru6_tuner_set_params()
118 buf[2] = 0x80 | ((div & 0x18000) >> 10) | 4; alps_bsru6_tuner_set_params()
H A Dtda826x.c79 u32 div; tda826x_set_params() local
87 div = (p->frequency + (1000-1)) / 1000; tda826x_set_params()
103 buf[3] = div >> 7; tda826x_set_params()
104 buf[4] = div << 1; tda826x_set_params()
120 priv->frequency = div * 1000; tda826x_set_params()
H A Dzl10036.c187 u32 div, foffset; zl10036_set_frequency() local
189 div = (frequency + _FR/2) / _FR; zl10036_set_frequency()
190 state->frequency = div * _FR; zl10036_set_frequency()
194 buf[0] = (div >> 8) & 0x7f; zl10036_set_frequency()
195 buf[1] = (div >> 0) & 0xff; zl10036_set_frequency()
197 deb_info("%s: ftodo=%u fpriv=%u ferr=%d div=%u\n", __func__, zl10036_set_frequency()
198 frequency, state->frequency, foffset, div); zl10036_set_frequency()
400 { 0x04, 0x00 }, /* 2/3: div=0x400 - arbitrary value */ zl10036_init_regs()
/linux-4.1.27/drivers/clk/socfpga/
H A Dclk-periph.c32 u32 div, val; clk_periclk_recalc_rate() local
35 div = socfpgaclk->fixed_div; clk_periclk_recalc_rate()
42 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); clk_periclk_recalc_rate()
45 return parent_rate / div; clk_periclk_recalc_rate()
73 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); __socfpga_periph_init()
H A Dclk-gate.c107 u32 div = 1, val; socfpga_clk_recalc_rate() local
110 div = socfpgaclk->fixed_div; socfpga_clk_recalc_rate()
116 div = val + 1; socfpga_clk_recalc_rate()
118 div = (1 << val); socfpga_clk_recalc_rate()
121 return parent_rate / div; socfpga_clk_recalc_rate()
221 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); __socfpga_gate_init()
/linux-4.1.27/drivers/pwm/
H A Dpwm-sun4i.c103 u64 clk_rate, div = 0; sun4i_pwm_config() local
117 div = clk_rate * period_ns + NSEC_PER_SEC/2; sun4i_pwm_config()
118 do_div(div, NSEC_PER_SEC); sun4i_pwm_config()
119 if (div - 1 > PWM_PRD_MASK) sun4i_pwm_config()
128 div = clk_rate; sun4i_pwm_config()
129 do_div(div, prescaler_table[prescaler]); sun4i_pwm_config()
130 div = div * period_ns; sun4i_pwm_config()
131 do_div(div, NSEC_PER_SEC); sun4i_pwm_config()
132 if (div - 1 <= PWM_PRD_MASK) sun4i_pwm_config()
136 if (div - 1 > PWM_PRD_MASK) { sun4i_pwm_config()
142 prd = div; sun4i_pwm_config()
143 div *= duty_ns; sun4i_pwm_config()
144 do_div(div, period_ns); sun4i_pwm_config()
145 dty = div; sun4i_pwm_config()
H A Dpwm-mxs.c35 #define PERIOD_CDIV(div) (((div) & 0x7) << 20)
54 int ret, div = 0; mxs_pwm_config() local
61 c = rate / cdiv[div]; mxs_pwm_config()
66 div++; mxs_pwm_config()
67 if (div >= PERIOD_CDIV_MAX) mxs_pwm_config()
89 PERIOD_INACTIVE_LOW | PERIOD_CDIV(div), mxs_pwm_config()
H A Dpwm-rockchip.c106 u64 clk_rate, div; rockchip_pwm_config() local
116 div = clk_rate * period_ns; rockchip_pwm_config()
117 do_div(div, pc->data->prescaler * NSEC_PER_SEC); rockchip_pwm_config()
118 period = div; rockchip_pwm_config()
120 div = clk_rate * duty_ns; rockchip_pwm_config()
121 do_div(div, pc->data->prescaler * NSEC_PER_SEC); rockchip_pwm_config()
122 duty = div; rockchip_pwm_config()
H A Dpwm-atmel.c106 unsigned long long div; atmel_pwm_config() local
117 div = (unsigned long long)clk_get_rate(atmel_pwm->clk) * period_ns; atmel_pwm_config()
118 do_div(div, NSEC_PER_SEC); atmel_pwm_config()
120 while (div > PWM_MAX_PRD) { atmel_pwm_config()
121 div >>= 1; atmel_pwm_config()
131 prd = div; atmel_pwm_config()
132 div *= duty_ns; atmel_pwm_config()
133 do_div(div, period_ns); atmel_pwm_config()
134 dty = prd - div; atmel_pwm_config()
H A Dpwm-img.c91 u32 val, div, duty, timebase; img_pwm_config() local
107 div = PWM_CTRL_CFG_NO_SUB_DIV; img_pwm_config()
110 div = PWM_CTRL_CFG_SUB_DIV0; img_pwm_config()
113 div = PWM_CTRL_CFG_SUB_DIV1; img_pwm_config()
116 div = PWM_CTRL_CFG_SUB_DIV0_DIV1; img_pwm_config()
128 val |= (div & PWM_CTRL_CFG_DIV_MASK) << img_pwm_config()
H A Dpwm-spear.c81 u64 val, div, clk_rate; spear_pwm_config() local
97 div = 1000000000; spear_pwm_config()
98 div *= 1 + prescale; spear_pwm_config()
100 pv = div64_u64(val, div); spear_pwm_config()
102 dc = div64_u64(val, div); spear_pwm_config()
H A Dpwm-atmel-tcb.c35 unsigned div; /* PWM clock divider */ member in struct:atmel_tcb_pwm_device
89 tcbpwm->div = 0; atmel_tcb_pwm_request()
105 tcbpwm->div = cmr & ATMEL_TC_TCCLKS; atmel_tcb_pwm_request()
252 cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS); atmel_tcb_pwm_enable()
339 (atcbpwm->div != i || atcbpwm->period != period)) { atmel_tcb_pwm_config()
346 tcbpwm->div = i; atmel_tcb_pwm_config()
/linux-4.1.27/drivers/gpu/drm/nouveau/
H A Dnouveau_backlight.c102 u32 div = 1025; nv50_get_intensity() local
107 return ((val * 100) + (div / 2)) / div; nv50_get_intensity()
117 u32 div = 1025; nv50_set_intensity() local
118 u32 val = (bd->props.brightness * div) / 100; nv50_set_intensity()
138 u32 div, val; nva3_get_intensity() local
140 div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); nva3_get_intensity()
143 if (div && div >= val) nva3_get_intensity()
144 return ((val * 100) + (div / 2)) / div; nva3_get_intensity()
156 u32 div, val; nva3_set_intensity() local
158 div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); nva3_set_intensity()
159 val = (bd->props.brightness * div) / 100; nva3_set_intensity()
160 if (div) { nva3_set_intensity()
/linux-4.1.27/drivers/video/fbdev/omap/
H A Dhwa742.c629 static unsigned long round_to_extif_ticks(unsigned long ps, int div) round_to_extif_ticks() argument
631 int bus_tick = hwa742.extif_clk_period * div; round_to_extif_ticks()
635 static int calc_reg_timing(unsigned long sysclk, int div) calc_reg_timing() argument
650 "extif_clk_div %d\n", systim, hwa742.extif_clk_period, div); calc_reg_timing()
654 t->clk_div = div; calc_reg_timing()
656 t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div); calc_reg_timing()
657 t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div); calc_reg_timing()
658 t->access_time = round_to_extif_ticks(t->re_on_time + 12200, div); calc_reg_timing()
659 t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div); calc_reg_timing()
660 t->re_off_time = round_to_extif_ticks(t->re_on_time + 16000, div); calc_reg_timing()
661 t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div); calc_reg_timing()
662 t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div); calc_reg_timing()
665 t->re_cycle_time = round_to_extif_ticks(2 * systim + 2000, div); calc_reg_timing()
681 static int calc_lut_timing(unsigned long sysclk, int div) calc_lut_timing() argument
697 "extif_clk_div %d\n", systim, hwa742.extif_clk_period, div); calc_lut_timing()
702 t->clk_div = div; calc_lut_timing()
705 t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div); calc_lut_timing()
706 t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div); calc_lut_timing()
708 26000, div); calc_lut_timing()
709 t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div); calc_lut_timing()
711 26000, div); calc_lut_timing()
712 t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div); calc_lut_timing()
713 t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div); calc_lut_timing()
716 t->re_cycle_time = round_to_extif_ticks(2000 + 4 * systim + 26000, div); calc_lut_timing()
735 int div; calc_extif_timings() local
738 for (div = 1; div < max_clk_div; div++) { calc_extif_timings()
739 if (calc_reg_timing(sysclk, div) == 0) calc_extif_timings()
742 if (div >= max_clk_div) calc_extif_timings()
745 *extif_mem_div = div; calc_extif_timings()
747 for (div = 1; div < max_clk_div; div++) { calc_extif_timings()
748 if (calc_lut_timing(sysclk, div) == 0) calc_extif_timings()
752 if (div >= max_clk_div) calc_extif_timings()
H A Dsossi.c125 static u32 ps_to_sossi_ticks(u32 ps, int div) ps_to_sossi_ticks() argument
127 u32 clk_period = HZ_TO_PS(sossi.fck_hz) * div; ps_to_sossi_ticks()
135 int div = t->clk_div; calc_rd_timings() local
141 reon = ps_to_sossi_ticks(t->re_on_time, div); calc_rd_timings()
146 reoff = ps_to_sossi_ticks(t->re_off_time, div); calc_rd_timings()
155 recyc = ps_to_sossi_ticks(t->re_cycle_time, div); calc_rd_timings()
166 actim = ps_to_sossi_ticks(t->access_time, div); calc_rd_timings()
186 int div = t->clk_div; calc_wr_timings() local
192 weon = ps_to_sossi_ticks(t->we_on_time, div); calc_wr_timings()
197 weoff = ps_to_sossi_ticks(t->we_off_time, div); calc_wr_timings()
204 wecyc = ps_to_sossi_ticks(t->we_cycle_time, div); calc_wr_timings()
221 static void _set_timing(int div, int tw0, int tw1) _set_timing() argument
226 dev_dbg(sossi.fbdev->dev, "Using TW0 = %d, TW1 = %d, div = %d\n", _set_timing()
227 tw0 + 1, tw1 + 1, div); _set_timing()
230 clk_set_rate(sossi.fck, sossi.fck_hz / div); _set_timing()
328 int div = t->clk_div; sossi_convert_timings() local
332 if (div <= 0 || div > 8) sossi_convert_timings()
342 t->tim[4] = div; sossi_convert_timings()
396 int hs_pol_inv, int vs_pol_inv, int div) sossi_setup_tearsync()
401 if (pin_cnt != 1 || div < 1 || div > 8) sossi_setup_tearsync()
404 hs = ps_to_sossi_ticks(hs_pulse_time, div); sossi_setup_tearsync()
405 vs = ps_to_sossi_ticks(vs_pulse_time, div); sossi_setup_tearsync()
394 sossi_setup_tearsync(unsigned pin_cnt, unsigned hs_pulse_time, unsigned vs_pulse_time, int hs_pol_inv, int vs_pol_inv, int div) sossi_setup_tearsync() argument
/linux-4.1.27/drivers/video/fbdev/omap2/dss/
H A Drfbi.c387 static inline unsigned long round_to_extif_ticks(unsigned long ps, int div) round_to_extif_ticks() argument
389 int bus_tick = extif_clk_period * div; round_to_extif_ticks()
393 static int calc_reg_timing(struct rfbi_timings *t, int div) calc_reg_timing() argument
395 t->clk_div = div; calc_reg_timing()
397 t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div); calc_reg_timing()
399 t->we_on_time = round_to_extif_ticks(t->we_on_time, div); calc_reg_timing()
400 t->we_off_time = round_to_extif_ticks(t->we_off_time, div); calc_reg_timing()
401 t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div); calc_reg_timing()
403 t->re_on_time = round_to_extif_ticks(t->re_on_time, div); calc_reg_timing()
404 t->re_off_time = round_to_extif_ticks(t->re_off_time, div); calc_reg_timing()
405 t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div); calc_reg_timing()
407 t->access_time = round_to_extif_ticks(t->access_time, div); calc_reg_timing()
408 t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div); calc_reg_timing()
409 t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div); calc_reg_timing()
425 int div; calc_extif_timings() local
428 for (div = 1; div <= max_clk_div; div++) { calc_extif_timings()
429 if (calc_reg_timing(t, div) == 0) calc_extif_timings()
433 if (div <= max_clk_div) calc_extif_timings()
463 static int ps_to_rfbi_ticks(int time, int div) ps_to_rfbi_ticks() argument
469 tick_ps = 1000000000 / (rfbi.l4_khz) * div; ps_to_rfbi_ticks()
487 int div = t->clk_div; rfbi_convert_timings() local
489 if (div <= 0 || div > 2) rfbi_convert_timings()
496 weon = ps_to_rfbi_ticks(t->we_on_time, div); rfbi_convert_timings()
497 weoff = ps_to_rfbi_ticks(t->we_off_time, div); rfbi_convert_timings()
505 reon = ps_to_rfbi_ticks(t->re_on_time, div); rfbi_convert_timings()
506 reoff = ps_to_rfbi_ticks(t->re_off_time, div); rfbi_convert_timings()
514 cson = ps_to_rfbi_ticks(t->cs_on_time, div); rfbi_convert_timings()
515 csoff = ps_to_rfbi_ticks(t->cs_off_time, div); rfbi_convert_timings()
534 actim = ps_to_rfbi_ticks(t->access_time, div); rfbi_convert_timings()
540 wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div); rfbi_convert_timings()
546 recyc = ps_to_rfbi_ticks(t->re_cycle_time, div); rfbi_convert_timings()
552 cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div); rfbi_convert_timings()
563 t->tim[2] = div - 1; rfbi_convert_timings()
/linux-4.1.27/drivers/clk/samsung/
H A Dclk-s3c2443.c128 { .val = 0, .div = 1 },
129 { .val = 1, .div = 2 },
130 { .val = 3, .div = 4 },
135 { .val = 0, .div = 1 },
136 { .val = 1, .div = 3 },
137 { .val = 2, .div = 5 },
138 { .val = 3, .div = 7 },
139 { .val = 4, .div = 9 },
140 { .val = 5, .div = 11 },
141 { .val = 6, .div = 13 },
142 { .val = 7, .div = 15 },
237 { .val = 0, .div = 1 },
238 { .val = 1, .div = 2 },
239 { .val = 2, .div = 3 },
240 { .val = 3, .div = 4 },
241 { .val = 5, .div = 6 },
242 { .val = 7, .div = 8 },
287 { .val = 0, .div = 1 },
288 { .val = 8, .div = 2 },
289 { .val = 2, .div = 3 },
290 { .val = 9, .div = 4 },
291 { .val = 10, .div = 6 },
292 { .val = 11, .div = 8 },
293 { .val = 13, .div = 12 },
294 { .val = 15, .div = 16 },
H A Dclk-s3c2410.c105 { .val = 0, .div = 1 },
106 { .val = 1, .div = 2 },
107 { .val = 2, .div = 4 },
108 { .val = 3, .div = 6 },
109 { .val = 4, .div = 8 },
110 { .val = 5, .div = 10 },
111 { .val = 6, .div = 12 },
112 { .val = 7, .div = 14 },
285 { .val = 0, .div = 4 },
286 { .val = 1, .div = 8 },
291 { .val = 0, .div = 3 },
292 { .val = 1, .div = 6 },
H A Dclk-s3c2412.c92 { .val = 0, .div = 1 }, s3c2412_clk_sleep_init()
93 { .val = 1, .div = 2 }, s3c2412_clk_sleep_init()
94 { .val = 2, .div = 4 }, s3c2412_clk_sleep_init()
95 { .val = 3, .div = 6 }, s3c2412_clk_sleep_init()
96 { .val = 4, .div = 8 }, s3c2412_clk_sleep_init()
97 { .val = 5, .div = 10 }, s3c2412_clk_sleep_init()
98 { .val = 6, .div = 12 }, s3c2412_clk_sleep_init()
99 { .val = 7, .div = 14 }, s3c2412_clk_sleep_init()
H A Dclk.h84 * @div: fixed division factor.
92 unsigned long div; member in struct:samsung_fixed_factor_clock
102 .div = d, \
163 * struct samsung_div_clock: information about div clock
165 * @name: name of this div clock.
168 * @offset: offset of the register for configuring the div.
169 * @shift: starting bit location of the div control bit-field in @reg.
170 * @div_flags: flags for div-type clock.
337 /* list of div clocks and respective count */
/linux-4.1.27/sound/soc/samsung/
H A Ds3c-i2s-v2.c450 int div_id, int div) s3c2412_i2s_set_clkdiv()
455 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div); s3c2412_i2s_set_clkdiv()
459 switch (div) { s3c2412_i2s_set_clkdiv()
461 div = S3C2412_IISMOD_BCLK_16FS; s3c2412_i2s_set_clkdiv()
465 div = S3C2412_IISMOD_BCLK_32FS; s3c2412_i2s_set_clkdiv()
469 div = S3C2412_IISMOD_BCLK_24FS; s3c2412_i2s_set_clkdiv()
473 div = S3C2412_IISMOD_BCLK_48FS; s3c2412_i2s_set_clkdiv()
482 writel(reg | div, i2s->regs + S3C2412_IISMOD); s3c2412_i2s_set_clkdiv()
488 switch (div) { s3c2412_i2s_set_clkdiv()
490 div = S3C2412_IISMOD_RCLK_256FS; s3c2412_i2s_set_clkdiv()
494 div = S3C2412_IISMOD_RCLK_384FS; s3c2412_i2s_set_clkdiv()
498 div = S3C2412_IISMOD_RCLK_512FS; s3c2412_i2s_set_clkdiv()
502 div = S3C2412_IISMOD_RCLK_768FS; s3c2412_i2s_set_clkdiv()
511 writel(reg | div, i2s->regs + S3C2412_IISMOD); s3c2412_i2s_set_clkdiv()
516 if (div >= 0) { s3c2412_i2s_set_clkdiv()
517 writel((div << 8) | S3C2412_IISPSR_PSREN, s3c2412_i2s_set_clkdiv()
567 unsigned int div; s3c_i2sv2_iis_calc_rate() local
587 div = fsclk / rate; s3c_i2sv2_iis_calc_rate()
590 div++; s3c_i2sv2_iis_calc_rate()
592 if (div <= 1) s3c_i2sv2_iis_calc_rate()
595 actual = clkrate / (fsdiv * div); s3c_i2sv2_iis_calc_rate()
598 printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n", s3c_i2sv2_iis_calc_rate()
599 fsdiv, div, actual, deviation); s3c_i2sv2_iis_calc_rate()
605 best_div = div; s3c_i2sv2_iis_calc_rate()
614 printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n", s3c_i2sv2_iis_calc_rate()
449 s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai, int div_id, int div) s3c2412_i2s_set_clkdiv() argument
H A Djive_wm8750.c43 struct s3c_i2sv2_rate_calc div; jive_hw_params() local
61 s3c_i2sv2_iis_calc_rate(&div, NULL, params_rate(params), jive_hw_params()
70 ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C2412_DIV_RCLK, div.fs_div); jive_hw_params()
75 div.clk_div - 1); jive_hw_params()
H A Drx1950_uda1380.c159 int div; rx1950_hw_params() local
169 div = s3c24xx_i2s_get_clockrate() / (256 * rate); rx1950_hw_params()
171 div++; rx1950_hw_params()
177 div = 1; rx1950_hw_params()
205 S3C24XX_PRESCALE(div, div)); rx1950_hw_params()
H A Dh1940_uda1380.c79 int div; h1940_hw_params() local
87 div = s3c24xx_i2s_get_clockrate() / (384 * rate); h1940_hw_params()
89 div++; h1940_hw_params()
117 S3C24XX_PRESCALE(div, div)); h1940_hw_params()
H A Ds3c24xx_uda134x.c136 unsigned int div; s3c24xx_uda134x_hw_params() local
156 div = 1; s3c24xx_uda134x_hw_params()
159 div = bi % 33; s3c24xx_uda134x_hw_params()
167 div, clk, err); s3c24xx_uda134x_hw_params()
191 S3C24XX_PRESCALE(div, div)); s3c24xx_uda134x_hw_params()
/linux-4.1.27/arch/unicore32/kernel/
H A Dclock.c102 unsigned long div; member in struct:__anon2956
104 {.rate = 25175000, .cfg = 0x00002001, .div = 0x9},
105 {.rate = 31500000, .cfg = 0x00002001, .div = 0x7},
106 {.rate = 40000000, .cfg = 0x00003801, .div = 0x9},
107 {.rate = 49500000, .cfg = 0x00003801, .div = 0x7},
108 {.rate = 65000000, .cfg = 0x00002c01, .div = 0x4},
109 {.rate = 78750000, .cfg = 0x00002400, .div = 0x7},
110 {.rate = 108000000, .cfg = 0x00002c01, .div = 0x2},
111 {.rate = 106500000, .cfg = 0x00003c01, .div = 0x3},
112 {.rate = 50650000, .cfg = 0x00106400, .div = 0x9},
113 {.rate = 61500000, .cfg = 0x00106400, .div = 0xa},
114 {.rate = 85500000, .cfg = 0x00002800, .div = 0x6},
147 pll_vgadiv = vga_clk_table[i].div; clk_set_rate()
167 /* set div cfg reg. */ clk_set_rate()
/linux-4.1.27/arch/blackfin/mach-bf609/
H A Dclock.c154 u32 div; pll_round_rate() local
155 div = rate / clk->parent->rate; pll_round_rate()
156 return clk->parent->rate * div; pll_round_rate()
190 u32 div = bfin_read32(CGU0_DIV); sys_clk_get_rate() local
191 div = (div & clk->mask) >> clk->shift; sys_clk_get_rate()
198 drate /= div; sys_clk_get_rate()
202 return clk->parent->rate / div; sys_clk_get_rate()
238 u32 div = bfin_read32(CGU0_DIV); sys_clk_set_rate() local
239 div = (div & clk->mask) >> clk->shift; sys_clk_set_rate()
246 div = (clk_get_rate(clk) * div) / rate; sys_clk_set_rate()
250 clk_reg_write_mask(CGU0_DIV, div << clk->shift, sys_clk_set_rate()
/linux-4.1.27/arch/x86/realmode/rm/
H A Dwakemain.c17 u16 div = 1193181/hz; beep() local
21 outb(div, 0x42); /* LSB of counter */ beep()
23 outb(div >> 8, 0x42); /* MSB of counter */ beep()
/linux-4.1.27/include/linux/platform_data/
H A Dhwmon-s3c.h20 * @div: Divide the value from the ADC by this.
23 * hwmon expects (mV) by result = (value_read * @mult) / @div.
28 unsigned int div; member in struct:s3c_hwmon_chcfg
/linux-4.1.27/arch/powerpc/boot/
H A Dcuboot-52xx.c27 int div; platform_fixups() local
50 div = in_8(reg + 0x204) & 0x0020 ? 8 : 4; platform_fixups()
51 sysfreq = bd.bi_busfreq * div; platform_fixups()
H A Dcuboot-acadia.c49 unsigned long div; /* total divisor udiv * bdiv */ get_clocks() local
130 div = plloutb / (16 * baud); /* total divisor */ get_clocks()
139 ibdiv = div / i; get_clocks()
141 idiff = (est > div) ? (est-div) : (div-est); get_clocks()
H A Dmpc8xx.c27 int mfi, mfn, mfd, pdf, div; mpc885_get_clock() local
46 div = (plprcr >> 20) & 3; mpc885_get_clock()
/linux-4.1.27/sound/soc/sh/rcar/
H A Dadg.c130 int idx, sel, div, step, ret; rsnd_adg_set_convert_clk_gen2() local
151 for (div = 2; div <= 98304; div += step) { rsnd_adg_set_convert_clk_gen2()
152 diff = abs(src_rate - sel_rate[sel] / div); rsnd_adg_set_convert_clk_gen2()
166 div += step; rsnd_adg_set_convert_clk_gen2()
206 int idx, sel, div, shift; rsnd_adg_set_convert_clk_gen1() local
218 /* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */ rsnd_adg_set_convert_clk_gen1()
220 for (div = 128, idx = 0; rsnd_adg_set_convert_clk_gen1()
221 div <= 2048; rsnd_adg_set_convert_clk_gen1()
222 div *= 2, idx++) { rsnd_adg_set_convert_clk_gen1()
223 if (src_rate == sel_rate[sel] / div) { rsnd_adg_set_convert_clk_gen1()
/linux-4.1.27/drivers/gpu/ipu-v3/
H A Dipu-di.c278 struct ipu_di_signal_cfg *sig, int div) ipu_di_sync_config_noninterlaced()
293 .offset_count = div * sig->v_to_h_sync, ipu_di_sync_config_noninterlaced()
353 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ ipu_di_sync_config_noninterlaced()
379 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ ipu_di_sync_config_noninterlaced()
438 unsigned div; ipu_di_config_clock() local
443 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); ipu_di_config_clock()
444 div = clamp(div, 1U, 255U); ipu_di_config_clock()
446 clkgen0 = div << 4; ipu_di_config_clock()
457 unsigned div, error; ipu_di_config_clock() local
460 div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock); ipu_di_config_clock()
461 div = clamp(div, 1U, 255U); ipu_di_config_clock()
462 rate = clkrate / div; ipu_di_config_clock()
467 rate, div, (signed)(error - 1000) / 10, error % 10); ipu_di_config_clock()
473 clkgen0 = div << 4; ipu_di_config_clock()
476 unsigned div; ipu_di_config_clock() local
483 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); ipu_di_config_clock()
484 div = clamp(div, 1U, 255U); ipu_di_config_clock()
486 clkgen0 = div << 4; ipu_di_config_clock()
550 u32 div; ipu_di_init_sync_panel() local
567 div = ipu_di_read(di, DI_BS_CLKGEN0) & 0xfff; ipu_di_init_sync_panel()
568 div = div / 16; /* Now divider is integer portion */ ipu_di_init_sync_panel()
572 ipu_di_write(di, (div << 16), DI_BS_CLKGEN1); ipu_di_init_sync_panel()
574 ipu_di_data_wave_config(di, SYNC_WAVE, div - 1, div - 1); ipu_di_init_sync_panel()
575 ipu_di_data_pin_config(di, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); ipu_di_init_sync_panel()
595 ipu_di_sync_config_noninterlaced(di, sig, div); ipu_di_init_sync_panel()
277 ipu_di_sync_config_noninterlaced(struct ipu_di *di, struct ipu_di_signal_cfg *sig, int div) ipu_di_sync_config_noninterlaced() argument
/linux-4.1.27/arch/m68k/math-emu/
H A Dmulti_arith.h131 #define fp_div64(quot, rem, srch, srcl, div) \
133 : "dm" (div), "1" (srch), "0" (srcl))
182 struct fp_ext *div) fp_dividemant()
190 /* the algorithm below requires dest to be smaller than div, fp_dividemant()
192 if (src->mant.m64 >= div->mant.m64) { fp_dividemant()
193 fp_sub64(src->mant, div->mant); fp_dividemant()
209 dummy = div->mant.m32[1] / div->mant.m32[0] + 1; fp_dividemant()
215 if (src->mant.m32[0] == div->mant.m32[0]) { fp_dividemant()
216 fp_div64(first, rem, 0, src->mant.m32[1], div->mant.m32[0]); fp_dividemant()
221 fp_div64(first, rem, src->mant.m32[0], src->mant.m32[1], div->mant.m32[0]); fp_dividemant()
226 fp_mul64(tmp.m32[0], tmp.m32[1], div->mant.m32[0], first - *mantp); fp_dividemant()
230 fp_mul64(tmp64.m32[0], tmp64.m32[1], *mantp, div->mant.m32[1]); fp_dividemant()
236 while (!fp_sub96c(tmp, 0, div->mant.m32[0], div->mant.m32[1])) { fp_dividemant()
181 fp_dividemant(union fp_mant128 *dest, struct fp_ext *src, struct fp_ext *div) fp_dividemant() argument
/linux-4.1.27/drivers/clk/st/
H A Dclk-flexgen.c106 unsigned long div; flexgen_round_rate() local
108 /* Round div according to exact prate and wished rate */ flexgen_round_rate()
109 div = clk_best_div(*prate, rate); flexgen_round_rate()
112 *prate = rate * div; flexgen_round_rate()
116 return *prate / div; flexgen_round_rate()
141 unsigned long div = 0; flexgen_set_rate() local
147 div = clk_best_div(parent_rate, rate); flexgen_set_rate()
151 * should be used for div <= 64. The other way round can flexgen_set_rate()
155 if (div <= 64) { flexgen_set_rate()
157 ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div); flexgen_set_rate()
160 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div); flexgen_set_rate()
H A Dclkgen-mux.c61 struct clk_divider div[NUM_INPUTS]; member in struct:clkgena_divmux
175 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw; clkgena_divmux_recalc_rate()
186 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw; clkgena_divmux_set_rate()
197 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw; clkgena_divmux_round_rate()
263 genamux->div[i].width = divider_width; clk_register_genamux()
264 genamux->div[i].reg = divbase + (idx * sizeof(u32)); clk_register_genamux()
465 { .val = 0, .div = 1 },
466 { .val = 1, .div = 16 },
467 { .div = 0 },
739 struct clk_divider *div; st_of_clkgen_vcc_setup() local
756 div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL); st_of_clkgen_vcc_setup()
757 if (!div) { st_of_clkgen_vcc_setup()
765 kfree(div); st_of_clkgen_vcc_setup()
774 div->reg = reg + VCC_DIV_OFFSET; st_of_clkgen_vcc_setup()
775 div->shift = 2 * i; st_of_clkgen_vcc_setup()
776 div->width = 2; st_of_clkgen_vcc_setup()
777 div->flags = CLK_DIVIDER_POWER_OF_TWO | st_of_clkgen_vcc_setup()
787 &div->hw, &clk_divider_ops, st_of_clkgen_vcc_setup()
792 kfree(div); st_of_clkgen_vcc_setup()
/linux-4.1.27/drivers/cpufreq/
H A Dcpufreq-nforce2.c23 #define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div)
69 unsigned char mul, div; nforce2_calc_fsb() local
72 div = pll & 0xff; nforce2_calc_fsb()
74 if (div > 0) nforce2_calc_fsb()
75 return NFORCE2_XTAL * mul / div; nforce2_calc_fsb()
89 unsigned char mul = 0, div = 0; nforce2_calc_pll() local
93 while (((mul == 0) || (div == 0)) && (tried <= 3)) { nforce2_calc_pll()
99 div = xdiv; nforce2_calc_pll()
104 if ((mul == 0) || (div == 0)) nforce2_calc_pll()
107 return NFORCE2_PLL(mul, div); nforce2_calc_pll()
H A Ds3c2440-cpufreq.c86 s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv); s3c2440_cpufreq_calcdivs()
204 int div; run_freq_for() local
206 for (div = *divs; div > 0; div = *divs++) { run_freq_for()
207 freq = fclk / div; run_freq_for()
209 if (freq > max_hclk && div != 1) run_freq_for()
/linux-4.1.27/arch/m68k/atari/
H A Ddebug.c219 int clksrc, clkmode, div, reg3, reg5; atari_init_scc_port() local
229 div = div_table[baud]; atari_init_scc_port()
236 div = 0; atari_init_scc_port()
253 SCC_WRITE(12, div); /* BRG value */ atari_init_scc_port()
256 SCC_WRITE(14, brgsrc_table[baud] | (div ? 1 : 0)); atari_init_scc_port()
269 int div; atari_init_midi_port() local
276 div = ACIA_DIV64; /* really 7812.5 bps */ atari_init_midi_port()
278 div = ACIA_DIV1; /* really 500 kbps (does that work??) */ atari_init_midi_port()
280 div = ACIA_DIV16; /* 31250 bps, standard for MIDI */ atari_init_midi_port()
283 acia.mid_ctrl = div | csize | parity | atari_init_midi_port()
/linux-4.1.27/arch/mips/ralink/
H A Dmt7620.c231 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) mt7620_calc_rate() argument
237 do_div(t, div); mt7620_calc_rate()
275 u32 div; mt7620_get_cpu_pll_rate() local
290 div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & mt7620_get_cpu_pll_rate()
293 WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider)); mt7620_get_cpu_pll_rate()
295 return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]); mt7620_get_cpu_pll_rate()
318 u32 div; mt7620_get_cpu_rate() local
323 div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & mt7620_get_cpu_rate()
326 return mt7620_calc_rate(pll_rate, mul, div); mt7620_get_cpu_rate()
351 u32 div; mt7620_get_sys_rate() local
361 div = mt7620_ocp_dividers[ocp_ratio]; mt7620_get_sys_rate()
362 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) mt7620_get_sys_rate()
365 return cpu_rate / div; mt7620_get_sys_rate()
/linux-4.1.27/drivers/media/pci/ttpci/
H A Dbudget.c212 u32 div = (c->frequency + 479500) / 125; alps_bsrv2_tuner_set_params() local
226 buf[0] = (div >> 8) & 0x7f; alps_bsrv2_tuner_set_params()
227 buf[1] = div & 0xff; alps_bsrv2_tuner_set_params()
228 buf[2] = ((div & 0x18000) >> 10) | 0x95; alps_bsrv2_tuner_set_params()
251 u32 div; alps_tdbe2_tuner_set_params() local
255 div = (c->frequency + 35937500 + 31250) / 62500; alps_tdbe2_tuner_set_params()
257 data[0] = (div >> 8) & 0x7f; alps_tdbe2_tuner_set_params()
258 data[1] = div & 0xff; alps_tdbe2_tuner_set_params()
259 data[2] = 0x85 | ((div >> 10) & 0x60); alps_tdbe2_tuner_set_params()
280 u32 div; grundig_29504_401_tuner_set_params() local
290 div = (36125000 + c->frequency) / 166666; grundig_29504_401_tuner_set_params()
312 data[0] = (div >> 8) & 0x7f; grundig_29504_401_tuner_set_params()
313 data[1] = div & 0xff; grundig_29504_401_tuner_set_params()
314 data[2] = ((div >> 10) & 0x60) | cfg; grundig_29504_401_tuner_set_params()
337 u32 div; grundig_29504_451_tuner_set_params() local
341 div = c->frequency / 125; grundig_29504_451_tuner_set_params()
342 data[0] = (div >> 8) & 0x7f; grundig_29504_451_tuner_set_params()
343 data[1] = div & 0xff; grundig_29504_451_tuner_set_params()
361 u32 div; s5h1420_tuner_set_params() local
365 div = c->frequency / 1000; s5h1420_tuner_set_params()
366 data[0] = (div >> 8) & 0x7f; s5h1420_tuner_set_params()
367 data[1] = div & 0xff; s5h1420_tuner_set_params()
370 if (div < 1450) s5h1420_tuner_set_params()
372 else if (div < 1850) s5h1420_tuner_set_params()
374 else if (div < 2000) s5h1420_tuner_set_params()
/linux-4.1.27/drivers/spi/
H A Dspi-sun4i.c59 #define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
61 #define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
172 unsigned int mclk_rate, div, timeout; sun4i_spi_transfer_one() local
251 div = mclk_rate / (2 * spi->max_speed_hz); sun4i_spi_transfer_one()
252 if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { sun4i_spi_transfer_one()
253 if (div > 0) sun4i_spi_transfer_one()
254 div--; sun4i_spi_transfer_one()
256 reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; sun4i_spi_transfer_one()
258 div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz); sun4i_spi_transfer_one()
259 reg = SUN4I_CLK_CTL_CDR1(div); sun4i_spi_transfer_one()
H A Dspi-sun6i.c64 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
66 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
162 unsigned int mclk_rate, div, timeout; sun6i_spi_transfer_one() local
239 div = mclk_rate / (2 * spi->max_speed_hz); sun6i_spi_transfer_one()
240 if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { sun6i_spi_transfer_one()
241 if (div > 0) sun6i_spi_transfer_one()
242 div--; sun6i_spi_transfer_one()
244 reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS; sun6i_spi_transfer_one()
246 div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz); sun6i_spi_transfer_one()
247 reg = SUN6I_CLK_CTL_CDR1(div); sun6i_spi_transfer_one()
/linux-4.1.27/arch/microblaze/lib/
H A Dmodsi3.S35 addik r30, r0, 0 /* clear div */
54 add r30, r30, r30 /* shift in the '1' into div */
62 or r3, r0, r0 /* set result to 0 [both mod as well as div are 0] */
H A Ddivsi3.S32 addik r3, r0, 0 /* clear div */
54 add r3, r3, r3 /* shift in the '1' into div */
H A Dumodsi3.S25 addik r3, r0, 0 /* clear div */
70 add r30, r30, r30 /* shift in the '1' into div */
/linux-4.1.27/sound/soc/codecs/
H A Drl6231.c27 int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL; rl6231_calc_dmic_clk() local
31 for (i = 0; i < ARRAY_SIZE(div); i++) { rl6231_calc_dmic_clk()
32 bound = div[i] * 3000000; rl6231_calc_dmic_clk()
H A Dadau17x1.c309 unsigned int val, div, dsp_div; adau17x1_hw_params() local
323 div = 0; adau17x1_hw_params()
327 div = 1; adau17x1_hw_params()
331 div = 2; adau17x1_hw_params()
335 div = 3; adau17x1_hw_params()
339 div = 4; adau17x1_hw_params()
343 div = 5; adau17x1_hw_params()
347 div = 6; adau17x1_hw_params()
355 ADAU17X1_CONVERTER0_CONVSR_MASK, div); adau17x1_hw_params()
357 regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div); adau17x1_hw_params()
394 unsigned int div; adau17x1_set_dai_pll() local
404 div = 0; adau17x1_set_dai_pll()
407 div = DIV_ROUND_UP(freq_in, 13500000); adau17x1_set_dai_pll()
408 freq_in /= div; adau17x1_set_dai_pll()
414 div--; adau17x1_set_dai_pll()
419 div = 0; adau17x1_set_dai_pll()
421 if (n > 0xffff || m > 0xffff || div > 3 || r > 8 || r < 2) adau17x1_set_dai_pll()
429 adau->pll_regs[4] = (r << 3) | (div << 1); adau17x1_set_dai_pll()
H A Dwm8350.c790 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div) wm8350_set_clkdiv() argument
799 snd_soc_write(codec, WM8350_ADC_DIVIDER, val | div); wm8350_set_clkdiv()
804 snd_soc_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div); wm8350_set_clkdiv()
809 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div); wm8350_set_clkdiv()
814 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div); wm8350_set_clkdiv()
819 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div); wm8350_set_clkdiv()
824 snd_soc_write(codec, WM8350_DAC_LR_RATE, val | div); wm8350_set_clkdiv()
829 snd_soc_write(codec, WM8350_ADC_LR_RATE, val | div); wm8350_set_clkdiv()
966 int div; /* FLL_OUTDIV */ member in struct:_fll_div
983 fll_div->div = 0x4; fll_factors()
985 fll_div->div = 0x3; fll_factors()
987 fll_div->div = 0x2; fll_factors()
989 fll_div->div = 0x1; fll_factors()
1000 t1 = output * (1 << (fll_div->div + 1)); fll_factors()
1049 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d", wm8350_set_fll()
1050 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div, wm8350_set_fll()
1057 fll_1 | (fll_div.div << 8) | 0x50); wm8350_set_fll()
/linux-4.1.27/arch/s390/kernel/
H A Dvtime.c90 u64 delta, mult, div; do_account_vtime() local
94 mult = div = 0; do_account_vtime()
98 div += (i + 1) * delta; do_account_vtime()
103 __this_cpu_write(mt_scaling_div, div); do_account_vtime()
123 u64 div = __this_cpu_read(mt_scaling_div); do_account_vtime() local
125 user_scaled = (user_scaled * mult) / div; do_account_vtime()
126 system_scaled = (system_scaled * mult) / div; do_account_vtime()
184 u64 div = __this_cpu_read(mt_scaling_div); vtime_account_irq_enter() local
186 system_scaled = (system_scaled * mult) / div; vtime_account_irq_enter()
/linux-4.1.27/arch/openrisc/
H A DMakefile36 KBUILD_CFLAGS += $(call cc-option,-mhard-div)
38 KBUILD_CFLAGS += $(call cc-option,-msoft-div)
/linux-4.1.27/sound/drivers/pcsp/
H A Dpcsp.h41 #define PCSP_CALC_NS(div) ({ \
42 u64 __val = 1000000000ULL * (div); \
H A Dpcsp.c47 int div, min_div, order; snd_pcsp_create() local
71 div = MAX_DIV / min_div; snd_pcsp_create()
72 order = fls(div) - 1; snd_pcsp_create()
/linux-4.1.27/arch/arm/mach-lpc32xx/
H A Dclock.c917 u32 div, rate, oldclk; mmc_get_rate() local
923 div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); mmc_get_rate()
930 div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf); mmc_get_rate()
932 if (!div) mmc_get_rate()
933 div = 1; mmc_get_rate()
935 return rate / div; mmc_get_rate()
940 unsigned long div, prate; mmc_round_rate() local
948 div = prate / rate; mmc_round_rate()
949 if (div > 0xf) mmc_round_rate()
950 div = 0xf; mmc_round_rate()
952 return prate / div; mmc_round_rate()
958 unsigned long prate, div, crate = mmc_round_rate(clk, rate); mmc_set_rate() local
962 div = prate / crate; mmc_set_rate()
967 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div) | mmc_set_rate()
986 u32 tmp, div, rate, oldclk; clcd_get_rate() local
1001 div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22); clcd_get_rate()
1002 tmp = rate / (2 + div); clcd_get_rate()
1009 u32 tmp, prate, div, oldclk; clcd_set_rate() local
1021 div = prate / rate; clcd_set_rate()
1022 if (div >= 2) { clcd_set_rate()
1023 div -= 2; clcd_set_rate()
1028 tmp |= (div & 0x1F); clcd_set_rate()
1029 tmp |= (((div >> 5) & 0x1F) << 27); clcd_set_rate()
1040 u32 prate, div; clcd_round_rate() local
1047 div = prate / rate; clcd_round_rate()
1048 if (div > 0x3ff) clcd_round_rate()
1049 div = 0x3ff; clcd_round_rate()
1051 rate = prate / div; clcd_round_rate()
/linux-4.1.27/drivers/iio/adc/
H A Dxilinx-xadc-core.c347 unsigned int div; xadc_zynq_setup() local
362 div = 2; xadc_zynq_setup()
364 div = pcap_rate / tck_rate; xadc_zynq_setup()
365 if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX) xadc_zynq_setup()
366 div++; xadc_zynq_setup()
369 if (div <= 3) xadc_zynq_setup()
371 else if (div <= 7) xadc_zynq_setup()
373 else if (div <= 15) xadc_zynq_setup()
391 unsigned int div; xadc_zynq_get_dclk_rate() local
398 div = 4; xadc_zynq_get_dclk_rate()
401 div = 8; xadc_zynq_get_dclk_rate()
404 div = 16; xadc_zynq_get_dclk_rate()
407 div = 2; xadc_zynq_get_dclk_rate()
411 return clk_get_rate(xadc->clk) / div; xadc_zynq_get_dclk_rate()
833 unsigned int div; xadc_read_raw() local
889 div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET; xadc_read_raw()
890 if (div < 2) xadc_read_raw()
891 div = 2; xadc_read_raw()
893 *val = xadc_get_dclk_rate(xadc) / div / 26; xadc_read_raw()
906 unsigned int div; xadc_write_raw() local
928 div = clk_rate / val; xadc_write_raw()
929 if (clk_rate / div / 26 > 150000) xadc_write_raw()
930 div++; xadc_write_raw()
931 if (div < 2) xadc_write_raw()
932 div = 2; xadc_write_raw()
933 else if (div > 0xff) xadc_write_raw()
934 div = 0xff; xadc_write_raw()
937 div << XADC_CONF2_DIV_OFFSET); xadc_write_raw()
/linux-4.1.27/drivers/mfd/
H A Dmcp-core.c58 * @div: SIB clock divisor
61 * sample rate is SIBCLOCK/div.
63 void mcp_set_telecom_divisor(struct mcp *mcp, unsigned int div) mcp_set_telecom_divisor() argument
68 mcp->ops->set_telecom_divisor(mcp, div); mcp_set_telecom_divisor()
76 * @div: SIB clock divisor
80 void mcp_set_audio_divisor(struct mcp *mcp, unsigned int div) mcp_set_audio_divisor() argument
85 mcp->ops->set_audio_divisor(mcp, div); mcp_set_audio_divisor()
H A Ddb8500-prcmu.c719 * @div: The divider to be applied.
722 * @div should be in the range [1,63] to request a configuration, or 0 to
725 int prcmu_config_clkout(u8 clkout, u8 source, u8 div) prcmu_config_clkout() argument
736 BUG_ON(div > 63); prcmu_config_clkout()
739 if (!div && !requests[clkout]) prcmu_config_clkout()
747 (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); prcmu_config_clkout()
754 (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); prcmu_config_clkout()
763 if (div) { prcmu_config_clkout()
776 requests[clkout] += (div ? 1 : -1); prcmu_config_clkout()
981 u32 div; request_even_slower_clocks() local
984 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); request_even_slower_clocks()
986 if ((div <= 1) || (div > 15)) { request_even_slower_clocks()
988 div, __func__); request_even_slower_clocks()
991 div <<= 1; request_even_slower_clocks()
993 if (div <= 2) request_even_slower_clocks()
995 div >>= 1; request_even_slower_clocks()
998 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); request_even_slower_clocks()
1498 u32 div = 1; pll_rate() local
1507 div *= d; pll_rate()
1511 div *= d; pll_rate()
1514 div *= 2; pll_rate()
1521 div *= 2; pll_rate()
1523 (void)do_div(rate, div); pll_rate()
1601 u32 div = 1; dsiclk_rate() local
1613 div *= 2; dsiclk_rate()
1615 div *= 2; dsiclk_rate()
1618 PLL_RAW) / div; dsiclk_rate()
1626 u32 div; dsiescclk_rate() local
1628 div = readl(PRCM_DSITVCLK_DIV); dsiescclk_rate()
1629 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); dsiescclk_rate()
1630 return clock_rate(PRCMU_TVCLK) / max((u32)1, div); dsiescclk_rate()
1677 u32 div; clock_divider() local
1679 div = (src_rate / rate); clock_divider()
1680 if (div == 0) clock_divider()
1682 if (rate < (src_rate / div)) clock_divider()
1683 div++; clock_divider()
1684 return div; clock_divider()
1690 u32 div; round_clock_rate() local
1697 div = clock_divider(src_rate, rate); round_clock_rate()
1700 if (div > 2) round_clock_rate()
1701 div = 2; round_clock_rate()
1703 div = 1; round_clock_rate()
1705 } else if ((clock == PRCMU_SGACLK) && (div == 3)) { round_clock_rate()
1712 rounded_rate = (src_rate / min(div, (u32)31)); round_clock_rate()
1787 u32 div; round_dsiclk_rate() local
1793 div = clock_divider(src_rate, rate); round_dsiclk_rate()
1794 rounded_rate = (src_rate / ((div > 2) ? 4 : div)); round_dsiclk_rate()
1801 u32 div; round_dsiescclk_rate() local
1806 div = clock_divider(src_rate, rate); round_dsiescclk_rate()
1807 rounded_rate = (src_rate / min(div, (u32)255)); round_dsiescclk_rate()
1831 u32 div; set_clock_rate() local
1844 div = clock_divider(src_rate, rate); set_clock_rate()
1847 if (div > 1) set_clock_rate()
1855 if (div == 3) { set_clock_rate()
1861 div = 0; set_clock_rate()
1864 val |= min(div, (u32)31); set_clock_rate()
1867 val |= min(div, (u32)31); set_clock_rate()
1945 u32 div; set_dsiclk_rate() local
1947 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, set_dsiclk_rate()
1950 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : set_dsiclk_rate()
1951 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : set_dsiclk_rate()
1963 u32 div; set_dsiescclk_rate() local
1965 div = clock_divider(clock_rate(PRCMU_TVCLK), rate); set_dsiescclk_rate()
1968 val |= (min(div, (u32)255) << dsiescclk[n].div_shift); set_dsiescclk_rate()
H A Drtsx_usb.c388 static u8 revise_ssc_depth(u8 ssc_depth, u8 div) revise_ssc_depth() argument
390 if (div > CLK_DIV_1) { revise_ssc_depth()
391 if (ssc_depth > div - 1) revise_ssc_depth()
392 ssc_depth -= (div - 1); revise_ssc_depth()
404 u8 n, clk_divider, mcu_cnt, div; rtsx_usb_switch_clock() local
437 /* Converting clock value into internal settings: n and div */ rtsx_usb_switch_clock()
448 div = CLK_DIV_1; rtsx_usb_switch_clock()
449 while (n < MIN_DIV_N && div < CLK_DIV_4) { rtsx_usb_switch_clock()
451 div++; rtsx_usb_switch_clock()
453 dev_dbg(&ucr->pusb_intf->dev, "n = %d, div = %d\n", n, div); rtsx_usb_switch_clock()
458 ssc_depth = revise_ssc_depth(ssc_depth, div); rtsx_usb_switch_clock()
464 0x3F, (div << 4) | mcu_cnt); rtsx_usb_switch_clock()
/linux-4.1.27/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c50 /* intermediates in div+gate combos or fractional dividers */
64 /* intermediates for the mux+gate+div+mux MCLK generation */
228 int mul, int div) mpc512x_clk_factor()
234 mul, div); mpc512x_clk_factor()
366 { .val = 2, .div = 2, },
367 { .val = 3, .div = 3, },
368 { .val = 4, .div = 4, },
369 { .val = 6, .div = 6, },
370 { .div = 0, },
375 { .val = 1, .div = 1, },
376 { .val = 2, .div = 2, },
377 { .val = 3, .div = 3, },
378 { .val = 4, .div = 4, },
379 { .div = 0, },
418 * SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div
428 /* fetch mul/div factors from the hardware */ mpc512x_clk_setup_ref_clock()
598 u32 __iomem *mccr_reg; /* MCLK control register (mux, en, div) */ mpc512x_clk_setup_mclk()
599 int div; mpc512x_clk_setup_mclk() local
650 div = clk_get_rate(clks[MPC512x_CLK_SYS]); mpc512x_clk_setup_mclk()
651 div /= clk_get_rate(clks[MPC512x_CLK_IPS]); mpc512x_clk_setup_mclk()
653 out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17)); mpc512x_clk_setup_mclk()
654 out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17)); mpc512x_clk_setup_mclk()
707 int mul, div; mpc512x_clk_setup_clock_tree() local
718 * most one of a mux, div, and gate each into one 'struct clk' mpc512x_clk_setup_clock_tree()
779 div = 2; /* compensate for the fractional factor */ mpc512x_clk_setup_clock_tree()
780 clks[MPC512x_CLK_E300] = mpc512x_clk_factor("e300", "csb", mul, div); mpc512x_clk_setup_clock_tree()
226 mpc512x_clk_factor( const char *name, const char *parent_name, int mul, int div) mpc512x_clk_factor() argument
/linux-4.1.27/drivers/media/pci/mantis/
H A Dmantis_vp1033.c93 u32 div; lgtdqcs001f_tuner_set() local
98 div = p->frequency / 250; lgtdqcs001f_tuner_set()
100 buf[0] = (div >> 8) & 0x7f; lgtdqcs001f_tuner_set()
101 buf[1] = div & 0xff; lgtdqcs001f_tuner_set()
H A Dmantis_vp2033.c81 u32 div = (p->frequency + CU1216_IF + TUNER_MUL / 2) / TUNER_MUL; tda1002x_cu1216_tuner_set() local
83 buf[0] = (div >> 8) & 0x7f; tda1002x_cu1216_tuner_set()
84 buf[1] = div & 0xff; tda1002x_cu1216_tuner_set()
H A Dmantis_vp2040.c63 u32 div = (p->frequency + CU1216_IF + TUNER_MUL / 2) / TUNER_MUL; tda1002x_cu1216_tuner_set() local
65 buf[0] = (div >> 8) & 0x7f; tda1002x_cu1216_tuner_set()
66 buf[1] = div & 0xff; tda1002x_cu1216_tuner_set()
/linux-4.1.27/drivers/media/platform/s3c-camif/
H A Dcamif-regs.c235 unsigned int div, rem; camif_get_dma_burst() local
240 for (div = 16; div >= 2; div /= 2) { camif_get_dma_burst()
241 if (nwords < div) camif_get_dma_burst()
244 rem = nwords & (div - 1); camif_get_dma_burst()
246 *mburst = div; camif_get_dma_burst()
247 *rburst = div; camif_get_dma_burst()
250 if (rem == div / 2 || rem == div / 4) { camif_get_dma_burst()
251 *mburst = div; camif_get_dma_burst()
/linux-4.1.27/drivers/sh/clk/
H A Dcore.c45 unsigned long mult, div; clk_rate_table_build() local
52 div = 1; clk_rate_table_build()
56 div = src_table->divisors[i]; clk_rate_table_build()
61 if (!div || !mult || (bitmap && !test_bit(i, bitmap))) clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; clk_rate_table_build()
563 unsigned long error = ULONG_MAX, freq_high, freq_low, div; clk_round_parent() local
613 div = freq->frequency / target; clk_round_parent()
614 freq_high = freq->frequency / div; clk_round_parent()
615 freq_low = freq->frequency / (div + 1); clk_round_parent()
632 freq->frequency, div, freq_high, div + 1, freq_low, clk_round_parent()
/linux-4.1.27/drivers/gpu/drm/imx/
H A Dimx-tve.c320 int div = 1; imx_tve_encoder_mode_set() local
332 div = 2; imx_tve_encoder_mode_set()
333 clk_set_rate(tve->di_clk, rounded_rate / div); imx_tve_encoder_mode_set()
429 unsigned long div; clk_tve_di_round_rate() local
431 div = *prate / rate; clk_tve_di_round_rate()
432 if (div >= 4) clk_tve_di_round_rate()
434 else if (div >= 2) clk_tve_di_round_rate()
443 unsigned long div; clk_tve_di_set_rate() local
447 div = parent_rate / rate; clk_tve_di_set_rate()
448 if (div >= 4) clk_tve_di_set_rate()
450 else if (div >= 2) clk_tve_di_set_rate()
/linux-4.1.27/arch/arm/mach-s3c24xx/
H A Diotiming-s3c2410.c108 unsigned int div = to_div(cyc, hclk_tns); calc_0124() local
111 s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n", calc_0124()
112 __func__, cyc, hclk_tns, shift, div); calc_0124()
114 switch (div) { calc_0124()
156 unsigned int div = to_div(cyc, hclk_tns); calc_tacc() local
159 s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n", calc_tacc()
160 __func__, cyc, nwait_en, hclk_tns, div); calc_tacc()
163 if (nwait_en && div < 4) calc_tacc()
164 div = 4; calc_tacc()
166 switch (div) { calc_tacc()
175 val = div - 1; calc_tacc()
/linux-4.1.27/drivers/clk/pxa/
H A Dclk-pxa.h87 .lp = { .mult = _mult_lp, .div = _div_lp }, \
88 .hp = { .mult = _mult_hp, .div = _div_hp }, \
/linux-4.1.27/arch/nios2/
H A DMakefile28 KBUILD_CFLAGS += $(if $(CONFIG_NIOS2_HW_DIV_SUPPORT),-mhw-div,-mno-hw-div)
/linux-4.1.27/include/linux/amba/
H A Dkmi.h74 * div = (ref / 8MHz) - 1; 0 <= div <= 15
/linux-4.1.27/include/linux/mfd/
H A Datmel-hlcdc.h55 #define ATMEL_HLCDC_CLKDIV(div) ((div - 2) << ATMEL_HLCDC_CLKDIV_SHFT)
H A Ducb1x00.h232 * @div: SIB clock divisor
234 static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div) ucb1x00_set_audio_divisor() argument
236 mcp_set_audio_divisor(ucb->mcp, div); ucb1x00_set_audio_divisor()
242 * @div: SIB clock divisor
244 static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div) ucb1x00_set_telecom_divisor() argument
246 mcp_set_telecom_divisor(ucb->mcp, div); ucb1x00_set_telecom_divisor()
/linux-4.1.27/drivers/media/pci/bt8xx/
H A Ddvb-bt8xx.c157 u32 div; thomson_dtt7579_tuner_calc_regs() local
164 div = (((c->frequency + 83333) * 3) / 500000) + IF_FREQUENCYx6; thomson_dtt7579_tuner_calc_regs()
181 pllbuf[1] = div >> 8; thomson_dtt7579_tuner_calc_regs()
182 pllbuf[2] = div & 0xff; thomson_dtt7579_tuner_calc_regs()
279 u32 div; microtune_mt7202dtf_tuner_set_params() local
282 div = (36000000 + c->frequency + 83333) / 166666; microtune_mt7202dtf_tuner_set_params()
303 data[0] = (div >> 8) & 0x7f; microtune_mt7202dtf_tuner_set_params()
304 data[1] = div & 0xff; microtune_mt7202dtf_tuner_set_params()
305 data[2] = ((div >> 10) & 0x60) | cfg; microtune_mt7202dtf_tuner_set_params()
311 return (div * 166666 - 36000000); microtune_mt7202dtf_tuner_set_params()
352 u32 div; advbt771_samsung_tdtc9251dh0_tuner_calc_regs() local
358 div = (((c->frequency + 83333) * 3) / 500000) + IF_FREQUENCYx6; advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
399 pllbuf[1] = div >> 8; advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
400 pllbuf[2] = div & 0xff; advbt771_samsung_tdtc9251dh0_tuner_calc_regs()
474 u32 div; vp3021_alps_tded4_tuner_set_params() local
477 div = (c->frequency + 36166667) / 166667; vp3021_alps_tded4_tuner_set_params()
479 buf[0] = (div >> 8) & 0x7F; vp3021_alps_tded4_tuner_set_params()
480 buf[1] = div & 0xFF; vp3021_alps_tded4_tuner_set_params()
524 u32 div; digitv_alps_tded4_tuner_calc_regs() local
530 div = (((c->frequency + 83333) * 3) / 500000) + IF_FREQUENCYx6; digitv_alps_tded4_tuner_calc_regs()
533 pllbuf[1] = (div >> 8) & 0x7F; digitv_alps_tded4_tuner_calc_regs()
534 pllbuf[2] = div & 0xFF; digitv_alps_tded4_tuner_calc_regs()
537 dprintk("frequency %u, div %u\n", c->frequency, div); digitv_alps_tded4_tuner_calc_regs()
/linux-4.1.27/drivers/net/wireless/iwlegacy/
H A D3945-debug.c418 struct iwl39_stats_div *div, *accum_div, *delta_div, *max_div; il3945_ucode_general_stats_read() local
436 div = &il->_3945.stats.general.div; il3945_ucode_general_stats_read()
443 accum_div = &il->_3945.accum_stats.general.div; il3945_ucode_general_stats_read()
444 delta_div = &il->_3945.delta_stats.general.div; il3945_ucode_general_stats_read()
445 max_div = &il->_3945.max_delta.general.div; il3945_ucode_general_stats_read()
485 le32_to_cpu(div->tx_on_a), accum_div->tx_on_a, il3945_ucode_general_stats_read()
490 le32_to_cpu(div->tx_on_b), accum_div->tx_on_b, il3945_ucode_general_stats_read()
495 le32_to_cpu(div->exec_time), accum_div->exec_time, il3945_ucode_general_stats_read()
500 le32_to_cpu(div->probe_time), accum_div->probe_time, il3945_ucode_general_stats_read()
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-mpc.c206 const struct mpc_i2c_divider *div = NULL; mpc_i2c_get_fdr_52xx() local
212 /* see below - default fdr = 0x3f -> div = 2048 */ mpc_i2c_get_fdr_52xx()
225 div = &mpc_i2c_dividers_52xx[i]; mpc_i2c_get_fdr_52xx()
227 if (div->fdr & 0xc0 && pvr == 0x80822011) mpc_i2c_get_fdr_52xx()
229 if (div->divider >= divider) mpc_i2c_get_fdr_52xx()
233 *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider; mpc_i2c_get_fdr_52xx()
234 return (int)div->fdr; mpc_i2c_get_fdr_52xx()
381 const struct mpc_i2c_divider *div = NULL; mpc_i2c_get_fdr_8xxx() local
386 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */ mpc_i2c_get_fdr_8xxx()
407 div = &mpc_i2c_dividers_8xxx[i]; mpc_i2c_get_fdr_8xxx()
408 if (div->divider >= divider) mpc_i2c_get_fdr_8xxx()
412 *real_clk = fsl_get_sys_freq() / prescaler / div->divider; mpc_i2c_get_fdr_8xxx()
413 return div ? (int)div->fdr : -EINVAL; mpc_i2c_get_fdr_8xxx()
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dradeon_audio.c556 unsigned long div, mul; radeon_audio_calc_cts() local
563 div = gcd(n, cts); radeon_audio_calc_cts()
565 n /= div; radeon_audio_calc_cts()
566 cts /= div; radeon_audio_calc_cts()
779 unsigned int radeon_audio_decode_dfs_div(unsigned int div) radeon_audio_decode_dfs_div() argument
781 if (div >= 8 && div < 64) radeon_audio_decode_dfs_div()
782 return (div - 8) * 25 + 200; radeon_audio_decode_dfs_div()
783 else if (div >= 64 && div < 96) radeon_audio_decode_dfs_div()
784 return (div - 64) * 50 + 1600; radeon_audio_decode_dfs_div()
785 else if (div >= 96 && div < 128) radeon_audio_decode_dfs_div()
786 return (div - 96) * 100 + 3200; radeon_audio_decode_dfs_div()
H A Ddce6_afmt.c285 unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) & dce6_dp_audio_set_dto() local
288 div = radeon_audio_decode_dfs_div(div); dce6_dp_audio_set_dto()
290 if (div) dce6_dp_audio_set_dto()
291 clock = clock * 100 / div; dce6_dp_audio_set_dto()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgf100.c201 u32 div = min((ref * 2) / freq, (u32)65); calc_div() local
202 if (div < 2) calc_div()
203 div = 2; calc_div()
205 *ddiv = div - 2; calc_div()
206 return (ref * 2) / div; calc_div()
390 { gf100_clk_prog_0 }, /* div programming */ gf100_clk_prog()
391 { gf100_clk_prog_1 }, /* select div mode */ gf100_clk_prog()
H A Dmcp77.c182 calc_P(u32 src, u32 target, int *div) calc_P() argument
185 for (*div = 0; *div <= 7; (*div)++) { calc_P()
187 clk1 = clk0 << (*div ? 1 : 0); calc_P()
195 (*div)--; calc_P()
/linux-4.1.27/arch/cris/arch-v10/kernel/
H A Dfasttimer.c142 unsigned long div; start_timer1() local
145 * T=div*t, div = T/t = delay_us*freq/1000000 start_timer1()
160 div = delay_us * timer_freq_100[freq_index]/10000; start_timer1()
161 if (div < 2) start_timer1()
164 div = 2; start_timer1()
166 if (div > 255) start_timer1()
168 div = 0; /* This means 256, the max the timer takes */ start_timer1()
174 timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = div; start_timer1()
178 D1(printk(KERN_DEBUG "start_timer1 : %d us freq: %i div: %i\n", start_timer1()
179 delay_us, freq_index, div)); start_timer1()
189 IO_FIELD(R_TIMER_CTRL, timerdiv1, div) | start_timer1()
546 seq_printf(m, "div: %i freq: %i delay: %i\n", proc_fasttimer_show()
/linux-4.1.27/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_crtc.c66 int div; atmel_hlcdc_crtc_mode_set_nofb() local
97 div = DIV_ROUND_UP(prate, mode_rate); atmel_hlcdc_crtc_mode_set_nofb()
98 if (div < 2) atmel_hlcdc_crtc_mode_set_nofb()
99 div = 2; atmel_hlcdc_crtc_mode_set_nofb()
101 cfg |= ATMEL_HLCDC_CLKDIV(div); atmel_hlcdc_crtc_mode_set_nofb()
/linux-4.1.27/drivers/thermal/
H A Darmada_thermal.c61 /* Formula coeficients: temp = (b + m * reg) / div */
162 unsigned long m, b, div; armada_get_temp() local
177 div = priv->data->coef_div; armada_get_temp()
180 *temp = ((m * reg) - b) / div; armada_get_temp()
182 *temp = (b - (m * reg)) / div; armada_get_temp()
/linux-4.1.27/drivers/tty/serial/
H A Dmax310x.c489 unsigned int mode = 0, clk = port->uartclk, div = clk / baud; max310x_set_baud() local
492 if (div < 16) max310x_set_baud()
493 div = 16; max310x_set_baud()
495 if (clk % baud && (div / 16) < 0x8000) { max310x_set_baud()
499 div = clk / baud; max310x_set_baud()
501 if (clk % baud && (div / 16) < 0x8000) { max310x_set_baud()
505 div = clk / baud; max310x_set_baud()
509 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8); max310x_set_baud()
510 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16); max310x_set_baud()
511 max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode); max310x_set_baud()
513 return DIV_ROUND_CLOSEST(clk, div); max310x_set_baud()
532 unsigned int div, clksrc, pllcfg = 0; max310x_set_ref_clk() local
540 for (div = 1; (div <= 63) && besterr; div++) { max310x_set_ref_clk()
541 fdiv = DIV_ROUND_CLOSEST(freq, div); max310x_set_ref_clk()
547 pllcfg = (0 << 6) | div; max310x_set_ref_clk()
554 pllcfg = (1 << 6) | div; max310x_set_ref_clk()
561 pllcfg = (2 << 6) | div; max310x_set_ref_clk()
568 pllcfg = (3 << 6) | div; max310x_set_ref_clk()
/linux-4.1.27/drivers/staging/rts5208/
H A Drtsx_card.c640 u8 mcu_cnt, div, max_div, ssc_depth, ssc_depth_mask; switch_ssc_clock() local
662 div = CLK_DIV_1; switch_ssc_clock()
663 while ((N < min_N) && (div < max_div)) { switch_ssc_clock()
665 div++; switch_ssc_clock()
667 dev_dbg(rtsx_dev(chip), "N = %d, div = %d\n", N, div); switch_ssc_clock() local
682 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt); switch_ssc_clock()
715 u8 sel, div, mcu_cnt; switch_normal_clock() local
725 div = CLK_DIV_4; switch_normal_clock()
732 div = CLK_DIV_4; switch_normal_clock()
739 div = CLK_DIV_2; switch_normal_clock()
746 div = CLK_DIV_2; switch_normal_clock()
753 div = CLK_DIV_2; switch_normal_clock()
760 div = CLK_DIV_1; switch_normal_clock()
767 div = CLK_DIV_1; switch_normal_clock()
774 div = CLK_DIV_1; switch_normal_clock()
781 div = CLK_DIV_1; switch_normal_clock()
788 div = CLK_DIV_1; switch_normal_clock()
819 (div << 4) | mcu_cnt); switch_normal_clock()
/linux-4.1.27/drivers/gpu/drm/tegra/
H A Ddsi.c44 unsigned int div; member in struct:tegra_dsi_state
489 unsigned int hact, hsw, hbp, hfp, i, mul, div; tegra_dsi_configure() local
501 div = state->div; tegra_dsi_configure()
547 hact = mode->hdisplay * mul / div; tegra_dsi_configure()
550 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; tegra_dsi_configure()
554 hbp = (mode->htotal - mode->hsync_end) * mul / div; tegra_dsi_configure()
558 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; tegra_dsi_configure()
567 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); tegra_dsi_configure()
577 bytes = 1 + (mode->hdisplay / 2) * mul / div; tegra_dsi_configure()
580 bytes = 1 + mode->hdisplay * mul / div; tegra_dsi_configure()
599 delay = DIV_ROUND_UP(delay * mul, div * lanes); tegra_dsi_configure()
603 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); tegra_dsi_configure()
608 value = 8 * mul / div; tegra_dsi_configure()
892 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div); tegra_dsi_encoder_atomic_check()
905 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); tegra_dsi_encoder_atomic_check()
907 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div, tegra_dsi_encoder_atomic_check()
946 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2; tegra_dsi_encoder_atomic_check()
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Dcomedi_8254.c368 unsigned int div = d1 * d2; comedi_8254_cascade_ns_to_timer() local
381 if (div * i8254->osc_base == *nanosec && comedi_8254_cascade_ns_to_timer()
385 div > d1 && div > d2 && comedi_8254_cascade_ns_to_timer()
386 div * i8254->osc_base > div && comedi_8254_cascade_ns_to_timer()
387 div * i8254->osc_base > i8254->osc_base) comedi_8254_cascade_ns_to_timer()
390 div = *nanosec / i8254->osc_base; comedi_8254_cascade_ns_to_timer()
392 start = div / d2; comedi_8254_cascade_ns_to_timer()
395 for (d1 = start; d1 <= div / d1 + 1 && d1 <= I8254_MAX_COUNT; d1++) { comedi_8254_cascade_ns_to_timer()
396 for (d2 = div / d1; comedi_8254_cascade_ns_to_timer()
397 d1 * d2 <= div + d1 + 1 && d2 <= I8254_MAX_COUNT; d2++) { comedi_8254_cascade_ns_to_timer()
/linux-4.1.27/arch/mips/alchemy/common/
H A Dclock.c297 int div; alchemy_clk_setup_mem() local
303 div = (v & (1 << 15)) ? 1 : 2; alchemy_clk_setup_mem()
307 div = (v & (1 << 31)) ? 1 : 2; alchemy_clk_setup_mem()
313 div = 2; alchemy_clk_setup_mem()
318 0, 1, div); alchemy_clk_setup_mem()
376 if (scale == 2) { /* only div-by-multiple-of-2 possible */ alchemy_calc_div()
539 unsigned long div, v, flags, ret; alchemy_clk_fgv1_setr() local
544 ret = alchemy_calc_div(rate, parent_rate, 2, 512, &div); alchemy_clk_fgv1_setr()
548 v |= div << sh; alchemy_clk_fgv1_setr()
665 unsigned long div, v, flags, ret; alchemy_clk_fgv2_setr() local
672 v ? 256 : 512, &div); alchemy_clk_fgv2_setr()
677 v |= (div & 0xff) << sh; alchemy_clk_fgv2_setr()
/linux-4.1.27/arch/blackfin/include/asm/
H A Dbfin_sport3.h68 #define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */
69 #define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */
86 u32 div; member in struct:sport_register
/linux-4.1.27/arch/arm/mach-omap1/
H A Dclock.c52 u32 div = omap_readl(MOD_CONF_CTRL_1); omap1_sossi_recalc() local
54 div = (div >> 17) & 0x7; omap1_sossi_recalc()
55 div++; omap1_sossi_recalc()
57 return clk->parent->rate / div; omap1_sossi_recalc()
369 int div; omap1_set_sossi_rate() local
374 div = (p_rate + rate - 1) / rate; omap1_set_sossi_rate()
375 div--; omap1_set_sossi_rate()
376 if (div < 0 || div > 7) omap1_set_sossi_rate()
381 l |= div << 17; omap1_set_sossi_rate()
384 clk->rate = p_rate / (div + 1); omap1_set_sossi_rate()
/linux-4.1.27/sound/soc/pxa/
H A Dpxa-ssp.c180 * @div: serial clock rate divider
182 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div) pxa_ssp_set_scr() argument
188 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */ pxa_ssp_set_scr()
191 sscr0 |= (div - 1) << 8; /* 1..4096 */ pxa_ssp_set_scr()
202 u32 div; pxa_ssp_get_scr() local
205 div = ((sscr0 >> 8) & 0xff) * 2 + 2; pxa_ssp_get_scr()
207 div = ((sscr0 >> 8) & 0xfff) + 1; pxa_ssp_get_scr()
208 return div; pxa_ssp_get_scr()
272 int div_id, int div) pxa_ssp_set_dai_clkdiv()
280 val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div); pxa_ssp_set_dai_clkdiv()
288 switch (div) { pxa_ssp_set_dai_clkdiv()
306 pxa_ssp_set_scr(ssp, div); pxa_ssp_set_dai_clkdiv()
271 pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, int div_id, int div) pxa_ssp_set_dai_clkdiv() argument
/linux-4.1.27/drivers/memory/
H A Domap-gpmc.c304 int div; gpmc_get_clk_period() local
310 div = (l & 0x03) + 1; gpmc_get_clk_period()
312 tick_ps *= div; gpmc_get_clk_period()
645 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
646 * div <= 0 check.
654 int div = gpmc_ns_to_ticks(wait_monitoring); gpmc_calc_waitmonitoring_divider() local
656 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1; gpmc_calc_waitmonitoring_divider()
657 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX; gpmc_calc_waitmonitoring_divider()
659 if (div > 4) gpmc_calc_waitmonitoring_divider()
661 if (div <= 0) gpmc_calc_waitmonitoring_divider()
662 div = 1; gpmc_calc_waitmonitoring_divider()
664 return div; gpmc_calc_waitmonitoring_divider()
676 int div = gpmc_ps_to_ticks(sync_clk); gpmc_calc_divider() local
678 if (div > 4) gpmc_calc_divider()
680 if (div <= 0) gpmc_calc_divider()
681 div = 1; gpmc_calc_divider()
683 return div; gpmc_calc_divider()
696 int div; gpmc_cs_set_timings() local
700 div = gpmc_calc_divider(t->sync_clk); gpmc_cs_set_timings()
701 if (div < 0) gpmc_cs_set_timings()
702 return div; gpmc_cs_set_timings()
712 * This statement must not change div to scale async WAITMONITORINGTIME gpmc_cs_set_timings()
721 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring); gpmc_cs_set_timings()
722 if (div < 0) { gpmc_cs_set_timings()
760 l |= (div - 1); gpmc_cs_set_timings()
771 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n", gpmc_cs_set_timings()
772 cs, (div * gpmc_get_fclk_period()) / 1000, div); gpmc_cs_set_timings()
1253 int div; gpmc_round_ps_to_sync_clk() local
1255 div = gpmc_calc_divider(sync_clk); gpmc_round_ps_to_sync_clk()
1257 temp = (temp + div - 1) / div; gpmc_round_ps_to_sync_clk()
1258 return gpmc_ticks_to_ps(temp * div); gpmc_round_ps_to_sync_clk()
/linux-4.1.27/drivers/net/ethernet/ti/
H A Ddavinci_mdio.c107 u32 mdio_in, div, mdio_out_khz, access_time; __davinci_mdio_reset() local
110 div = (mdio_in / data->pdata.bus_freq) - 1; __davinci_mdio_reset()
111 if (div > CONTROL_MAX_DIV) __davinci_mdio_reset()
112 div = CONTROL_MAX_DIV; __davinci_mdio_reset()
115 __raw_writel(div | CONTROL_ENABLE, &data->regs->control); __davinci_mdio_reset()
123 mdio_out_khz = mdio_in / (1000 * (div + 1)); __davinci_mdio_reset()
/linux-4.1.27/arch/mips/include/asm/octeon/
H A Dcvmx-gpio-defs.h181 uint64_t div:1; member in struct:cvmx_gpio_clk_qlmx::cvmx_gpio_clk_qlmx_s
185 uint64_t div:1;
196 uint64_t div:1; member in struct:cvmx_gpio_clk_qlmx::cvmx_gpio_clk_qlmx_cn61xx
200 uint64_t div:1;
209 uint64_t div:1; member in struct:cvmx_gpio_clk_qlmx::cvmx_gpio_clk_qlmx_cn63xx
213 uint64_t div:1;
/linux-4.1.27/arch/avr32/mach-at32ap/
H A Dat32ap700x.c117 unsigned long div, mul, rate; pll_get_rate() local
119 div = PM_BFEXT(PLLDIV, control) + 1; pll_get_rate()
123 rate = (rate + div / 2) / div; pll_get_rate()
134 unsigned long div; pll_set_rate() local
159 for (div = div_min; div <= div_max; div++) { pll_set_rate()
160 pll_in = (base + div / 2) / div; pll_set_rate()
171 div_best_fit = div; pll_set_rate()
372 unsigned long parent_rate, child_div, actual_rate, div; cpu_clk_set_rate() local
387 div = (parent_rate + rate / 2) / rate; cpu_clk_set_rate()
388 if (div > child_div) cpu_clk_set_rate()
389 div = child_div; cpu_clk_set_rate()
390 cpusel = (div > 1) ? (fls(div) - 2) : 0; cpu_clk_set_rate()
528 unsigned long div = 1; genclk_get_rate() local
532 div = 2 * (PM_BFEXT(DIV, control) + 1); genclk_get_rate()
534 return clk->parent->get_rate(clk->parent) / div; genclk_get_rate()
540 unsigned long parent_rate, actual_rate, div; genclk_set_rate() local
549 div = (parent_rate + rate) / (2 * rate) - 1; genclk_set_rate()
550 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN); genclk_set_rate()
551 actual_rate = parent_rate / (2 * (div + 1)); genclk_set_rate()
/linux-4.1.27/arch/c6x/include/asm/
H A Dclock.h93 u32 div; member in struct:clk
102 #define PRE_PLL BIT(3) /* source is before PLL mult/div */
/linux-4.1.27/arch/cris/arch-v32/kernel/
H A Ddebugport.c131 tr_baud_div.div = rec_baud_div.div = 29493000 / p->baudrate / 8; start_port()
/linux-4.1.27/drivers/video/fbdev/mbx/
H A Dmbxfb.c122 struct pixclock_div *div) mbxfb_get_pixclock()
155 div->m = m; mbxfb_get_pixclock()
156 div->n = n; mbxfb_get_pixclock()
157 div->p = p; mbxfb_get_pixclock()
184 struct pixclock_div div; mbxfb_check_var() local
186 var->pixclock = mbxfb_get_pixclock(var->pixclock, &div); mbxfb_check_var()
236 struct pixclock_div div; mbxfb_set_par() local
282 var->pixclock = mbxfb_get_pixclock(info->var.pixclock, &div); mbxfb_set_par()
284 write_reg_dly((Disp_Pll_M(div.m) | Disp_Pll_N(div.n) | mbxfb_set_par()
285 Disp_Pll_P(div.p) | DISP_PLL_EN), DISPPLL); mbxfb_set_par()
121 mbxfb_get_pixclock(unsigned int pixclock_ps, struct pixclock_div *div) mbxfb_get_pixclock() argument
/linux-4.1.27/sound/soc/davinci/
H A Ddavinci-mcasp.c536 int div, bool explicit) __davinci_mcasp_set_clkdiv()
544 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); __davinci_mcasp_set_clkdiv()
546 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); __davinci_mcasp_set_clkdiv()
551 ACLKXDIV(div - 1), ACLKXDIV_MASK); __davinci_mcasp_set_clkdiv()
553 ACLKRDIV(div - 1), ACLKRDIV_MASK); __davinci_mcasp_set_clkdiv()
555 mcasp->bclk_div = div; __davinci_mcasp_set_clkdiv()
559 mcasp->bclk_lrclk_ratio = div; __davinci_mcasp_set_clkdiv()
571 int div) davinci_mcasp_set_clkdiv()
573 return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1); davinci_mcasp_set_clkdiv()
825 /* Set the TX clock controls : div = 1 and internal */ mcasp_dit_hw_param()
883 int div = mcasp->sysclk_freq / bclk_freq; davinci_mcasp_calc_clk_div() local
887 if (div == 0 || davinci_mcasp_calc_clk_div()
888 ((mcasp->sysclk_freq / div) - bclk_freq) > davinci_mcasp_calc_clk_div()
889 (bclk_freq - (mcasp->sysclk_freq / (div+1)))) { davinci_mcasp_calc_clk_div()
890 div++; davinci_mcasp_calc_clk_div()
896 (div*1000000 + (int)div64_long(1000000LL*rem, davinci_mcasp_calc_clk_div()
898 /div - 1000000; davinci_mcasp_calc_clk_div()
900 return div; davinci_mcasp_calc_clk_div()
921 int ppm, div; davinci_mcasp_hw_params() local
926 div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*channels, davinci_mcasp_hw_params()
932 __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0); davinci_mcasp_hw_params()
535 __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div, bool explicit) __davinci_mcasp_set_clkdiv() argument
570 davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) davinci_mcasp_set_clkdiv() argument
/linux-4.1.27/drivers/staging/clocking-wizard/
H A Dclk-xlnx-clock-wizard.c195 /* we don't support fractional div/mul yet */ clk_wzrd_probe()
201 dev_warn(&pdev->dev, "fractional div/mul not supported\n"); clk_wzrd_probe()
222 /* register div */ clk_wzrd_probe()
241 /* register div per output */ clk_wzrd_probe()
/linux-4.1.27/drivers/clocksource/
H A Dtime-armada-370-xp.c55 #define TIMER0_DIV(div) ((div) << 19)
59 #define TIMER1_DIV(div) ((div) << 22)

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