278 		struct ipu_di_signal_cfg *sig, int div)  in ipu_di_sync_config_noninterlaced()  argument
293 			.offset_count = div * sig->v_to_h_sync,  in ipu_di_sync_config_noninterlaced()
353 			.offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */  in ipu_di_sync_config_noninterlaced()
379 			.offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */  in ipu_di_sync_config_noninterlaced()
438 			unsigned div;  in ipu_di_config_clock()  local
443 			div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);  in ipu_di_config_clock()
444 			div = clamp(div, 1U, 255U);  in ipu_di_config_clock()
446 			clkgen0 = div << 4;  in ipu_di_config_clock()
457 		unsigned div, error;  in ipu_di_config_clock()  local
460 		div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock);  in ipu_di_config_clock()
461 		div = clamp(div, 1U, 255U);  in ipu_di_config_clock()
462 		rate = clkrate / div;  in ipu_di_config_clock()
467 			rate, div, (signed)(error - 1000) / 10, error % 10);  in ipu_di_config_clock()
473 			clkgen0 = div << 4;  in ipu_di_config_clock()
476 			unsigned div;  in ipu_di_config_clock()  local
483 			div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);  in ipu_di_config_clock()
484 			div = clamp(div, 1U, 255U);  in ipu_di_config_clock()
486 			clkgen0 = div << 4;  in ipu_di_config_clock()
550 	u32 div;  in ipu_di_init_sync_panel()  local
567 	div = ipu_di_read(di, DI_BS_CLKGEN0) & 0xfff;  in ipu_di_init_sync_panel()
568 	div = div / 16;		/* Now divider is integer portion */  in ipu_di_init_sync_panel()
572 	ipu_di_write(di, (div << 16), DI_BS_CLKGEN1);  in ipu_di_init_sync_panel()
574 	ipu_di_data_wave_config(di, SYNC_WAVE, div - 1, div - 1);  in ipu_di_init_sync_panel()
575 	ipu_di_data_pin_config(di, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);  in ipu_di_init_sync_panel()
595 		ipu_di_sync_config_noninterlaced(di, sig, div);  in ipu_di_init_sync_panel()