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/linux-4.1.27/Documentation/
Dphy.txt1 PHY SUBSYSTEM
4 This document explains the Generic PHY Framework along with the APIs provided,
9 *PHY* is the abbreviation for physical layer. It is used to connect a device
10 to the physical medium e.g., the USB controller has a PHY to provide functions
13 controllers have PHY functionality embedded into it and others use an external
14 PHY. Other peripherals that use PHY include Wireless LAN, Ethernet,
17 The intention of creating this framework is to bring the PHY drivers spread
21 This framework will be of use only to devices that use external PHY (PHY
24 2. Registering/Unregistering the PHY provider
26 PHY provider refers to an entity that implements one or more PHY instances.
[all …]
D00-INDEX357 - Description of the generic PHY framework.
/linux-4.1.27/drivers/phy/
DKconfig2 # PHY
5 menu "PHY Subsystem"
8 bool "PHY Core"
10 Generic PHY support.
12 This framework is designed to provide a generic interface for PHY
14 API by which phy drivers can create PHY using the phy framework and
15 phy users can obtain reference to the PHY. All the users of this
19 tristate "Marvell Berlin USB PHY Driver"
23 Enable this to support the USB PHY on Marvell Berlin SoCs.
26 tristate "Marvell Berlin SATA PHY driver"
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/phy/
Dphy-bindings.txt2 information about PHY subsystem refer to Documentation/phy.txt
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
29 That node describes an IP block (PHY provider) that implements 2 different PHYs.
33 PHY user node
37 phys : the phandle for the PHY device (used by the PHY subsystem)
[all …]
Dsamsung-phy.txt10 the PHY specifier identifies the PHY and its meaning is as follows:
16 Samsung EXYNOS SoC series Display Port PHY
25 - #phy-cells : from the generic PHY bindings, must be 0;
27 Samsung S5P/EXYNOS SoC series USB PHY
45 PHY module
47 The first phandle argument in the PHY specifier identifies the PHY, its
74 Then the PHY can be used in other nodes such as:
81 Refer to DT bindings documentation of particular PHY consumer devices for more
84 Samsung SATA PHY Controller
87 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
[all …]
Dqcom-dwc3-usb-phy.txt1 Qualcomm DWC3 HS AND SS PHY CONTROLLER
4 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
5 controllers. Each DWC3 PHY controller should have its own node.
9 - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
10 - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
11 - reg: offset and length of the DWC3 PHY controller register set
15 - clock-names: Should contain "ref" for the PHY reference clock
Dti-phy.txt1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
11 e.g. USB3 PHY and SATA PHY on OMAP5.
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
30 OMAP USB2 PHY
44 - ctrl-module : phandle of the control module used by PHY driver to power on
45 the PHY.
58 TI PIPE3 PHY
[all …]
Drockchip-usb-phy.txt1 ROCKCHIP USB2 PHY
11 Each PHY should be represented as a sub-node.
16 - reg: PHY configure reg address offset in GRF
17 "0x320" - for PHY attach to OTG controller
18 "0x334" - for PHY attach to HOST0 controller
19 "0x348" - for PHY attach to HOST1 controller
Dqcom-ipq806x-sata-phy.txt1 Qualcomm IPQ806x SATA PHY Controller
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
5 Each SATA PHY controller should have its own node.
9 - reg: offset and length of the SATA PHY register set;
Dberlin-sata-phy.txt1 Berlin SATA PHY
10 - phy-cells: from the generic PHY bindings, must be 1
15 Each PHY should be represented as a sub-node.
18 - reg: the PHY number
Dqcom-apq8064-sata-phy.txt1 Qualcomm APQ8064 SATA PHY Controller
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
5 Each SATA PHY controller should have its own node.
9 - reg: offset and length of the SATA PHY register set;
Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
4 PHY (pair of lanes) has its own node.
8 - reg : PHY memory resource is the SDS PHY access resource.
10 the mode of the PHY. Possible values are 0 (SATA),
57 NOTE: PHY override parameters are board specific setting.
Dbrcm,kona-usb2-phy.txt1 BROADCOM KONA USB2 PHY
5 - reg: offset and length of the PHY registers
7 Refer to phy/phy-bindings.txt for the generic PHY binding properties
Dhix5hd2-phy.txt1 Hisilicon hix5hd2 SATA PHY
6 - reg: offset and length of the PHY registers
8 Refer to phy/phy-bindings.txt for the generic PHY binding properties
Ddm816x-phy.txt1 Device tree binding documentation for am816x USB PHY
6 - reg : offset and length of the PHY register set.
11 - #phy-cells : from the generic PHY bindings, must be 1
Drcar-gen2-phy.txt1 * Renesas R-Car generation 2 USB PHY
4 2 USB PHY contains.
16 The USB PHY device tree node should have the subnodes corresponding to the USB
21 The phandle's argument in the PHY specifier is the USB controller selector for
Dst-spear-miphy.txt8 - reg : offset and length of the PHY register set.
10 - #phy-cells : from the generic PHY bindings, must be 1.
Dphy-stih407-usb.txt1 ST STiH407 USB PHY controller
3 This file documents the dt bindings for the usb picoPHY driver which is the PHY for both USB2 and U…
Dberlin-usb-phy.txt1 * Marvell Berlin USB PHY
Dphy-miphy365x.txt1 STMicroelectronics STi MIPHY365x PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
Dphy-stih41x-usb.txt1 STMicroelectronics STiH41x USB PHY binding
Dsun4i-usb-phy.txt1 Allwinner sun4i USB PHY
Dphy-miphy28lp.txt1 STMicroelectronics STi MIPHY28LP PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
Dphy-mvebu.txt1 * Marvell MVEBU SATA PHY
Dsun9i-usb-phy.txt1 Allwinner sun9i USB PHY
/linux-4.1.27/Documentation/networking/
Dphy.txt3 PHY Abstraction Layer
10 PHY. The PHY concerns itself with negotiating link parameters with the link
17 the PHY management code with the network driver. This has resulted in large
23 accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
30 Basically, this layer is meant to provide an interface to PHY devices which
36 Most network devices are connected to a PHY by means of a management bus.
46 mii_id is the address on the bus for the PHY, and regnum is the register
68 Connecting to a PHY
71 between the PHY device, and the network device. At this time, the PHY's bus
73 At this point, there are several ways to connect to the PHY:
[all …]
Ddm9000.txt90 device, whether or not an external PHY is attached to the device and
109 The chip is connected to an external PHY.
118 Switch to using the simpler PHY polling method which does not
119 try and read the MII PHY state regularly. This is only available
120 when using the internal PHY. See the section on link state polling
124 "Force simple NSR based PHY polling" allows this flag to be
128 PHY Link state polling
133 depending on the version of the chip and on which PHY is being used.
135 For the internal PHY, the original (and currently default) method is
140 To reduce the overhead for the internal PHY, there is now the option
[all …]
Dswitchdev.txt15 PHY PHY | | | | NIC0 NIC1
34 PHY PHY | | | | eth0 eth1
Dieee802154.txt8 two layers: Medium Access Control (MAC) and Physical (PHY). And there
22 - PHY - represents device drivers
107 register PHY in the system
110 freeing registered PHY
Dstmmac.txt30 phyaddr: to manually provide the physical address to the PHY device;
112 PHY and GPHY devices.
153 o interface: PHY device's interface.
205 o irqs: list of IRQs, one per PHY.
206 o probed_phy_irq: if irqs is NULL, use this for probed PHY.
247 there are two MAC cores: one MAC is for MDIO Bus/PHY emulation
266 and the second one, with a real PHY device attached to the bus,
342 the LPI mode & communicate this to PHY.
346 register and the PHY devices MCD registers.
Daltera_tse.txt46 The driver limits PHY operations to 10/100Mbps, and has not yet been fully
91 4.5) PHY Support
92 The driver is compatible with PAL to work with PHY and GPHY devices.
De1000e.txt199 Allows PHY to turn off in lower power states. The user can set this parameter
207 This workaround skips resetting the PHY at shutdown for the initial
D00-INDEX168 - The PHY abstraction layer.
De1000.txt328 Allows PHY to turn off in lower power states. The user can turn off
336 This workaround skips resetting the PHY at shutdown for the initial
/linux-4.1.27/Documentation/devicetree/bindings/usb/
Dusb-nop-xceiv.txt1 USB NOP PHY
7 - clocks: phandle to the PHY clock. Use as per Documentation/devicetree
13 - clock-frequency: the clock frequency (in Hz) that the PHY clock must
16 - vcc-supply: phandle to the regulator that provides power to the PHY.
38 hsusb1_phy is a NOP USB PHY device that gets its clock from an oscillator
39 and expects that clock to be configured to 19.2MHz by the NOP PHY driver.
40 hsusb1_vcc_regulator provides power to the PHY and GPIO 7 controls RESET.
Dkeystone-phy.txt1 TI Keystone USB PHY
9 The main purpose of this PHY driver is to enable the USB PHY reference clock
10 gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
11 an NOP PHY driver. Hence this node is referenced as both the usb2 and usb3
Dmsm-hsusb.txt8 - usb-phy: phandle for the PHY device
18 USB PHY with optional OTG:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
31 "phy" USB PHY reference clock
45 "phy" USB PHY controller reset
49 1 - PHY control
55 - qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device
63 0 - PHY one, default
64 1 - Second PHY
Dnvidia,tegra20-usb-phy.txt1 Tegra SOC USB PHY
3 The device node for Tegra SOC USB PHY:
11 - The PHY's own register set.
13 - The register set of the PHY containing the UTMI pad control registers.
18 - reg: The clock needed to access the PHY's own registers. This is the
24 - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).
29 - usb: The PHY's own reset signal.
30 - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control
34 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
36 Required PHY timing params for utmi phy, for all chips:
[all …]
Ddwc3.txt11 - usb-phy : array of phandle for the PHY device. The first element
12 in the array is expected to be a handle to the USB2/HS PHY and
13 the second element is expected to be a handle to the USB3/SS PHY
14 - phys: from the *Generic PHY* bindings
15 - phy-names: from the *Generic PHY* bindings
28 - snps,del_phy_power_chg_quirk: when set core will delay PHY power change
34 - snps,tx_de_emphasis: the value driven to the PHY is controlled by the
Dehci-orion.txt11 - phys: reference to the USB PHY
12 - phy-names: name of the USB PHY, should be "usb"
Domap-usb.txt18 - usb-phy : the phandle for the PHY device
19 - phys : the phandle for the PHY device (used by generic PHY framework)
20 - phy-names : the names of the PHY corresponding to the PHYs present in the
Dehci-omap.txt14 - phys: list of phandles to PHY nodes.
16 PHY mode i.e. OMAP_EHCI_PORT_MODE_PHY
Dam33xx-usb.txt8 at least a control module node, USB node and a PHY node. The second USB
9 node and its PHY node is optional. The DMA node is also optional.
20 USB PHY
23 reg: offset and length of the "USB PHY" register space
26 The PHY should have a "phy" alias numbered properly in the alias
Dsamsung-usbphy.txt1 SAMSUNG USB-PHY controllers
8 TODO: Adding the PHY binding with controller(s) according to the under
9 development generic PHY driver.
Dci-hdrc-qcom.txt7 - usb-phy: phandle for the PHY device
Dci-hdrc-usb2.txt10 - phys: reference to the USB PHY
Dexynos-usb.txt21 - phys: from the *Generic PHY* bindings; specifying phy used by port.
62 - phys: from the *Generic PHY* bindings, specifying phy used by port.
Dohci-st.txt13 - phys : phandle for the PHY device
Dnvidia,tegra20-ehci.txt13 - nvidia,phy : phandle of the PHY that the controller is connected to.
Dehci-st.txt15 - phys : phandle for the PHY device
Dtwlxxxx-usb.txt23 TWL4030 USB PHY AND COMPARATOR
Dfsl-usb.txt41 port power polarity of internal PHY signal DRVVBUS is inverted.
/linux-4.1.27/drivers/usb/phy/
DKconfig45 tristate "Keystone USB PHY Driver"
50 interface to interact with USB 2.0 and USB 3.0 PHY that is part
65 tristate "AM335x USB PHY Driver"
71 This driver provides PHY support for that phy which part for the
78 This driver provides common interface to interact, for Samsung USB 2.0 PHY
79 driver and later for Samsung USB 3.0 PHY driver.
88 UTMI PHY is embedded in OMAP4430. The internal PHY configurations APIs
90 The definition of internal PHY APIs are in the mach-omap2 layer.
147 handles PHY initialization, clock management, and workarounds
152 has an external PHY.
[all …]
/linux-4.1.27/Documentation/ABI/testing/
Dsysfs-bus-mdio6 This attribute contains the 32-bit PHY Identifier as reported
16 This attribute contains the PHY interface as configured by the
19 appropriate mode for its data lines to the PHY hardware.
26 This attribute contains the boolean value whether a given PHY
29 PHY configurations.
Dsysfs-class-uwb_rc10 Wideband MAC and PHY Specification' is assumed.
149 This gives an estimate on a suitable PHY rate. Refer
Dsysfs-class-uwb_rc-wusbhc32 The maximum PHY rate to use for all connected devices.
Dsysfs-ptp24 name" and to help distinguish PHY based devices from
/linux-4.1.27/drivers/net/wireless/b43/
DKconfig126 bool "Support for G-PHY (802.11g) devices"
130 This PHY type can be found in the following chipsets:
135 bool "Support for N-PHY (the main 802.11n series) devices"
139 This PHY type can be found in the following chipsets:
146 bool "Support for LP-PHY (low-power 802.11g) devices"
150 The LP-PHY is a low-power PHY built into some notebooks
155 bool "Support for HT-PHY (high throughput 802.11n) devices"
159 This PHY type with 3x3:3 MIMO can be found in the BCM4331 PCI chipset.
162 bool "Support for LCN-PHY devices (BROKEN)"
165 Support for the LCN-PHY.
[all …]
/linux-4.1.27/Documentation/phy/
Dsamsung-usb2.txt2 | Samsung USB 2.0 PHY adaptation layer |
8 The architecture of the USB 2.0 PHY module in Samsung SoCs is similar
10 create a one driver that would fit all these PHY controllers. Often
12 registers of the PHY. In some rare cases the order of register writes or
13 the PHY powering up process had to be altered. This adaptation layer is
22 the probe function and provides two callbacks to the Generic PHY
25 of the PHY module. Depending on which SoC was chosen they execute SoC
67 used as the reference clock for the PHY module to the value
125 Enable USB PHY support for Exynos 4210. This option requires that
126 Samsung USB 2.0 PHY driver is enabled and means that support for this
/linux-4.1.27/drivers/net/phy/
DKconfig2 # PHY Layer Configuration
6 tristate "PHY Device support and infrastructure"
9 Ethernet controllers are usually attached to PHY
11 managing PHY devices.
15 comment "MII PHY device drivers"
32 Currently supports the AMD 10GbE PHY
76 tristate "Drivers for Broadcom 63xx SOCs internal PHY"
100 Supports the Realtek 821x PHY.
105 Currently supports the DP83865 PHY.
113 tristate "Driver for LSI ET1011C PHY"
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/video/
Dexynos_dp.txt8 For the DP-PHY initialization, we use the dptx-phy node.
11 Base address of DP PHY register.
13 The bit-mask used to enable/disable DP PHY.
31 from general PHY binding: the phandle for the PHY device.
33 from general PHY binding: Should be "dp".
Dexynos_hdmi.txt21 d) sclk_hdmiphy: HDMI PHY clock output, one of two possible inputs of
/linux-4.1.27/drivers/atm/
Dnicstarmac.copyright6 * 10/1/97 - commented out CFG_PHYIE bit - we don't care when the PHY
10 * 10/5/97 - added code to handle PHY interrupts, disable PHY on
11 * loss of link, and correctly re-enable PHY when link is
19 * PHY component is expected to be 155 Mbps S/UNI-Lite or IDT 77155;
20 * see init_nicstar() for PHY initialization to change this. This driver
DKconfig190 bool "Use suni PHY driver (155Mbps)"
202 bool "Use IDT77015 PHY driver (25Mbps)"
302 memory (128K, 512K, 1M), and the PHY type (Single/Multi mode OC3,
388 bool "Use S/UNI PHY driver"
/linux-4.1.27/drivers/net/ethernet/davicom/
DKconfig17 bool "Force simple NSR based PHY polling"
22 costly MII PHY reads. Note, this will not work if the chip is
23 operating with an external PHY.
/linux-4.1.27/Documentation/devicetree/bindings/net/
Dethernet.txt12 - phy-mode: string, operation mode of the PHY interface; supported values are
17 - phy-handle: phandle, specifies a reference to a node representing a PHY
28 - managed: string, specifies the PHY management type. Supported values are:
32 Child nodes of the Ethernet controller are typically the individual PHY devices
35 For non-MDIO PHY management see fixed-link.txt.
Dmicrel.txt1 Micrel PHY properties.
20 See the respective PHY datasheet for the mode values.
28 Note that this option in only needed for certain PHY revisions with a
Demac_rockchip.txt14 - phy-supply: phandle to a regulator if the PHY needs one
22 Child nodes of the driver are the individual PHY devices connected to the
23 MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus.
Dapm-xgene-enet.txt24 - phy-connection-type: Interface type between ethernet device and PHY device
26 Required properties for ethernet interfaces that have external PHY:
27 - phy-handle: Reference to a PHY node connected to this device
35 - compatible: PHY identifier. Please refer ./phy.txt for the format.
Drockchip-dwmac.txt11 - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.
24 is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
25 PHY provides the reference clock(50MHz), "output" means GMAC provides the
36 - phy-supply: phandle to a regulator if the PHY needs one
Dbrcm,bcmgenet.txt22 configurations where a PHY (internal or external) is used.
32 - mdio bus node: this node should always be present regarless of the PHY
45 Ethernet PHY node properties:
50 Internal Gigabit PHY example:
97 External MDIO-connected Gigabit PHY/switch:
Dmarvell-orion-mdio.txt16 The child nodes of the MDIO driver are the individual PHY devices
18 PHY address on the MDIO bus.
Darc_emac.txt16 Child nodes of the driver are the individual PHY devices connected to the
17 MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus.
Dmarvell-pxa168.txt17 Each PHY can be represented as a sub-node. This is not mandatory.
20 - reg: the MDIO address of the PHY.
Dbrcm,systemport.txt10 - phy-mode: Should be a string describing the PHY interface to the
11 Ethernet switch/PHY, see Documentation/devicetree/bindings/net/ethernet.txt
Dfsl-tsec-phy.txt3 The MDIO is a bus to which the PHY devices are connected. For each
5 the definition of the PHY node in booting-without-of.txt for an example
6 of how to define a PHY.
35 As of this writing, every tsec is associated with an internal TBI PHY.
36 This PHY is accessed through the local MDIO bus. These buses are defined
Dsmsc911x.txt19 internal PHY
21 external PHY
Dmicrel-ksz90x1.txt1 Micrel KSZ9021/KSZ9031 Gigabit Ethernet PHY
60 /* Attach to an Ethernet device with autodetected PHY */
69 /* Attach to an explicitly-specified PHY */
Dphy.txt1 PHY nodes
31 - max-speed: Maximum PHY supported speed (10, 100, 1000...)
Dfixed-link.txt5 normal MDIO-managed PHY device. For those situations, a Device Tree
25 - a: emulated PHY ID, choose any but but unique to the all specified
Dfsl-fec.txt15 - phy-supply : regulator that powers the Ethernet PHY.
16 - phy-handle : phandle to the PHY device connected to this device.
Dallwinner,sun4i-mdio.txt9 - phy-supply: phandle to a regulator if the PHY needs one
Dmarvell-orion-net.txt55 - speed: port speed if no PHY connected.
56 - duplex: port mode if no PHY connected.
Dallwinner,sun7i-a20-gmac.txt14 - phy-supply: phandle to a regulator if the PHY needs one
Ddavicom-dm9000.txt13 - davicom,ext-phy : Use external PHY
Dhisilicon-hix5hd2-gmac.txt16 - PHY subnode: inherits from phy binding [2]
Dbroadcom-bcm87xx.txt2 have these bindings in addition to the standard PHY bindings.
Dsamsung-sxgbe.txt15 - phy-mode: String, operation mode of the PHY interface.
Dbrcm,unimac-mdio.txt22 Child nodes of this MDIO bus controller node are standard Ethernet PHY device
Dmarvell-pp2.txt29 - phy: a phandle to a phy node defining the PHY address (as the reg
Damd-xgbe-phy.txt1 * AMD 10GbE PHY driver (amd-xgbe-phy)
Dcavium-pip.txt6 ports might be an individual Ethernet PHY.
Dsti-dwmac.txt21 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
Dkeystone-netcp.txt105 ----phy-handle: phandle to PHY device
113 will only initialize these ports and attach PHY
/linux-4.1.27/drivers/net/ethernet/wiznet/
DKconfig28 PHY and hardware TCP/IP stack, but this driver is limited to
29 the MAC and PHY functions only, onchip TCP/IP is unused.
41 PHY and hardware TCP/IP stack, but this driver is limited to
42 the MAC and PHY functions only, onchip TCP/IP is unused.
/linux-4.1.27/Documentation/devicetree/bindings/media/
Dti,omap3isp.txt17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
42 vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1
43 vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2
Dvideo-interfaces.txt223 reg = <1>; /* CSI-2 PHY #1 of 2: PHY_S,
/linux-4.1.27/drivers/bus/
DKconfig90 protocol to scp protocol. In OMAP4, USB PHY is connected via
91 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
/linux-4.1.27/Documentation/devicetree/bindings/pci/
Dti-pci.txt10 - phys : list of PHY specifiers (used by generic PHY framework)
Dbrcm,iproc-pcie.txt17 - phys: phandle of the PCIe PHY device
/linux-4.1.27/Documentation/devicetree/bindings/memory-controllers/ti/
Demif.txt14 <1> : Attila PHY
15 <2> : Intelli PHY
/linux-4.1.27/Documentation/devicetree/bindings/ata/
Dahci-platform.txt31 - phys : reference to the SATA PHY node
46 - phys : reference to the SATA PHY node
Dtegra-sata.txt27 - sata-phy : XUSB PADCTL SATA PHY
Dahci-st.txt12 - phys : The phandle for the PHY port
Dapm-xgene.txt24 * "sata-phy" for the SATA 6.0Gbps PHY
/linux-4.1.27/Documentation/ABI/stable/
Dfirewire-cdev27 - PHY packet transmission and reception
48 - PHY packet transmission and reception
73 request reception, or PHY packet reception. Always use a read
/linux-4.1.27/Documentation/devicetree/bindings/powerpc/4xx/
Demac.txt45 - phy-mode : string, mode of operations of the PHY interface.
51 MDIO lines for the PHY used by this EMAC.
66 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
68 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
/linux-4.1.27/arch/mips/boot/dts/brcm/
Dbcm97420c.dts26 /* FIXME: MAC driver comes up but cannot attach to PHY */
/linux-4.1.27/Documentation/devicetree/bindings/power/
Disp1704.txt8 - usb-phy: Should contain a phandle to the USB PHY
/linux-4.1.27/arch/mips/lantiq/
DKconfig41 bool "XRX200 PHY firmware loader"
/linux-4.1.27/arch/powerpc/boot/dts/
Dpdm360ng.dts130 /* USB1 using external ULPI PHY */
135 /* USB0 using internal UTMI PHY */
Dmpc866ads.dts75 PHY: ethernet-phy@f { label
88 phy-handle = <&PHY>;
Dtqm8xx.dts108 PHY: ethernet-phy@f { label
120 phy-handle = <&PHY>;
Dmpc5121ads.dts134 /* USB0 using internal UTMI PHY */
Dmpc5121.dtsi297 /* USB1 using external ULPI PHY */
310 /* USB0 using internal UTMI PHY */
/linux-4.1.27/net/mac802154/
DKconfig12 only PHY level of IEEE 802.15.4 standard).
/linux-4.1.27/drivers/net/ethernet/freescale/
DKconfig51 an external MII PHY chip or 10 Mbps 7-wire interface
53 If your board uses an external PHY connected to FEC, enable this.
/linux-4.1.27/Documentation/scsi/
Dufs.txt28 on MIPI M-PHY physical layer standard. UFS uses MIPI M-PHY as the
85 MIPI UniPro and MIPI M-PHY. UIC provides 2 service access points
DChangeLog.arcmsr10 ** 1.20.00.00 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error
/linux-4.1.27/arch/arm/mach-davinci/
DKconfig186 bool "RMII Ethernet PHY"
188 Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x
189 EVM. This PHY is found on the UI daughter card that is supplied with
191 NOTE: Please take care while choosing this option, MII PHY will
/linux-4.1.27/Documentation/devicetree/bindings/net/dsa/
Ddsa.txt51 - phy-handle : Phandle to a PHY on an external MDIO bus, not the
57 PHY node specified by the 'phy-handle' property. See
/linux-4.1.27/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/
Ducc.txt48 - phy-handle : The phandle for the PHY connected to this controller.
51 - phy-connection-type : a string naming the controller/PHY interface type,
/linux-4.1.27/Documentation/devicetree/bindings/
Dmarvell.txt74 The MDIO is a bus to which the PHY devices are connected. For each
76 the definition of the PHY node below for an example of how to define
77 a PHY.
139 - phy : the phandle for the PHY connected to this ethernet
155 c) Marvell Discovery PHY nodes
163 Example Discovery PHY node:
/linux-4.1.27/Documentation/devicetree/bindings/drm/imx/
Dhdmi.txt7 with accompanying PHY IP.
/linux-4.1.27/arch/arm/boot/dts/
Dimx28-eukrea-mbmx287lc.dts16 * Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC
Dimx28-eukrea-mbmx283lc.dts16 * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC
Dimx25-karo-tx25.dts56 MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */
Dimx28-duckbill.dts42 MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */
Dimx6qdl-tx6.dtsi302 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
303 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
418 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
Domap3-cm-t3x.dtsi41 /* HS USB Host PHY on PORT 1 */
47 /* HS USB Host PHY on PORT 2 */
Domap5.dtsi830 phy-type = <2>; /* DDR PHY type: Intelli PHY */
842 phy-type = <2>; /* DDR PHY type: Intelli PHY */
Dimx6qdl-gw51xx.dtsi233 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
Dkirkwood-dir665.dts256 /* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set
Domap3-igep0020-common.dtsi56 /* HS USB Host PHY on PORT 1 */
Domap3-overo-base.dtsi43 /* HS USB Host PHY on PORT 2 */
Darmada-385-db-ap.dts152 * provide a clock to the PHY
Domap5-uevm.dts52 /* HS USB Host PHY on PORT 2 */
61 /* HS USB Host PHY on PORT 3 */
Domap4-duovero.dtsi38 /* HS USB Host PHY on PORT 1 */
Domap5-cm-t54.dts61 /* HS USB Host PHY on PORT 2 */
67 /* HS USB Host PHY on PORT 3 */
Domap4-var-som-om44.dtsi36 /* HS USB Host PHY on PORT 1 */
Dimx6qdl-gw52xx.dtsi356 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
Domap3-beagle-xm.dts87 /* HS USB Host PHY on PORT 2 */
Domap3-tao3530.dtsi44 /* HS USB Host PHY on PORT 2 */
Darmada-xp-lenovo-ix4-300d.dts284 * Warning: you need both eth1 & 0 PHY initialized (i.e having
Dimx6qdl-gw53xx.dtsi278 eth1: sky2@8 { /* MAC/PHY on bus 8 */
Domap3-beagle.dts62 /* HS USB Host PHY on PORT 2 */
Dimx6q-gw5400-a.dts352 eth1: sky2@8 { /* MAC/PHY on bus 8 */
Dimx6qdl-gw54xx.dtsi367 eth1: sky2@8 { /* MAC/PHY on bus 8 */
Darmada-388-gp.dts147 * clock to the PHY
Domap4-panda-common.dtsi83 /* HS USB Host PHY on PORT 1 */
Dexynos5250-arndale.dts111 // SMSC USB3503 connected in hardware only mode as a PHY
Dam335x-pepper.dts307 /* ethernet PHY nReset */
Dstih407-pinctrl.dtsi176 * standard PHY transceiver on-board).
Domap3-pandora-common.dtsi413 /* USB Host PHY */
Dstih416-clock.dtsi584 * Add a dummy clock for the HDMI PHY for the VCC input mux
Dsun6i-a31.dtsi344 * clock. The gmac driver will choose one parent depending on the PHY
Dsun7i-a20.dtsi469 * clock. The gmac driver will choose one parent depending on the PHY
/linux-4.1.27/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra124-xusb-padctl.txt6 associated PHY that must be powered up before the pad can be used.
24 - #phy-cells: Should be 1. The specifier is the index of the PHY to reference.
/linux-4.1.27/Documentation/devicetree/bindings/mfd/
Dmfd.txt11 drivers, level shifters, PHY (physical interfaces to things like USB or
/linux-4.1.27/Documentation/memory-devices/
Dti-emif.txt41 - PHY type
/linux-4.1.27/drivers/of/
DKconfig63 OpenFirmware MDIO bus (Ethernet PHY) accessors
/linux-4.1.27/drivers/net/wireless/ath/ath5k/
DKconfig18 PHY: RF5111/2111 RF5112/2112 RF5413/2413
/linux-4.1.27/Documentation/devicetree/bindings/i2c/
Di2c-s3c2410.txt14 a host to SATA PHY controller on an internal bus.
/linux-4.1.27/drivers/net/wireless/rtl818x/
Drtl818x.h241 u8 PHY[4]; /* 0x7c */ member
/linux-4.1.27/Documentation/usb/
Dchipidea.txt82 2.3 Enable PHY's wakeup (optional)
/linux-4.1.27/drivers/scsi/ufs/
DKconfig81 accessing the hardware which includes PHY configuration and vendor
/linux-4.1.27/Documentation/devicetree/bindings/clock/
Dpistachio-clock.txt15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
Dmvebu-gated-clock.txt139 30 gephy Gigabit Ethernel PHY
/linux-4.1.27/drivers/net/wireless/rtl818x/rtl8187/
Ddev.c183 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF); in rtl8187_write_phy()
184 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF); in rtl8187_write_phy()
185 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF); in rtl8187_write_phy()
186 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF); in rtl8187_write_phy()
/linux-4.1.27/drivers/scsi/mpt2sas/
Dmpt2sas_scsih.c3052 handle = le16_to_cpu(event_data->PHY[i].AttachedDevHandle); in _scsih_block_io_to_children_attached_directly()
3056 reason_code = event_data->PHY[i].PhyStatus & in _scsih_block_io_to_children_attached_directly()
3440 handle = le16_to_cpu(event_data->PHY[i].AttachedDevHandle); in _scsih_check_topo_delete_events()
3443 reason_code = event_data->PHY[i].PhyStatus & in _scsih_check_topo_delete_events()
5444 handle = le16_to_cpu(event_data->PHY[i].AttachedDevHandle); in _scsih_sas_topology_change_event_debug()
5448 reason_code = event_data->PHY[i].PhyStatus & in _scsih_sas_topology_change_event_debug()
5470 link_rate = event_data->PHY[i].LinkRate >> 4; in _scsih_sas_topology_change_event_debug()
5471 prev_link_rate = event_data->PHY[i].LinkRate & 0xF; in _scsih_sas_topology_change_event_debug()
5557 reason_code = event_data->PHY[i].PhyStatus & in _scsih_sas_topology_change_event()
5559 if ((event_data->PHY[i].PhyStatus & in _scsih_sas_topology_change_event()
[all …]
/linux-4.1.27/drivers/scsi/mpt3sas/
Dmpt3sas_scsih.c2732 handle = le16_to_cpu(event_data->PHY[i].AttachedDevHandle); in _scsih_block_io_to_children_attached_directly()
2735 reason_code = event_data->PHY[i].PhyStatus & in _scsih_block_io_to_children_attached_directly()
3135 handle = le16_to_cpu(event_data->PHY[i].AttachedDevHandle); in _scsih_check_topo_delete_events()
3138 reason_code = event_data->PHY[i].PhyStatus & in _scsih_check_topo_delete_events()
5016 handle = le16_to_cpu(event_data->PHY[i].AttachedDevHandle); in _scsih_sas_topology_change_event_debug()
5020 reason_code = event_data->PHY[i].PhyStatus & in _scsih_sas_topology_change_event_debug()
5042 link_rate = event_data->PHY[i].LinkRate >> 4; in _scsih_sas_topology_change_event_debug()
5043 prev_link_rate = event_data->PHY[i].LinkRate & 0xF; in _scsih_sas_topology_change_event_debug()
5128 reason_code = event_data->PHY[i].PhyStatus & in _scsih_sas_topology_change_event()
5130 if ((event_data->PHY[i].PhyStatus & in _scsih_sas_topology_change_event()
[all …]
/linux-4.1.27/Documentation/networking/caif/
DLinux-CAIF.txt67 - Clients must call configuration function to add PHY layer.
/linux-4.1.27/Documentation/cris/
DREADME62 including multiple high speed serial ports and an integrated USB 1.1 PHY.
/linux-4.1.27/arch/arm/mach-s3c64xx/
DKconfig81 Common setup code for USB PHY controller
/linux-4.1.27/drivers/net/wireless/rtl818x/rtl8180/
Ddev.c203 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80); in rtl8180_write_phy()
205 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf); in rtl8180_write_phy()
206 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF)) in rtl8180_write_phy()
/linux-4.1.27/drivers/pinctrl/
Dpinctrl-falcon.c167 MFP_FALCON(GPIO88, PHY, GPIO, NONE, NONE),
/linux-4.1.27/Documentation/driver-model/
Ddevres.txt319 PHY
/linux-4.1.27/drivers/message/fusion/lsi/
Dmpi_history.txt364 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY.
387 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode.
450 * Added OwnerDevHandle and Flags field to SAS PHY Page 0.
/linux-4.1.27/drivers/usb/host/
DKconfig206 This driver depends on OTG driver for PHY initialization,
209 has an external PHY.
467 module because it lacks a proper PHY abstraction.
/linux-4.1.27/Documentation/devicetree/bindings/powerpc/fsl/
Dmpc5200.txt168 - phy-handle - Contains a phandle to an Ethernet PHY.
Dfman.txt365 The MDIO is a bus to which the PHY devices are connected.
/linux-4.1.27/arch/powerpc/platforms/
DKconfig342 chip-selects, Ethernet/USB PHY's power and various other small
/linux-4.1.27/net/
DKconfig97 bool "Timestamping in PHY devices"
/linux-4.1.27/drivers/scsi/mpt3sas/mpi/
Dmpi2_ioc.h901 PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /*0x0C */ member
Dmpi2_cnfg.h2163 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */ member
/linux-4.1.27/arch/cris/arch-v32/drivers/
DKconfig12 bool "PHY not present"
/linux-4.1.27/drivers/scsi/mpt2sas/mpi/
Dmpi2_ioc.h904 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ member
Dmpi2_cnfg.h2076 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ member
/linux-4.1.27/Documentation/nfc/
Dnfc-hci.txt122 PHY Management
/linux-4.1.27/arch/blackfin/
DKconfig1292 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1296 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
/linux-4.1.27/
DMAINTAINERS3875 ETHERNET PHY LIBRARY
4349 GENERIC PHY FRAMEWORK
8602 SAMSUNG USB2 PHY DRIVER
10377 USB PHY LAYER
DCREDITS2159 D: PCILynx patch to work with 1394a PHY and without local RAM