1============================================================================= 2Freescale Frame Manager Device Bindings 3 4CONTENTS 5 - FMan Node 6 - FMan Port Node 7 - FMan MURAM Node 8 - FMan dTSEC/XGEC/mEMAC Node 9 - FMan IEEE 1588 Node 10 - FMan MDIO Node 11 - Example 12 13============================================================================= 14FMan Node 15 16DESCRIPTION 17 18Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs, 19etc.) the FMan node will have child nodes for each of them. 20 21PROPERTIES 22 23- compatible 24 Usage: required 25 Value type: <stringlist> 26 Definition: Must include "fsl,fman" 27 FMan version can be determined via FM_IP_REV_1 register in the 28 FMan block. The offset is 0xc4 from the beginning of the 29 Frame Processing Manager memory map (0xc3000 from the 30 beginning of the FMan node). 31 32- cell-index 33 Usage: required 34 Value type: <u32> 35 Definition: Specifies the index of the FMan unit. 36 37 The cell-index value may be used by the SoC, to identify the 38 FMan unit in the SoC memory map. In the table bellow, 39 there's a description of the cell-index use in each SoC: 40 41 - P1023: 42 register[bit] FMan unit cell-index 43 ============================================================ 44 DEVDISR[1] 1 0 45 46 - P2041, P3041, P4080 P5020, P5040: 47 register[bit] FMan unit cell-index 48 ============================================================ 49 DCFG_DEVDISR2[6] 1 0 50 DCFG_DEVDISR2[14] 2 1 51 (Second FM available only in P4080 and P5040) 52 53 - B4860, T1040, T2080, T4240: 54 register[bit] FMan unit cell-index 55 ============================================================ 56 DCFG_CCSR_DEVDISR2[24] 1 0 57 DCFG_CCSR_DEVDISR2[25] 2 1 58 (Second FM available only in T4240) 59 60 DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in 61 the specific SoC "Device Configuration/Pin Control" Memory 62 Map. 63 64- reg 65 Usage: required 66 Value type: <prop-encoded-array> 67 Definition: A standard property. Specifies the offset of the 68 following configuration registers: 69 - BMI configuration registers. 70 - QMI configuration registers. 71 - DMA configuration registers. 72 - FPM configuration registers. 73 - FMan controller configuration registers. 74 75- ranges 76 Usage: required 77 Value type: <prop-encoded-array> 78 Definition: A standard property. 79 80- clocks 81 Usage: required 82 Value type: <prop-encoded-array> 83 Definition: phandle for the fman input clock. 84 85- clock-names 86 usage: required 87 Value type: <stringlist> 88 Definition: "fmanclk" for the fman input clock. 89 90- interrupts 91 Usage: required 92 Value type: <prop-encoded-array> 93 Definition: A pair of IRQs are specified in this property. 94 The first element is associated with the event interrupts and 95 the second element is associated with the error interrupts. 96 97- fsl,qman-channel-range 98 Usage: required 99 Value type: <prop-encoded-array> 100 Definition: Specifies the range of the available dedicated 101 channels in the FMan. The first cell specifies the beginning 102 of the range and the second cell specifies the number of 103 channels. 104 Further information available at: 105 "Work Queue (WQ) Channel Assignments in the QMan" section 106 in DPAA Reference Manual. 107 108- fsl,qman 109- fsl,bman 110 Usage: required 111 Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt 112 113============================================================================= 114FMan MURAM Node 115 116DESCRIPTION 117 118FMan Internal memory - shared between all the FMan modules. 119It contains data structures that are common and written to or read by 120the modules. 121FMan internal memory is split into the following parts: 122 Packet buffering (Tx/Rx FIFOs) 123 Frames internal context 124 125PROPERTIES 126 127- compatible 128 Usage: required 129 Value type: <stringlist> 130 Definition: Must include "fsl,fman-muram" 131 132- ranges 133 Usage: required 134 Value type: <prop-encoded-array> 135 Definition: A standard property. 136 Specifies the multi-user memory offset and the size within 137 the FMan. 138 139EXAMPLE 140 141muram@0 { 142 compatible = "fsl,fman-muram"; 143 ranges = <0 0x000000 0x28000>; 144}; 145 146============================================================================= 147FMan Port Node 148 149DESCRIPTION 150 151The Frame Manager (FMan) supports several types of hardware ports: 152 Ethernet receiver (RX) 153 Ethernet transmitter (TX) 154 Offline/Host command (O/H) 155 156PROPERTIES 157 158- compatible 159 Usage: required 160 Value type: <stringlist> 161 Definition: A standard property. 162 Must include one of the following: 163 - "fsl,fman-v2-port-oh" for FManV2 OH ports 164 - "fsl,fman-v2-port-rx" for FManV2 RX ports 165 - "fsl,fman-v2-port-tx" for FManV2 TX ports 166 - "fsl,fman-v3-port-oh" for FManV3 OH ports 167 - "fsl,fman-v3-port-rx" for FManV3 RX ports 168 - "fsl,fman-v3-port-tx" for FManV3 TX ports 169 170- cell-index 171 Usage: required 172 Value type: <u32> 173 Definition: Specifies the hardware port id. 174 Each hardware port on the FMan has its own hardware PortID. 175 Super set of all hardware Port IDs available at FMan Reference 176 Manual under "FMan Hardware Ports in Freescale Devices" table. 177 178 Each hardware port is assigned a 4KB, port-specific page in 179 the FMan hardware port memory region (which is part of the 180 FMan memory map). The first 4 KB in the FMan hardware ports 181 memory region is used for what are called common registers. 182 The subsequent 63 4KB pages are allocated to the hardware 183 ports. 184 The page of a specific port is determined by the cell-index. 185 186- reg 187 Usage: required 188 Value type: <prop-encoded-array> 189 Definition: There is one reg region describing the port 190 configuration registers. 191 192EXAMPLE 193 194port@a8000 { 195 cell-index = <0x28>; 196 compatible = "fsl,fman-v2-port-tx"; 197 reg = <0xa8000 0x1000>; 198}; 199 200port@88000 { 201 cell-index = <0x8>; 202 compatible = "fsl,fman-v2-port-rx"; 203 reg = <0x88000 0x1000>; 204}; 205 206port@81000 { 207 cell-index = <0x1>; 208 compatible = "fsl,fman-v2-port-oh"; 209 reg = <0x81000 0x1000>; 210}; 211 212============================================================================= 213FMan dTSEC/XGEC/mEMAC Node 214 215DESCRIPTION 216 217mEMAC/dTSEC/XGEC are the Ethernet network interfaces 218 219PROPERTIES 220 221- compatible 222 Usage: required 223 Value type: <stringlist> 224 Definition: A standard property. 225 Must include one of the following: 226 - "fsl,fman-dtsec" for dTSEC MAC 227 - "fsl,fman-xgec" for XGEC MAC 228 - "fsl,fman-memac for mEMAC MAC 229 230- cell-index 231 Usage: required 232 Value type: <u32> 233 Definition: Specifies the MAC id. 234 235 The cell-index value may be used by the FMan or the SoC, to 236 identify the MAC unit in the FMan (or SoC) memory map. 237 In the tables bellow there's a description of the cell-index 238 use, there are two tables, one describes the use of cell-index 239 by the FMan, the second describes the use by the SoC: 240 241 1. FMan Registers 242 243 FManV2: 244 register[bit] MAC cell-index 245 ============================================================ 246 FM_EPI[16] XGEC 8 247 FM_EPI[16+n] dTSECn n-1 248 FM_NPI[11+n] dTSECn n-1 249 n = 1,..,5 250 251 FManV3: 252 register[bit] MAC cell-index 253 ============================================================ 254 FM_EPI[16+n] mEMACn n-1 255 FM_EPI[25] mEMAC10 9 256 257 FM_NPI[11+n] mEMACn n-1 258 FM_NPI[10] mEMAC10 9 259 FM_NPI[11] mEMAC9 8 260 n = 1,..8 261 262 FM_EPI and FM_NPI are located in the FMan memory map. 263 264 2. SoC registers: 265 266 - P2041, P3041, P4080 P5020, P5040: 267 register[bit] FMan MAC cell 268 Unit index 269 ============================================================ 270 DCFG_DEVDISR2[7] 1 XGEC 8 271 DCFG_DEVDISR2[7+n] 1 dTSECn n-1 272 DCFG_DEVDISR2[15] 2 XGEC 8 273 DCFG_DEVDISR2[15+n] 2 dTSECn n-1 274 n = 1,..5 275 276 - T1040, T2080, T4240, B4860: 277 register[bit] FMan MAC cell 278 Unit index 279 ============================================================ 280 DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1 281 DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1 282 n = 1,..6,9,10 283 284 EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in 285 the specific SoC "Device Configuration/Pin Control" Memory 286 Map. 287 288- reg 289 Usage: required 290 Value type: <prop-encoded-array> 291 Definition: A standard property. 292 293- fsl,fman-ports 294 Usage: required 295 Value type: <prop-encoded-array> 296 Definition: An array of two phandles - the first references is 297 the FMan RX port and the second is the TX port used by this 298 MAC. 299 300- ptp-timer 301 Usage required 302 Value type: <phandle> 303 Definition: A phandle for 1EEE1588 timer. 304 305EXAMPLE 306 307fman1_tx28: port@a8000 { 308 cell-index = <0x28>; 309 compatible = "fsl,fman-v2-port-tx"; 310 reg = <0xa8000 0x1000>; 311}; 312 313fman1_rx8: port@88000 { 314 cell-index = <0x8>; 315 compatible = "fsl,fman-v2-port-rx"; 316 reg = <0x88000 0x1000>; 317}; 318 319ptp-timer: ptp_timer@fe000 { 320 compatible = "fsl,fman-ptp-timer"; 321 reg = <0xfe000 0x1000>; 322}; 323 324ethernet@e0000 { 325 compatible = "fsl,fman-dtsec"; 326 cell-index = <0>; 327 reg = <0xe0000 0x1000>; 328 fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; 329 ptp-timer = <&ptp-timer>; 330}; 331 332============================================================================ 333FMan IEEE 1588 Node 334 335DESCRIPTION 336 337The FMan interface to support IEEE 1588 338 339 340PROPERTIES 341 342- compatible 343 Usage: required 344 Value type: <stringlist> 345 Definition: A standard property. 346 Must include "fsl,fman-ptp-timer". 347 348- reg 349 Usage: required 350 Value type: <prop-encoded-array> 351 Definition: A standard property. 352 353EXAMPLE 354 355ptp-timer@fe000 { 356 compatible = "fsl,fman-ptp-timer"; 357 reg = <0xfe000 0x1000>; 358}; 359 360============================================================================= 361FMan MDIO Node 362 363DESCRIPTION 364 365The MDIO is a bus to which the PHY devices are connected. 366 367PROPERTIES 368 369- compatible 370 Usage: required 371 Value type: <stringlist> 372 Definition: A standard property. 373 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2. 374 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2. 375 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from 376 FMan v3. 377 378- reg 379 Usage: required 380 Value type: <prop-encoded-array> 381 Definition: A standard property. 382 383- bus-frequency 384 Usage: optional 385 Value type: <u32> 386 Definition: Specifies the external MDIO bus clock speed to 387 be used, if different from the standard 2.5 MHz. 388 This may be due to the standard speed being unsupported (e.g. 389 due to a hardware problem), or to advertise that all relevant 390 components in the system support a faster speed. 391 392- interrupts 393 Usage: required for external MDIO 394 Value type: <prop-encoded-array> 395 Definition: Event interrupt of external MDIO controller. 396 397- fsl,fman-internal-mdio 398 Usage: required for internal MDIO 399 Value type: boolean 400 Definition: Fman has internal MDIO for internal PCS(Physical 401 Coding Sublayer) PHYs and external MDIO for external PHYs. 402 The settings and programming routines for internal/external 403 MDIO are different. Must be included for internal MDIO. 404 405EXAMPLE 406 407Example for FMan v2 external MDIO: 408 409mdio@f1000 { 410 compatible = "fsl,fman-xmdio"; 411 reg = <0xf1000 0x1000>; 412 interrupts = <101 2 0 0>; 413}; 414 415Example for FMan v3 internal MDIO: 416 417mdio@f1000 { 418 compatible = "fsl,fman-memac-mdio"; 419 reg = <0xf1000 0x1000>; 420 fsl,fman-internal-mdio; 421}; 422 423============================================================================= 424Example 425 426fman@400000 { 427 #address-cells = <1>; 428 #size-cells = <1>; 429 cell-index = <1>; 430 compatible = "fsl,fman" 431 ranges = <0 0x400000 0x100000>; 432 reg = <0x400000 0x100000>; 433 clocks = <&fman_clk>; 434 clock-names = "fmanclk"; 435 interrupts = < 436 96 2 0 0 437 16 2 1 1>; 438 fsl,qman-channel-range = <0x40 0xc>; 439 440 muram@0 { 441 compatible = "fsl,fman-muram"; 442 reg = <0x0 0x28000>; 443 }; 444 445 port@81000 { 446 cell-index = <1>; 447 compatible = "fsl,fman-v2-port-oh"; 448 reg = <0x81000 0x1000>; 449 }; 450 451 port@82000 { 452 cell-index = <2>; 453 compatible = "fsl,fman-v2-port-oh"; 454 reg = <0x82000 0x1000>; 455 }; 456 457 port@83000 { 458 cell-index = <3>; 459 compatible = "fsl,fman-v2-port-oh"; 460 reg = <0x83000 0x1000>; 461 }; 462 463 port@84000 { 464 cell-index = <4>; 465 compatible = "fsl,fman-v2-port-oh"; 466 reg = <0x84000 0x1000>; 467 }; 468 469 port@85000 { 470 cell-index = <5>; 471 compatible = "fsl,fman-v2-port-oh"; 472 reg = <0x85000 0x1000>; 473 }; 474 475 port@86000 { 476 cell-index = <6>; 477 compatible = "fsl,fman-v2-port-oh"; 478 reg = <0x86000 0x1000>; 479 }; 480 481 fman1_rx_0x8: port@88000 { 482 cell-index = <0x8>; 483 compatible = "fsl,fman-v2-port-rx"; 484 reg = <0x88000 0x1000>; 485 }; 486 487 fman1_rx_0x9: port@89000 { 488 cell-index = <0x9>; 489 compatible = "fsl,fman-v2-port-rx"; 490 reg = <0x89000 0x1000>; 491 }; 492 493 fman1_rx_0xa: port@8a000 { 494 cell-index = <0xa>; 495 compatible = "fsl,fman-v2-port-rx"; 496 reg = <0x8a000 0x1000>; 497 }; 498 499 fman1_rx_0xb: port@8b000 { 500 cell-index = <0xb>; 501 compatible = "fsl,fman-v2-port-rx"; 502 reg = <0x8b000 0x1000>; 503 }; 504 505 fman1_rx_0xc: port@8c000 { 506 cell-index = <0xc>; 507 compatible = "fsl,fman-v2-port-rx"; 508 reg = <0x8c000 0x1000>; 509 }; 510 511 fman1_rx_0x10: port@90000 { 512 cell-index = <0x10>; 513 compatible = "fsl,fman-v2-port-rx"; 514 reg = <0x90000 0x1000>; 515 }; 516 517 fman1_tx_0x28: port@a8000 { 518 cell-index = <0x28>; 519 compatible = "fsl,fman-v2-port-tx"; 520 reg = <0xa8000 0x1000>; 521 }; 522 523 fman1_tx_0x29: port@a9000 { 524 cell-index = <0x29>; 525 compatible = "fsl,fman-v2-port-tx"; 526 reg = <0xa9000 0x1000>; 527 }; 528 529 fman1_tx_0x2a: port@aa000 { 530 cell-index = <0x2a>; 531 compatible = "fsl,fman-v2-port-tx"; 532 reg = <0xaa000 0x1000>; 533 }; 534 535 fman1_tx_0x2b: port@ab000 { 536 cell-index = <0x2b>; 537 compatible = "fsl,fman-v2-port-tx"; 538 reg = <0xab000 0x1000>; 539 }; 540 541 fman1_tx_0x2c: port@ac0000 { 542 cell-index = <0x2c>; 543 compatible = "fsl,fman-v2-port-tx"; 544 reg = <0xac000 0x1000>; 545 }; 546 547 fman1_tx_0x30: port@b0000 { 548 cell-index = <0x30>; 549 compatible = "fsl,fman-v2-port-tx"; 550 reg = <0xb0000 0x1000>; 551 }; 552 553 ethernet@e0000 { 554 compatible = "fsl,fman-dtsec"; 555 cell-index = <0>; 556 reg = <0xe0000 0x1000>; 557 fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>; 558 }; 559 560 ethernet@e2000 { 561 compatible = "fsl,fman-dtsec"; 562 cell-index = <1>; 563 reg = <0xe2000 0x1000>; 564 fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>; 565 }; 566 567 ethernet@e4000 { 568 compatible = "fsl,fman-dtsec"; 569 cell-index = <2>; 570 reg = <0xe4000 0x1000>; 571 fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>; 572 }; 573 574 ethernet@e6000 { 575 compatible = "fsl,fman-dtsec"; 576 cell-index = <3>; 577 reg = <0xe6000 0x1000>; 578 fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>; 579 }; 580 581 ethernet@e8000 { 582 compatible = "fsl,fman-dtsec"; 583 cell-index = <4>; 584 reg = <0xf0000 0x1000>; 585 fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>; 586 587 ethernet@f0000 { 588 cell-index = <8>; 589 compatible = "fsl,fman-xgec"; 590 reg = <0xf0000 0x1000>; 591 fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>; 592 }; 593 594 ptp-timer@fe000 { 595 compatible = "fsl,fman-ptp-timer"; 596 reg = <0xfe000 0x1000>; 597 }; 598 599 mdio@f1000 { 600 compatible = "fsl,fman-xmdio"; 601 reg = <0xf1000 0x1000>; 602 interrupts = <101 2 0 0>; 603 }; 604}; 605