1/* 2 * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de> 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/input/input.h> 14#include <dt-bindings/pwm/pwm.h> 15 16/ { 17 aliases { 18 can0 = &can2; 19 can1 = &can1; 20 ethernet0 = &fec; 21 lcdif_23bit_pins_a = &pinctrl_disp0_1; 22 lcdif_24bit_pins_a = &pinctrl_disp0_2; 23 pwm0 = &pwm1; 24 pwm1 = &pwm2; 25 reg_can_xcvr = ®_can_xcvr; 26 stk5led = &user_led; 27 usbotg = &usbotg; 28 sdhc0 = &usdhc1; 29 sdhc1 = &usdhc2; 30 }; 31 32 memory { 33 reg = <0 0>; /* will be filled by U-Boot */ 34 }; 35 36 clocks { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 mclk: clock@0 { 40 compatible = "fixed-clock"; 41 reg = <0>; 42 #clock-cells = <0>; 43 clock-frequency = <27000000>; 44 }; 45 }; 46 47 gpio-keys { 48 compatible = "gpio-keys"; 49 50 power { 51 label = "Power Button"; 52 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; 53 linux,code = <KEY_POWER>; 54 gpio-key,wakeup; 55 }; 56 }; 57 58 leds { 59 compatible = "gpio-leds"; 60 61 user_led: user { 62 label = "Heartbeat"; 63 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 64 linux,default-trigger = "heartbeat"; 65 }; 66 }; 67 68 regulators { 69 compatible = "simple-bus"; 70 #address-cells = <1>; 71 #size-cells = <0>; 72 73 reg_3v3_etn: regulator@0 { 74 compatible = "regulator-fixed"; 75 reg = <0>; 76 regulator-name = "3V3_ETN"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_etnphy_power>; 81 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; 82 enable-active-high; 83 }; 84 85 reg_2v5: regulator@1 { 86 compatible = "regulator-fixed"; 87 reg = <1>; 88 regulator-name = "2V5"; 89 regulator-min-microvolt = <2500000>; 90 regulator-max-microvolt = <2500000>; 91 regulator-always-on; 92 }; 93 94 reg_3v3: regulator@2 { 95 compatible = "regulator-fixed"; 96 reg = <2>; 97 regulator-name = "3V3"; 98 regulator-min-microvolt = <3300000>; 99 regulator-max-microvolt = <3300000>; 100 regulator-always-on; 101 }; 102 103 reg_can_xcvr: regulator@3 { 104 compatible = "regulator-fixed"; 105 reg = <3>; 106 regulator-name = "CAN XCVR"; 107 regulator-min-microvolt = <3300000>; 108 regulator-max-microvolt = <3300000>; 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_flexcan_xcvr>; 111 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 112 enable-active-low; 113 }; 114 115 reg_lcd0_pwr: regulator@4 { 116 compatible = "regulator-fixed"; 117 reg = <4>; 118 regulator-name = "LCD0 POWER"; 119 regulator-min-microvolt = <3300000>; 120 regulator-max-microvolt = <3300000>; 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pinctrl_lcd0_pwr>; 123 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; 124 enable-active-high; 125 regulator-boot-on; 126 regulator-always-on; 127 }; 128 129 reg_lcd1_pwr: regulator@5 { 130 compatible = "regulator-fixed"; 131 reg = <5>; 132 regulator-name = "LCD1 POWER"; 133 regulator-min-microvolt = <3300000>; 134 regulator-max-microvolt = <3300000>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_lcd1_pwr>; 137 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; 138 enable-active-high; 139 regulator-boot-on; 140 regulator-always-on; 141 }; 142 143 reg_usbh1_vbus: regulator@6 { 144 compatible = "regulator-fixed"; 145 reg = <6>; 146 regulator-name = "usbh1_vbus"; 147 regulator-min-microvolt = <5000000>; 148 regulator-max-microvolt = <5000000>; 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_usbh1_vbus>; 151 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; 152 enable-active-high; 153 }; 154 155 reg_usbotg_vbus: regulator@7 { 156 compatible = "regulator-fixed"; 157 reg = <7>; 158 regulator-name = "usbotg_vbus"; 159 regulator-min-microvolt = <5000000>; 160 regulator-max-microvolt = <5000000>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_usbotg_vbus>; 163 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 164 enable-active-high; 165 }; 166 }; 167 168 sound { 169 compatible = "karo,imx6qdl-tx6qdl-sgtl5000", 170 "fsl,imx-audio-sgtl5000"; 171 model = "sgtl5000-audio"; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_audmux>; 174 ssi-controller = <&ssi1>; 175 audio-codec = <&sgtl5000>; 176 audio-routing = 177 "MIC_IN", "Mic Jack", 178 "Mic Jack", "Mic Bias", 179 "Headphone Jack", "HP_OUT"; 180 mux-int-port = <1>; 181 mux-ext-port = <5>; 182 }; 183}; 184 185&audmux { 186 status = "okay"; 187}; 188 189&can1 { 190 pinctrl-names = "default"; 191 pinctrl-0 = <&pinctrl_flexcan1>; 192 xceiver-supply = <®_can_xcvr>; 193 status = "okay"; 194}; 195 196&can2 { 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_flexcan2>; 199 xceiver-supply = <®_can_xcvr>; 200 status = "okay"; 201}; 202 203&ecspi1 { 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_ecspi1>; 206 fsl,spi-num-chipselects = <2>; 207 cs-gpios = < 208 &gpio2 30 GPIO_ACTIVE_HIGH 209 &gpio3 19 GPIO_ACTIVE_HIGH 210 >; 211 status = "okay"; 212 213 spidev0: spi@0 { 214 compatible = "spidev"; 215 reg = <0>; 216 spi-max-frequency = <54000000>; 217 }; 218 219 spidev1: spi@1 { 220 compatible = "spidev"; 221 reg = <1>; 222 spi-max-frequency = <54000000>; 223 }; 224}; 225 226&fec { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_enet>; 229 phy-mode = "rmii"; 230 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; 231 phy-supply = <®_3v3_etn>; 232 status = "okay"; 233}; 234 235&gpmi { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_gpmi_nand>; 238 nand-on-flash-bbt; 239 fsl,no-blockmark-swap; 240 status = "okay"; 241}; 242 243&i2c1 { 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_i2c1>; 246 clock-frequency = <400000>; 247 status = "okay"; 248 249 ds1339: rtc@68 { 250 compatible = "dallas,ds1339"; 251 reg = <0x68>; 252 }; 253}; 254 255&i2c3 { 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_i2c3>; 258 clock-frequency = <400000>; 259 status = "okay"; 260 261 sgtl5000: sgtl5000@0a { 262 compatible = "fsl,sgtl5000"; 263 reg = <0x0a>; 264 VDDA-supply = <®_2v5>; 265 VDDIO-supply = <®_3v3>; 266 clocks = <&mclk>; 267 }; 268 269 polytouch: edt-ft5x06@38 { 270 compatible = "edt,edt-ft5x06"; 271 reg = <0x38>; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_edt_ft5x06>; 274 interrupt-parent = <&gpio6>; 275 interrupts = <15 0>; 276 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; 277 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; 278 linux,wakeup; 279 }; 280 281 touchscreen: tsc2007@48 { 282 compatible = "ti,tsc2007"; 283 reg = <0x48>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_tsc2007>; 286 interrupt-parent = <&gpio3>; 287 interrupts = <26 0>; 288 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; 289 ti,x-plate-ohms = <660>; 290 linux,wakeup; 291 }; 292}; 293 294&iomuxc { 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pinctrl_hog>; 297 298 imx6qdl-tx6 { 299 pinctrl_hog: hoggrp { 300 fsl,pins = < 301 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */ 302 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ 303 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ 304 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ 305 >; 306 }; 307 308 pinctrl_audmux: audmuxgrp { 309 fsl,pins = < 310 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */ 311 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */ 312 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */ 313 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */ 314 >; 315 }; 316 317 pinctrl_disp0_1: disp0grp-1 { 318 fsl,pins = < 319 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 320 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 321 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 322 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 323 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */ 324 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 325 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 326 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 327 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 328 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 329 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 330 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 331 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 332 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 333 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 334 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 335 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 336 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 337 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 338 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 339 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 340 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 341 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 342 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 343 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 344 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 345 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 346 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 347 >; 348 }; 349 350 pinctrl_disp0_2: disp0grp-2 { 351 fsl,pins = < 352 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 353 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 354 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 355 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 356 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 357 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 358 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 359 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 360 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 361 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 362 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 363 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 364 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 365 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 366 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 367 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 368 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 369 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 370 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 371 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 372 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 373 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 374 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 375 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 376 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 377 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 378 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 379 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 380 >; 381 }; 382 383 pinctrl_ecspi1: ecspi1grp { 384 fsl,pins = < 385 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0 386 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0 387 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0 388 MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0 389 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */ 390 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */ 391 >; 392 }; 393 394 pinctrl_edt_ft5x06: edt-ft5x06grp { 395 fsl,pins = < 396 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */ 397 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ 398 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ 399 >; 400 }; 401 402 pinctrl_enet: enetgrp { 403 fsl,pins = < 404 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 405 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 406 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 407 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 408 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 409 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 410 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 411 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 412 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 413 >; 414 }; 415 416 pinctrl_etnphy_power: etnphy-pwrgrp { 417 fsl,pins = < 418 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ 419 >; 420 }; 421 422 pinctrl_flexcan1: flexcan1grp { 423 fsl,pins = < 424 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 425 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 426 >; 427 }; 428 429 pinctrl_flexcan2: flexcan2grp { 430 fsl,pins = < 431 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 432 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 433 >; 434 }; 435 436 pinctrl_flexcan_xcvr: flexcan-xcvrgrp { 437 fsl,pins = < 438 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */ 439 >; 440 }; 441 442 pinctrl_gpmi_nand: gpminandgrp { 443 fsl,pins = < 444 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 445 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 446 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 447 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 448 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 449 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 450 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 451 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 452 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 453 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 454 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 455 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 456 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 457 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 458 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 459 >; 460 }; 461 462 pinctrl_i2c1: i2c1grp { 463 fsl,pins = < 464 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 465 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 466 >; 467 }; 468 469 pinctrl_i2c3: i2c3grp { 470 fsl,pins = < 471 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 472 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 473 >; 474 }; 475 476 pinctrl_kpp: kppgrp { 477 fsl,pins = < 478 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1 479 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1 480 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1 481 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1 482 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1 483 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1 484 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1 485 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1 486 >; 487 }; 488 489 pinctrl_lcd0_pwr: lcd0-pwrgrp { 490 fsl,pins = < 491 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */ 492 >; 493 }; 494 495 pinctrl_lcd1_pwr: lcd1-pwrgrp { 496 fsl,pins = < 497 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */ 498 >; 499 }; 500 501 pinctrl_pwm1: pwm1grp { 502 fsl,pins = < 503 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 504 >; 505 }; 506 507 pinctrl_pwm2: pwm2grp { 508 fsl,pins = < 509 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 510 >; 511 }; 512 513 pinctrl_tsc2007: tsc2007grp { 514 fsl,pins = < 515 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */ 516 >; 517 }; 518 519 pinctrl_uart1: uart1grp { 520 fsl,pins = < 521 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 522 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 523 >; 524 }; 525 526 pinctrl_uart1_rtscts: uart1_rtsctsgrp { 527 fsl,pins = < 528 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1 529 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1 530 >; 531 }; 532 533 pinctrl_uart2: uart2grp { 534 fsl,pins = < 535 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 536 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 537 >; 538 }; 539 540 pinctrl_uart2_rtscts: uart2_rtsctsgrp { 541 fsl,pins = < 542 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 543 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 544 >; 545 }; 546 547 pinctrl_uart3: uart3grp { 548 fsl,pins = < 549 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 550 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 551 >; 552 }; 553 554 pinctrl_uart3_rtscts: uart3_rtsctsgrp { 555 fsl,pins = < 556 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1 557 MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1 558 >; 559 }; 560 561 pinctrl_usbh1_vbus: usbh1-vbusgrp { 562 fsl,pins = < 563 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */ 564 >; 565 }; 566 567 pinctrl_usbotg: usbotggrp { 568 fsl,pins = < 569 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059 570 >; 571 }; 572 573 pinctrl_usbotg_vbus: usbotg-vbusgrp { 574 fsl,pins = < 575 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */ 576 >; 577 }; 578 579 pinctrl_usdhc1: usdhc1grp { 580 fsl,pins = < 581 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 582 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 583 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 584 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 585 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 586 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 587 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ 588 >; 589 }; 590 591 pinctrl_usdhc2: usdhc2grp { 592 fsl,pins = < 593 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1 594 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1 595 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1 596 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1 597 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1 598 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1 599 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */ 600 >; 601 }; 602 }; 603}; 604 605&kpp { 606 pinctrl-names = "default"; 607 pinctrl-0 = <&pinctrl_kpp>; 608 /* sample keymap */ 609 /* row/col 0,1 are mapped to KPP row/col 6,7 */ 610 linux,keymap = < 611 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */ 612 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */ 613 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */ 614 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */ 615 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */ 616 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */ 617 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */ 618 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */ 619 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */ 620 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */ 621 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */ 622 >; 623 status = "okay"; 624}; 625 626&pwm1 { 627 pinctrl-names = "default"; 628 pinctrl-0 = <&pinctrl_pwm1>; 629 #pwm-cells = <3>; 630 status = "disabled"; 631}; 632 633&pwm2 { 634 pinctrl-names = "default"; 635 pinctrl-0 = <&pinctrl_pwm2>; 636 #pwm-cells = <3>; 637 status = "okay"; 638}; 639 640&ssi1 { 641 status = "okay"; 642}; 643 644&uart1 { 645 pinctrl-names = "default"; 646 pinctrl-0 = <&pinctrl_uart1>; 647 status = "okay"; 648}; 649 650&uart2 { 651 pinctrl-names = "default"; 652 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; 653 status = "okay"; 654}; 655 656&uart3 { 657 pinctrl-names = "default"; 658 pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; 659 status = "okay"; 660}; 661 662&usbh1 { 663 vbus-supply = <®_usbh1_vbus>; 664 dr_mode = "host"; 665 disable-over-current; 666 status = "okay"; 667}; 668 669&usbotg { 670 vbus-supply = <®_usbotg_vbus>; 671 pinctrl-names = "default"; 672 pinctrl-0 = <&pinctrl_usbotg>; 673 dr_mode = "peripheral"; 674 disable-over-current; 675 status = "okay"; 676}; 677 678&usdhc1 { 679 pinctrl-names = "default"; 680 pinctrl-0 = <&pinctrl_usdhc1>; 681 bus-width = <4>; 682 no-1-8-v; 683 cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; 684 fsl,wp-controller; 685 status = "okay"; 686}; 687 688&usdhc2 { 689 pinctrl-names = "default"; 690 pinctrl-0 = <&pinctrl_usdhc2>; 691 bus-width = <4>; 692 no-1-8-v; 693 cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; 694 fsl,wp-controller; 695 status = "okay"; 696}; 697