1Marvell Distributed Switch Architecture Device Tree Bindings
2------------------------------------------------------------
3
4Required properties:
5- compatible		: Should be "marvell,dsa"
6- #address-cells	: Must be 2, first cell is the address on the MDIO bus
7			  and second cell is the address in the switch tree.
8			  Second cell is used only when cascading/chaining.
9- #size-cells		: Must be 0
10- dsa,ethernet		: Should be a phandle to a valid Ethernet device node
11- dsa,mii-bus		: Should be a phandle to a valid MDIO bus device node
12
13Optional properties:
14- interrupts		: property with a value describing the switch
15			  interrupt number (not supported by the driver)
16
17A DSA node can contain multiple switch chips which are therefore child nodes of
18the parent DSA node. The maximum number of allowed child nodes is 4
19(DSA_MAX_SWITCHES).
20Each of these switch child nodes should have the following required properties:
21
22- reg			: Contains two fields. The first one describes the
23			  address on the MII bus. The second is the switch
24			  number that must be unique in cascaded configurations
25- #address-cells	: Must be 1
26- #size-cells		: Must be 0
27
28A switch child node has the following optional property:
29
30- eeprom-length		: Set to the length of an EEPROM connected to the
31			  switch. Must be set if the switch can not detect
32			  the presence and/or size of a connected EEPROM,
33			  otherwise optional.
34
35A switch may have multiple "port" children nodes
36
37Each port children node must have the following mandatory properties:
38- reg			: Describes the port address in the switch
39- label			: Describes the label associated with this port, special
40			  labels are "cpu" to indicate a CPU port and "dsa" to
41			  indicate an uplink/downlink port.
42
43Note that a port labelled "dsa" will imply checking for the uplink phandle
44described below.
45
46Optionnal property:
47- link			: Should be a phandle to another switch's DSA port.
48			  This property is only used when switches are being
49			  chained/cascaded together.
50
51- phy-handle		: Phandle to a PHY on an external MDIO bus, not the
52			  switch internal one. See
53			  Documentation/devicetree/bindings/net/ethernet.txt
54			  for details.
55
56- phy-mode		: String representing the connection to the designated
57			  PHY node specified by the 'phy-handle' property. See
58			  Documentation/devicetree/bindings/net/ethernet.txt
59			  for details.
60
61Optional subnodes:
62- fixed-link		: Fixed-link subnode describing a link to a non-MDIO
63			  managed entity. See
64			  Documentation/devicetree/bindings/net/fixed-link.txt
65			  for details.
66
67Example:
68
69	dsa@0 {
70		compatible = "marvell,dsa";
71		#address-cells = <2>;
72		#size-cells = <0>;
73
74		interrupts = <10>;
75		dsa,ethernet = <&ethernet0>;
76		dsa,mii-bus = <&mii_bus0>;
77
78		switch@0 {
79			#address-cells = <1>;
80			#size-cells = <0>;
81			reg = <16 0>;	/* MDIO address 16, switch 0 in tree */
82
83			port@0 {
84				reg = <0>;
85				label = "lan1";
86				phy-handle = <&phy0>;
87			};
88
89			port@1 {
90				reg = <1>;
91				label = "lan2";
92			};
93
94			port@5 {
95				reg = <5>;
96				label = "cpu";
97			};
98
99			switch0uplink: port@6 {
100				reg = <6>;
101				label = "dsa";
102				link = <&switch1uplink>;
103			};
104		};
105
106		switch@1 {
107			#address-cells = <1>;
108			#size-cells = <0>;
109			reg = <17 1>;	/* MDIO address 17, switch 1 in tree */
110
111			switch1uplink: port@0 {
112				reg = <0>;
113				label = "dsa";
114				link = <&switch0uplink>;
115			};
116		};
117	};
118