1config MMU
2	def_bool n
3
4config FPU
5	def_bool n
6
7config RWSEM_GENERIC_SPINLOCK
8	def_bool y
9
10config RWSEM_XCHGADD_ALGORITHM
11	def_bool n
12
13config BLACKFIN
14	def_bool y
15	select HAVE_ARCH_KGDB
16	select HAVE_ARCH_TRACEHOOK
17	select HAVE_DYNAMIC_FTRACE
18	select HAVE_FTRACE_MCOUNT_RECORD
19	select HAVE_FUNCTION_GRAPH_TRACER
20	select HAVE_FUNCTION_TRACER
21	select HAVE_IDE
22	select HAVE_KERNEL_GZIP if RAMKERNEL
23	select HAVE_KERNEL_BZIP2 if RAMKERNEL
24	select HAVE_KERNEL_LZMA if RAMKERNEL
25	select HAVE_KERNEL_LZO if RAMKERNEL
26	select HAVE_OPROFILE
27	select HAVE_PERF_EVENTS
28	select ARCH_HAVE_CUSTOM_GPIO_H
29	select ARCH_REQUIRE_GPIOLIB
30	select HAVE_UID16
31	select HAVE_UNDERSCORE_SYMBOL_PREFIX
32	select VIRT_TO_BUS
33	select ARCH_WANT_IPC_PARSE_VERSION
34	select GENERIC_ATOMIC64
35	select GENERIC_IRQ_PROBE
36	select GENERIC_IRQ_SHOW
37	select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
38	select GENERIC_SMP_IDLE_THREAD
39	select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
40	select HAVE_MOD_ARCH_SPECIFIC
41	select MODULES_USE_ELF_RELA
42	select HAVE_DEBUG_STACKOVERFLOW
43
44config GENERIC_CSUM
45	def_bool y
46
47config GENERIC_BUG
48	def_bool y
49	depends on BUG
50
51config ZONE_DMA
52	def_bool y
53
54config FORCE_MAX_ZONEORDER
55	int
56	default "14"
57
58config GENERIC_CALIBRATE_DELAY
59	def_bool y
60
61config LOCKDEP_SUPPORT
62	def_bool y
63
64config STACKTRACE_SUPPORT
65	def_bool y
66
67config TRACE_IRQFLAGS_SUPPORT
68	def_bool y
69
70source "init/Kconfig"
71
72source "kernel/Kconfig.preempt"
73
74source "kernel/Kconfig.freezer"
75
76menu "Blackfin Processor Options"
77
78comment "Processor and Board Settings"
79
80choice
81	prompt "CPU"
82	default BF533
83
84config BF512
85	bool "BF512"
86	help
87	  BF512 Processor Support.
88
89config BF514
90	bool "BF514"
91	help
92	  BF514 Processor Support.
93
94config BF516
95	bool "BF516"
96	help
97	  BF516 Processor Support.
98
99config BF518
100	bool "BF518"
101	help
102	  BF518 Processor Support.
103
104config BF522
105	bool "BF522"
106	help
107	  BF522 Processor Support.
108
109config BF523
110	bool "BF523"
111	help
112	  BF523 Processor Support.
113
114config BF524
115	bool "BF524"
116	help
117	  BF524 Processor Support.
118
119config BF525
120	bool "BF525"
121	help
122	  BF525 Processor Support.
123
124config BF526
125	bool "BF526"
126	help
127	  BF526 Processor Support.
128
129config BF527
130	bool "BF527"
131	help
132	  BF527 Processor Support.
133
134config BF531
135	bool "BF531"
136	help
137	  BF531 Processor Support.
138
139config BF532
140	bool "BF532"
141	help
142	  BF532 Processor Support.
143
144config BF533
145	bool "BF533"
146	help
147	  BF533 Processor Support.
148
149config BF534
150	bool "BF534"
151	help
152	  BF534 Processor Support.
153
154config BF536
155	bool "BF536"
156	help
157	  BF536 Processor Support.
158
159config BF537
160	bool "BF537"
161	help
162	  BF537 Processor Support.
163
164config BF538
165	bool "BF538"
166	help
167	  BF538 Processor Support.
168
169config BF539
170	bool "BF539"
171	help
172	  BF539 Processor Support.
173
174config BF542_std
175	bool "BF542"
176	help
177	  BF542 Processor Support.
178
179config BF542M
180	bool "BF542m"
181	help
182	  BF542 Processor Support.
183
184config BF544_std
185	bool "BF544"
186	help
187	  BF544 Processor Support.
188
189config BF544M
190	bool "BF544m"
191	help
192	  BF544 Processor Support.
193
194config BF547_std
195	bool "BF547"
196	help
197	  BF547 Processor Support.
198
199config BF547M
200	bool "BF547m"
201	help
202	  BF547 Processor Support.
203
204config BF548_std
205	bool "BF548"
206	help
207	  BF548 Processor Support.
208
209config BF548M
210	bool "BF548m"
211	help
212	  BF548 Processor Support.
213
214config BF549_std
215	bool "BF549"
216	help
217	  BF549 Processor Support.
218
219config BF549M
220	bool "BF549m"
221	help
222	  BF549 Processor Support.
223
224config BF561
225	bool "BF561"
226	help
227	  BF561 Processor Support.
228
229config BF609
230	bool "BF609"
231	select CLKDEV_LOOKUP
232	help
233	  BF609 Processor Support.
234
235endchoice
236
237config SMP
238	depends on BF561
239	select TICKSOURCE_CORETMR
240	bool "Symmetric multi-processing support"
241	---help---
242	  This enables support for systems with more than one CPU,
243	  like the dual core BF561. If you have a system with only one
244	  CPU, say N. If you have a system with more than one CPU, say Y.
245
246	  If you don't know what to do here, say N.
247
248config NR_CPUS
249	int
250	depends on SMP
251	default 2 if BF561
252
253config HOTPLUG_CPU
254	bool "Support for hot-pluggable CPUs"
255	depends on SMP
256	default y
257
258config BF_REV_MIN
259	int
260	default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
261	default 2 if (BF537 || BF536 || BF534)
262	default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
263	default 4 if (BF538 || BF539)
264
265config BF_REV_MAX
266	int
267	default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
268	default 3 if (BF537 || BF536 || BF534 || BF54xM)
269	default 5 if (BF561 || BF538 || BF539)
270	default 6 if (BF533 || BF532 || BF531)
271
272choice
273	prompt "Silicon Rev"
274	default BF_REV_0_0 if (BF51x || BF52x || BF60x)
275	default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
276	default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
277
278config BF_REV_0_0
279	bool "0.0"
280	depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
281
282config BF_REV_0_1
283	bool "0.1"
284	depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
285
286config BF_REV_0_2
287	bool "0.2"
288	depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
289
290config BF_REV_0_3
291	bool "0.3"
292	depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
293
294config BF_REV_0_4
295	bool "0.4"
296	depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
297
298config BF_REV_0_5
299	bool "0.5"
300	depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
301
302config BF_REV_0_6
303	bool "0.6"
304	depends on (BF533 || BF532 || BF531)
305
306config BF_REV_ANY
307	bool "any"
308
309config BF_REV_NONE
310	bool "none"
311
312endchoice
313
314config BF53x
315	bool
316	depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
317	default y
318
319config GPIO_ADI
320	def_bool y
321	depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
322
323config PINCTRL
324	def_bool y
325	depends on BF54x || BF60x
326
327config MEM_MT48LC64M4A2FB_7E
328	bool
329	depends on (BFIN533_STAMP)
330	default y
331
332config MEM_MT48LC16M16A2TG_75
333	bool
334	depends on (BFIN533_EZKIT || BFIN561_EZKIT \
335		|| BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
336		|| BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
337		|| BFIN527_BLUETECHNIX_CM)
338	default y
339
340config MEM_MT48LC32M8A2_75
341	bool
342	depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
343	default y
344
345config MEM_MT48LC8M32B2B5_7
346	bool
347	depends on (BFIN561_BLUETECHNIX_CM)
348	default y
349
350config MEM_MT48LC32M16A2TG_75
351	bool
352	depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
353	default y
354
355config MEM_MT48H32M16LFCJ_75
356	bool
357	depends on (BFIN526_EZBRD)
358	default y
359
360config MEM_MT47H64M16
361	bool
362	depends on (BFIN609_EZKIT)
363	default y
364
365source "arch/blackfin/mach-bf518/Kconfig"
366source "arch/blackfin/mach-bf527/Kconfig"
367source "arch/blackfin/mach-bf533/Kconfig"
368source "arch/blackfin/mach-bf561/Kconfig"
369source "arch/blackfin/mach-bf537/Kconfig"
370source "arch/blackfin/mach-bf538/Kconfig"
371source "arch/blackfin/mach-bf548/Kconfig"
372source "arch/blackfin/mach-bf609/Kconfig"
373
374menu "Board customizations"
375
376config CMDLINE_BOOL
377	bool "Default bootloader kernel arguments"
378
379config CMDLINE
380	string "Initial kernel command string"
381	depends on CMDLINE_BOOL
382	default "console=ttyBF0,57600"
383	help
384	  If you don't have a boot loader capable of passing a command line string
385	  to the kernel, you may specify one here. As a minimum, you should specify
386	  the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
387
388config BOOT_LOAD
389	hex "Kernel load address for booting"
390	default "0x1000"
391	range 0x1000 0x20000000
392	help
393	  This option allows you to set the load address of the kernel.
394	  This can be useful if you are on a board which has a small amount
395	  of memory or you wish to reserve some memory at the beginning of
396	  the address space.
397
398	  Note that you need to keep this value above 4k (0x1000) as this
399	  memory region is used to capture NULL pointer references as well
400	  as some core kernel functions.
401
402config PHY_RAM_BASE_ADDRESS
403	hex "Physical RAM Base"
404	default 0x0
405	help
406	  set BF609 FPGA physical SRAM base address
407
408config ROM_BASE
409	hex "Kernel ROM Base"
410	depends on ROMKERNEL
411	default "0x20040040"
412	range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
413	range 0x20000000 0x30000000 if (BF54x || BF561)
414	range 0xB0000000 0xC0000000 if (BF60x)
415	help
416	  Make sure your ROM base does not include any file-header
417	  information that is prepended to the kernel.
418
419	  For example, the bootable U-Boot format (created with
420	  mkimage) has a 64 byte header (0x40).  So while the image
421	  you write to flash might start at say 0x20080000, you have
422	  to add 0x40 to get the kernel's ROM base as it will come
423	  after the header.
424
425comment "Clock/PLL Setup"
426
427config CLKIN_HZ
428	int "Frequency of the crystal on the board in Hz"
429	default "10000000" if BFIN532_IP0X
430	default "11059200" if BFIN533_STAMP
431	default "24576000" if PNAV10
432	default "25000000" # most people use this
433	default "27000000" if BFIN533_EZKIT
434	default "30000000" if BFIN561_EZKIT
435	default "24000000" if BFIN527_AD7160EVAL
436	help
437	  The frequency of CLKIN crystal oscillator on the board in Hz.
438	  Warning: This value should match the crystal on the board. Otherwise,
439	  peripherals won't work properly.
440
441config BFIN_KERNEL_CLOCK
442	bool "Re-program Clocks while Kernel boots?"
443	default n
444	help
445	  This option decides if kernel clocks are re-programed from the
446	  bootloader settings. If the clocks are not set, the SDRAM settings
447	  are also not changed, and the Bootloader does 100% of the hardware
448	  configuration.
449
450config PLL_BYPASS
451	bool "Bypass PLL"
452	depends on BFIN_KERNEL_CLOCK && (!BF60x)
453	default n
454
455config CLKIN_HALF
456	bool "Half Clock In"
457	depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
458	default n
459	help
460	  If this is set the clock will be divided by 2, before it goes to the PLL.
461
462config VCO_MULT
463	int "VCO Multiplier"
464	depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
465	range 1 64
466	default "22" if BFIN533_EZKIT
467	default "45" if BFIN533_STAMP
468	default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
469	default "22" if BFIN533_BLUETECHNIX_CM
470	default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
471	default "20" if (BFIN561_EZKIT || BF609)
472	default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
473	default "25" if BFIN527_AD7160EVAL
474	help
475	  This controls the frequency of the on-chip PLL. This can be between 1 and 64.
476	  PLL Frequency = (Crystal Frequency) * (this setting)
477
478choice
479	prompt "Core Clock Divider"
480	depends on BFIN_KERNEL_CLOCK
481	default CCLK_DIV_1
482	help
483	  This sets the frequency of the core. It can be 1, 2, 4 or 8
484	  Core Frequency = (PLL frequency) / (this setting)
485
486config CCLK_DIV_1
487	bool "1"
488
489config CCLK_DIV_2
490	bool "2"
491
492config CCLK_DIV_4
493	bool "4"
494
495config CCLK_DIV_8
496	bool "8"
497endchoice
498
499config SCLK_DIV
500	int "System Clock Divider"
501	depends on BFIN_KERNEL_CLOCK
502	range 1 15
503	default 4
504	help
505	  This sets the frequency of the system clock (including SDRAM or DDR) on
506	  !BF60x else it set the clock for system buses and provides the
507	  source from which SCLK0 and SCLK1 are derived.
508	  This can be between 1 and 15
509	  System Clock = (PLL frequency) / (this setting)
510
511config SCLK0_DIV
512	int "System Clock0 Divider"
513	depends on BFIN_KERNEL_CLOCK && BF60x
514	range 1 15
515	default 1
516	help
517	  This sets the frequency of the system clock0 for PVP and all other
518	  peripherals not clocked by SCLK1.
519	  This can be between 1 and 15
520	  System Clock0 = (System Clock) / (this setting)
521
522config SCLK1_DIV
523	int "System Clock1 Divider"
524	depends on BFIN_KERNEL_CLOCK && BF60x
525	range 1 15
526	default 1
527	help
528	  This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
529	  This can be between 1 and 15
530	  System Clock1 = (System Clock) / (this setting)
531
532config DCLK_DIV
533	int "DDR Clock Divider"
534	depends on BFIN_KERNEL_CLOCK && BF60x
535	range 1 15
536	default 2
537	help
538	  This sets the frequency of the DDR memory.
539	  This can be between 1 and 15
540	  DDR Clock = (PLL frequency) / (this setting)
541
542choice
543	prompt "DDR SDRAM Chip Type"
544	depends on BFIN_KERNEL_CLOCK
545	depends on BF54x
546	default MEM_MT46V32M16_5B
547
548config MEM_MT46V32M16_6T
549	bool "MT46V32M16_6T"
550
551config MEM_MT46V32M16_5B
552	bool "MT46V32M16_5B"
553endchoice
554
555choice
556	prompt "DDR/SDRAM Timing"
557	depends on BFIN_KERNEL_CLOCK && !BF60x
558	default BFIN_KERNEL_CLOCK_MEMINIT_CALC
559	help
560	  This option allows you to specify Blackfin SDRAM/DDR Timing parameters
561	  The calculated SDRAM timing parameters may not be 100%
562	  accurate - This option is therefore marked experimental.
563
564config BFIN_KERNEL_CLOCK_MEMINIT_CALC
565	bool "Calculate Timings"
566
567config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
568	bool "Provide accurate Timings based on target SCLK"
569	help
570	  Please consult the Blackfin Hardware Reference Manuals as well
571	  as the memory device datasheet.
572	  http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
573endchoice
574
575menu "Memory Init Control"
576	depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
577
578config MEM_DDRCTL0
579	depends on BF54x
580	hex "DDRCTL0"
581	default 0x0
582
583config MEM_DDRCTL1
584	depends on BF54x
585	hex "DDRCTL1"
586	default 0x0
587
588config MEM_DDRCTL2
589	depends on BF54x
590	hex "DDRCTL2"
591	default 0x0
592
593config MEM_EBIU_DDRQUE
594	depends on BF54x
595	hex "DDRQUE"
596	default 0x0
597
598config MEM_SDRRC
599	depends on !BF54x
600	hex "SDRRC"
601	default 0x0
602
603config MEM_SDGCTL
604	depends on !BF54x
605	hex "SDGCTL"
606	default 0x0
607endmenu
608
609#
610# Max & Min Speeds for various Chips
611#
612config MAX_VCO_HZ
613	int
614	default 400000000 if BF512
615	default 400000000 if BF514
616	default 400000000 if BF516
617	default 400000000 if BF518
618	default 400000000 if BF522
619	default 600000000 if BF523
620	default 400000000 if BF524
621	default 600000000 if BF525
622	default 400000000 if BF526
623	default 600000000 if BF527
624	default 400000000 if BF531
625	default 400000000 if BF532
626	default 750000000 if BF533
627	default 500000000 if BF534
628	default 400000000 if BF536
629	default 600000000 if BF537
630	default 533333333 if BF538
631	default 533333333 if BF539
632	default 600000000 if BF542
633	default 533333333 if BF544
634	default 600000000 if BF547
635	default 600000000 if BF548
636	default 533333333 if BF549
637	default 600000000 if BF561
638	default 800000000 if BF609
639
640config MIN_VCO_HZ
641	int
642	default 50000000
643
644config MAX_SCLK_HZ
645	int
646	default 200000000 if BF609
647	default 133333333
648
649config MIN_SCLK_HZ
650	int
651	default 27000000
652
653comment "Kernel Timer/Scheduler"
654
655source kernel/Kconfig.hz
656
657config SET_GENERIC_CLOCKEVENTS
658	bool "Generic clock events"
659	default y
660	select GENERIC_CLOCKEVENTS
661
662menu "Clock event device"
663	depends on GENERIC_CLOCKEVENTS
664config TICKSOURCE_GPTMR0
665	bool "GPTimer0"
666	depends on !SMP
667	select BFIN_GPTIMERS
668
669config TICKSOURCE_CORETMR
670	bool "Core timer"
671	default y
672endmenu
673
674menu "Clock source"
675	depends on GENERIC_CLOCKEVENTS
676config CYCLES_CLOCKSOURCE
677	bool "CYCLES"
678	default y
679	depends on !BFIN_SCRATCH_REG_CYCLES
680	depends on !SMP
681	help
682	  If you say Y here, you will enable support for using the 'cycles'
683	  registers as a clock source.  Doing so means you will be unable to
684	  safely write to the 'cycles' register during runtime.  You will
685	  still be able to read it (such as for performance monitoring), but
686	  writing the registers will most likely crash the kernel.
687
688config GPTMR0_CLOCKSOURCE
689	bool "GPTimer0"
690	select BFIN_GPTIMERS
691	depends on !TICKSOURCE_GPTMR0
692endmenu
693
694comment "Misc"
695
696choice
697	prompt "Blackfin Exception Scratch Register"
698	default BFIN_SCRATCH_REG_RETN
699	help
700	  Select the resource to reserve for the Exception handler:
701	    - RETN: Non-Maskable Interrupt (NMI)
702	    - RETE: Exception Return (JTAG/ICE)
703	    - CYCLES: Performance counter
704
705	  If you are unsure, please select "RETN".
706
707config BFIN_SCRATCH_REG_RETN
708	bool "RETN"
709	help
710	  Use the RETN register in the Blackfin exception handler
711	  as a stack scratch register.  This means you cannot
712	  safely use NMI on the Blackfin while running Linux, but
713	  you can debug the system with a JTAG ICE and use the
714	  CYCLES performance registers.
715
716	  If you are unsure, please select "RETN".
717
718config BFIN_SCRATCH_REG_RETE
719	bool "RETE"
720	help
721	  Use the RETE register in the Blackfin exception handler
722	  as a stack scratch register.  This means you cannot
723	  safely use a JTAG ICE while debugging a Blackfin board,
724	  but you can safely use the CYCLES performance registers
725	  and the NMI.
726
727	  If you are unsure, please select "RETN".
728
729config BFIN_SCRATCH_REG_CYCLES
730	bool "CYCLES"
731	help
732	  Use the CYCLES register in the Blackfin exception handler
733	  as a stack scratch register.  This means you cannot
734	  safely use the CYCLES performance registers on a Blackfin
735	  board at anytime, but you can debug the system with a JTAG
736	  ICE and use the NMI.
737
738	  If you are unsure, please select "RETN".
739
740endchoice
741
742endmenu
743
744
745menu "Blackfin Kernel Optimizations"
746
747comment "Memory Optimizations"
748
749config I_ENTRY_L1
750	bool "Locate interrupt entry code in L1 Memory"
751	default y
752	depends on !SMP
753	help
754	  If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
755	  into L1 instruction memory. (less latency)
756
757config EXCPT_IRQ_SYSC_L1
758	bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
759	default y
760	depends on !SMP
761	help
762	  If enabled, the entire ASM lowlevel exception and interrupt entry code
763	  (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
764	  (less latency)
765
766config DO_IRQ_L1
767	bool "Locate frequently called do_irq dispatcher function in L1 Memory"
768	default y
769	depends on !SMP
770	help
771	  If enabled, the frequently called do_irq dispatcher function is linked
772	  into L1 instruction memory. (less latency)
773
774config CORE_TIMER_IRQ_L1
775	bool "Locate frequently called timer_interrupt() function in L1 Memory"
776	default y
777	depends on !SMP
778	help
779	  If enabled, the frequently called timer_interrupt() function is linked
780	  into L1 instruction memory. (less latency)
781
782config IDLE_L1
783	bool "Locate frequently idle function in L1 Memory"
784	default y
785	depends on !SMP
786	help
787	  If enabled, the frequently called idle function is linked
788	  into L1 instruction memory. (less latency)
789
790config SCHEDULE_L1
791	bool "Locate kernel schedule function in L1 Memory"
792	default y
793	depends on !SMP
794	help
795	  If enabled, the frequently called kernel schedule is linked
796	  into L1 instruction memory. (less latency)
797
798config ARITHMETIC_OPS_L1
799	bool "Locate kernel owned arithmetic functions in L1 Memory"
800	default y
801	depends on !SMP
802	help
803	  If enabled, arithmetic functions are linked
804	  into L1 instruction memory. (less latency)
805
806config ACCESS_OK_L1
807	bool "Locate access_ok function in L1 Memory"
808	default y
809	depends on !SMP
810	help
811	  If enabled, the access_ok function is linked
812	  into L1 instruction memory. (less latency)
813
814config MEMSET_L1
815	bool "Locate memset function in L1 Memory"
816	default y
817	depends on !SMP
818	help
819	  If enabled, the memset function is linked
820	  into L1 instruction memory. (less latency)
821
822config MEMCPY_L1
823	bool "Locate memcpy function in L1 Memory"
824	default y
825	depends on !SMP
826	help
827	  If enabled, the memcpy function is linked
828	  into L1 instruction memory. (less latency)
829
830config STRCMP_L1
831	bool "locate strcmp function in L1 Memory"
832	default y
833	depends on !SMP
834	help
835	  If enabled, the strcmp function is linked
836	  into L1 instruction memory (less latency).
837
838config STRNCMP_L1
839	bool "locate strncmp function in L1 Memory"
840	default y
841	depends on !SMP
842	help
843	  If enabled, the strncmp function is linked
844	  into L1 instruction memory (less latency).
845
846config STRCPY_L1
847	bool "locate strcpy function in L1 Memory"
848	default y
849	depends on !SMP
850	help
851	  If enabled, the strcpy function is linked
852	  into L1 instruction memory (less latency).
853
854config STRNCPY_L1
855	bool "locate strncpy function in L1 Memory"
856	default y
857	depends on !SMP
858	help
859	  If enabled, the strncpy function is linked
860	  into L1 instruction memory (less latency).
861
862config SYS_BFIN_SPINLOCK_L1
863	bool "Locate sys_bfin_spinlock function in L1 Memory"
864	default y
865	depends on !SMP
866	help
867	  If enabled, sys_bfin_spinlock function is linked
868	  into L1 instruction memory. (less latency)
869
870config CACHELINE_ALIGNED_L1
871	bool "Locate cacheline_aligned data to L1 Data Memory"
872	default y if !BF54x
873	default n if BF54x
874	depends on !SMP && !BF531 && !CRC32
875	help
876	  If enabled, cacheline_aligned data is linked
877	  into L1 data memory. (less latency)
878
879config SYSCALL_TAB_L1
880	bool "Locate Syscall Table L1 Data Memory"
881	default n
882	depends on !SMP && !BF531
883	help
884	  If enabled, the Syscall LUT is linked
885	  into L1 data memory. (less latency)
886
887config CPLB_SWITCH_TAB_L1
888	bool "Locate CPLB Switch Tables L1 Data Memory"
889	default n
890	depends on !SMP && !BF531
891	help
892	  If enabled, the CPLB Switch Tables are linked
893	  into L1 data memory. (less latency)
894
895config ICACHE_FLUSH_L1
896	bool "Locate icache flush funcs in L1 Inst Memory"
897	default y
898	help
899	  If enabled, the Blackfin icache flushing functions are linked
900	  into L1 instruction memory.
901
902	  Note that this might be required to address anomalies, but
903	  these functions are pretty small, so it shouldn't be too bad.
904	  If you are using a processor affected by an anomaly, the build
905	  system will double check for you and prevent it.
906
907config DCACHE_FLUSH_L1
908	bool "Locate dcache flush funcs in L1 Inst Memory"
909	default y
910	depends on !SMP
911	help
912	  If enabled, the Blackfin dcache flushing functions are linked
913	  into L1 instruction memory.
914
915config APP_STACK_L1
916	bool "Support locating application stack in L1 Scratch Memory"
917	default y
918	depends on !SMP
919	help
920	  If enabled the application stack can be located in L1
921	  scratch memory (less latency).
922
923	  Currently only works with FLAT binaries.
924
925config EXCEPTION_L1_SCRATCH
926	bool "Locate exception stack in L1 Scratch Memory"
927	default n
928	depends on !SMP && !APP_STACK_L1
929	help
930	  Whenever an exception occurs, use the L1 Scratch memory for
931	  stack storage.  You cannot place the stacks of FLAT binaries
932	  in L1 when using this option.
933
934	  If you don't use L1 Scratch, then you should say Y here.
935
936comment "Speed Optimizations"
937config BFIN_INS_LOWOVERHEAD
938	bool "ins[bwl] low overhead, higher interrupt latency"
939	default y
940	depends on !SMP
941	help
942	  Reads on the Blackfin are speculative. In Blackfin terms, this means
943	  they can be interrupted at any time (even after they have been issued
944	  on to the external bus), and re-issued after the interrupt occurs.
945	  For memory - this is not a big deal, since memory does not change if
946	  it sees a read.
947
948	  If a FIFO is sitting on the end of the read, it will see two reads,
949	  when the core only sees one since the FIFO receives both the read
950	  which is cancelled (and not delivered to the core) and the one which
951	  is re-issued (which is delivered to the core).
952
953	  To solve this, interrupts are turned off before reads occur to
954	  I/O space. This option controls which the overhead/latency of
955	  controlling interrupts during this time
956	   "n" turns interrupts off every read
957		(higher overhead, but lower interrupt latency)
958	   "y" turns interrupts off every loop
959		(low overhead, but longer interrupt latency)
960
961	  default behavior is to leave this set to on (type "Y"). If you are experiencing
962	  interrupt latency issues, it is safe and OK to turn this off.
963
964endmenu
965
966choice
967	prompt "Kernel executes from"
968	help
969	  Choose the memory type that the kernel will be running in.
970
971config RAMKERNEL
972	bool "RAM"
973	help
974	  The kernel will be resident in RAM when running.
975
976config ROMKERNEL
977	bool "ROM"
978	help
979	  The kernel will be resident in FLASH/ROM when running.
980
981endchoice
982
983# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
984config XIP_KERNEL
985	bool
986	default y
987	depends on ROMKERNEL
988
989source "mm/Kconfig"
990
991config BFIN_GPTIMERS
992	tristate "Enable Blackfin General Purpose Timers API"
993	default n
994	help
995	  Enable support for the General Purpose Timers API.  If you
996	  are unsure, say N.
997
998	  To compile this driver as a module, choose M here: the module
999	  will be called gptimers.
1000
1001choice
1002	prompt "Uncached DMA region"
1003	default DMA_UNCACHED_1M
1004config DMA_UNCACHED_32M
1005	bool "Enable 32M DMA region"
1006config DMA_UNCACHED_16M
1007	bool "Enable 16M DMA region"
1008config DMA_UNCACHED_8M
1009	bool "Enable 8M DMA region"
1010config DMA_UNCACHED_4M
1011	bool "Enable 4M DMA region"
1012config DMA_UNCACHED_2M
1013	bool "Enable 2M DMA region"
1014config DMA_UNCACHED_1M
1015	bool "Enable 1M DMA region"
1016config DMA_UNCACHED_512K
1017	bool "Enable 512K DMA region"
1018config DMA_UNCACHED_256K
1019	bool "Enable 256K DMA region"
1020config DMA_UNCACHED_128K
1021	bool "Enable 128K DMA region"
1022config DMA_UNCACHED_NONE
1023	bool "Disable DMA region"
1024endchoice
1025
1026
1027comment "Cache Support"
1028
1029config BFIN_ICACHE
1030	bool "Enable ICACHE"
1031	default y
1032config BFIN_EXTMEM_ICACHEABLE
1033	bool "Enable ICACHE for external memory"
1034	depends on BFIN_ICACHE
1035	default y
1036config BFIN_L2_ICACHEABLE
1037	bool "Enable ICACHE for L2 SRAM"
1038	depends on BFIN_ICACHE
1039	depends on (BF54x || BF561 || BF60x) && !SMP
1040	default n
1041
1042config BFIN_DCACHE
1043	bool "Enable DCACHE"
1044	default y
1045config BFIN_DCACHE_BANKA
1046	bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1047	depends on BFIN_DCACHE && !BF531
1048	default n
1049config BFIN_EXTMEM_DCACHEABLE
1050	bool "Enable DCACHE for external memory"
1051	depends on BFIN_DCACHE
1052	default y
1053choice
1054	prompt "External memory DCACHE policy"
1055	depends on BFIN_EXTMEM_DCACHEABLE
1056	default BFIN_EXTMEM_WRITEBACK if !SMP
1057	default BFIN_EXTMEM_WRITETHROUGH if SMP
1058config BFIN_EXTMEM_WRITEBACK
1059	bool "Write back"
1060	depends on !SMP
1061	help
1062	  Write Back Policy:
1063	    Cached data will be written back to SDRAM only when needed.
1064	    This can give a nice increase in performance, but beware of
1065	    broken drivers that do not properly invalidate/flush their
1066	    cache.
1067
1068	  Write Through Policy:
1069	    Cached data will always be written back to SDRAM when the
1070	    cache is updated.  This is a completely safe setting, but
1071	    performance is worse than Write Back.
1072
1073	  If you are unsure of the options and you want to be safe,
1074	  then go with Write Through.
1075
1076config BFIN_EXTMEM_WRITETHROUGH
1077	bool "Write through"
1078	help
1079	  Write Back Policy:
1080	    Cached data will be written back to SDRAM only when needed.
1081	    This can give a nice increase in performance, but beware of
1082	    broken drivers that do not properly invalidate/flush their
1083	    cache.
1084
1085	  Write Through Policy:
1086	    Cached data will always be written back to SDRAM when the
1087	    cache is updated.  This is a completely safe setting, but
1088	    performance is worse than Write Back.
1089
1090	  If you are unsure of the options and you want to be safe,
1091	  then go with Write Through.
1092
1093endchoice
1094
1095config BFIN_L2_DCACHEABLE
1096	bool "Enable DCACHE for L2 SRAM"
1097	depends on BFIN_DCACHE
1098	depends on (BF54x || BF561 || BF60x) && !SMP
1099	default n
1100choice
1101	prompt "L2 SRAM DCACHE policy"
1102	depends on BFIN_L2_DCACHEABLE
1103	default BFIN_L2_WRITEBACK
1104config BFIN_L2_WRITEBACK
1105	bool "Write back"
1106
1107config BFIN_L2_WRITETHROUGH
1108	bool "Write through"
1109endchoice
1110
1111
1112comment "Memory Protection Unit"
1113config MPU
1114	bool "Enable the memory protection unit"
1115	default n
1116	help
1117	  Use the processor's MPU to protect applications from accessing
1118	  memory they do not own.  This comes at a performance penalty
1119	  and is recommended only for debugging.
1120
1121comment "Asynchronous Memory Configuration"
1122
1123menu "EBIU_AMGCTL Global Control"
1124	depends on !BF60x
1125config C_AMCKEN
1126	bool "Enable CLKOUT"
1127	default y
1128
1129config C_CDPRIO
1130	bool "DMA has priority over core for ext. accesses"
1131	default n
1132
1133config C_B0PEN
1134	depends on BF561
1135	bool "Bank 0 16 bit packing enable"
1136	default y
1137
1138config C_B1PEN
1139	depends on BF561
1140	bool "Bank 1 16 bit packing enable"
1141	default y
1142
1143config C_B2PEN
1144	depends on BF561
1145	bool "Bank 2 16 bit packing enable"
1146	default y
1147
1148config C_B3PEN
1149	depends on BF561
1150	bool "Bank 3 16 bit packing enable"
1151	default n
1152
1153choice
1154	prompt "Enable Asynchronous Memory Banks"
1155	default C_AMBEN_ALL
1156
1157config C_AMBEN
1158	bool "Disable All Banks"
1159
1160config C_AMBEN_B0
1161	bool "Enable Bank 0"
1162
1163config C_AMBEN_B0_B1
1164	bool "Enable Bank 0 & 1"
1165
1166config C_AMBEN_B0_B1_B2
1167	bool "Enable Bank 0 & 1 & 2"
1168
1169config C_AMBEN_ALL
1170	bool "Enable All Banks"
1171endchoice
1172endmenu
1173
1174menu "EBIU_AMBCTL Control"
1175	depends on !BF60x
1176config BANK_0
1177	hex "Bank 0 (AMBCTL0.L)"
1178	default 0x7BB0
1179	help
1180	  These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1181	  used to control the Asynchronous Memory Bank 0 settings.
1182
1183config BANK_1
1184	hex "Bank 1 (AMBCTL0.H)"
1185	default 0x7BB0
1186	default 0x5558 if BF54x
1187	help
1188	  These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1189	  used to control the Asynchronous Memory Bank 1 settings.
1190
1191config BANK_2
1192	hex "Bank 2 (AMBCTL1.L)"
1193	default 0x7BB0
1194	help
1195	  These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1196	  used to control the Asynchronous Memory Bank 2 settings.
1197
1198config BANK_3
1199	hex "Bank 3 (AMBCTL1.H)"
1200	default 0x99B3
1201	help
1202	  These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1203	  used to control the Asynchronous Memory Bank 3 settings.
1204
1205endmenu
1206
1207config EBIU_MBSCTLVAL
1208	hex "EBIU Bank Select Control Register"
1209	depends on BF54x
1210	default 0
1211
1212config EBIU_MODEVAL
1213	hex "Flash Memory Mode Control Register"
1214	depends on BF54x
1215	default 1
1216
1217config EBIU_FCTLVAL
1218	hex "Flash Memory Bank Control Register"
1219	depends on BF54x
1220	default 6
1221endmenu
1222
1223#############################################################################
1224menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1225
1226config PCI
1227	bool "PCI support"
1228	depends on BROKEN
1229	help
1230	  Support for PCI bus.
1231
1232source "drivers/pci/Kconfig"
1233
1234source "drivers/pcmcia/Kconfig"
1235
1236source "drivers/pci/hotplug/Kconfig"
1237
1238endmenu
1239
1240menu "Executable file formats"
1241
1242source "fs/Kconfig.binfmt"
1243
1244endmenu
1245
1246menu "Power management options"
1247
1248source "kernel/power/Kconfig"
1249
1250config ARCH_SUSPEND_POSSIBLE
1251	def_bool y
1252
1253choice
1254	prompt "Standby Power Saving Mode"
1255	depends on PM && !BF60x
1256	default PM_BFIN_SLEEP_DEEPER
1257config  PM_BFIN_SLEEP_DEEPER
1258	bool "Sleep Deeper"
1259	help
1260	  Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1261	  power dissipation by disabling the clock to the processor core (CCLK).
1262	  Furthermore, Standby sets the internal power supply voltage (VDDINT)
1263	  to 0.85 V to provide the greatest power savings, while preserving the
1264	  processor state.
1265	  The PLL and system clock (SCLK) continue to operate at a very low
1266	  frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1267	  the SDRAM is put into Self Refresh Mode. Typically an external event
1268	  such as GPIO interrupt or RTC activity wakes up the processor.
1269	  Various Peripherals such as UART, SPORT, PPI may not function as
1270	  normal during Sleep Deeper, due to the reduced SCLK frequency.
1271	  When in the sleep mode, system DMA access to L1 memory is not supported.
1272
1273	  If unsure, select "Sleep Deeper".
1274
1275config  PM_BFIN_SLEEP
1276	bool "Sleep"
1277	help
1278	  Sleep Mode (High Power Savings) - The sleep mode reduces power
1279	  dissipation by disabling the clock to the processor core (CCLK).
1280	  The PLL and system clock (SCLK), however, continue to operate in
1281	  this mode. Typically an external event or RTC activity will wake
1282	  up the processor. When in the sleep mode, system DMA access to L1
1283	  memory is not supported.
1284
1285	  If unsure, select "Sleep Deeper".
1286endchoice
1287
1288comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1289	depends on PM
1290
1291config PM_BFIN_WAKE_PH6
1292	bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1293	depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1294	default n
1295	help
1296	  Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1297
1298config PM_BFIN_WAKE_GP
1299	bool "Allow Wake-Up from GPIOs"
1300	depends on PM && BF54x
1301	default n
1302	help
1303	  Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1304	  (all processors, except ADSP-BF549). This option sets
1305	  the general-purpose wake-up enable (GPWE) control bit to enable
1306	  wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1307	  On ADSP-BF549 this option enables the same functionality on the
1308	  /MRXON pin also PH7.
1309
1310config PM_BFIN_WAKE_PA15
1311	bool "Allow Wake-Up from PA15"
1312	depends on PM && BF60x
1313	default n
1314	help
1315	  Enable PA15 Wake-Up
1316
1317config PM_BFIN_WAKE_PA15_POL
1318	int "Wake-up priority"
1319	depends on PM_BFIN_WAKE_PA15
1320	default 0
1321	help
1322	  Wake-Up priority 0(low) 1(high)
1323
1324config PM_BFIN_WAKE_PB15
1325	bool "Allow Wake-Up from PB15"
1326	depends on PM && BF60x
1327	default n
1328	help
1329	  Enable PB15 Wake-Up
1330
1331config PM_BFIN_WAKE_PB15_POL
1332	int "Wake-up priority"
1333	depends on PM_BFIN_WAKE_PB15
1334	default 0
1335	help
1336	  Wake-Up priority 0(low) 1(high)
1337
1338config PM_BFIN_WAKE_PC15
1339	bool "Allow Wake-Up from PC15"
1340	depends on PM && BF60x
1341	default n
1342	help
1343	  Enable PC15 Wake-Up
1344
1345config PM_BFIN_WAKE_PC15_POL
1346	int "Wake-up priority"
1347	depends on PM_BFIN_WAKE_PC15
1348	default 0
1349	help
1350	  Wake-Up priority 0(low) 1(high)
1351
1352config PM_BFIN_WAKE_PD06
1353	bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1354	depends on PM && BF60x
1355	default n
1356	help
1357	  Enable PD06(ETH0_PHYINT) Wake-up
1358
1359config PM_BFIN_WAKE_PD06_POL
1360	int "Wake-up priority"
1361	depends on PM_BFIN_WAKE_PD06
1362	default 0
1363	help
1364	  Wake-Up priority 0(low) 1(high)
1365
1366config PM_BFIN_WAKE_PE12
1367	bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1368	depends on PM && BF60x
1369	default n
1370	help
1371	  Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1372
1373config PM_BFIN_WAKE_PE12_POL
1374	int "Wake-up priority"
1375	depends on PM_BFIN_WAKE_PE12
1376	default 0
1377	help
1378	  Wake-Up priority 0(low) 1(high)
1379
1380config PM_BFIN_WAKE_PG04
1381	bool "Allow Wake-Up from PG04(CAN0_RX)"
1382	depends on PM && BF60x
1383	default n
1384	help
1385	  Enable PG04(CAN0_RX) Wake-up
1386
1387config PM_BFIN_WAKE_PG04_POL
1388	int "Wake-up priority"
1389	depends on PM_BFIN_WAKE_PG04
1390	default 0
1391	help
1392	  Wake-Up priority 0(low) 1(high)
1393
1394config PM_BFIN_WAKE_PG13
1395	bool "Allow Wake-Up from PG13"
1396	depends on PM && BF60x
1397	default n
1398	help
1399	  Enable PG13 Wake-Up
1400
1401config PM_BFIN_WAKE_PG13_POL
1402	int "Wake-up priority"
1403	depends on PM_BFIN_WAKE_PG13
1404	default 0
1405	help
1406	  Wake-Up priority 0(low) 1(high)
1407
1408config PM_BFIN_WAKE_USB
1409	bool "Allow Wake-Up from (USB)"
1410	depends on PM && BF60x
1411	default n
1412	help
1413	  Enable (USB) Wake-up
1414
1415config PM_BFIN_WAKE_USB_POL
1416	int "Wake-up priority"
1417	depends on PM_BFIN_WAKE_USB
1418	default 0
1419	help
1420	  Wake-Up priority 0(low) 1(high)
1421
1422endmenu
1423
1424menu "CPU Frequency scaling"
1425
1426source "drivers/cpufreq/Kconfig"
1427
1428config BFIN_CPU_FREQ
1429	bool
1430	depends on CPU_FREQ
1431	default y
1432
1433config CPU_VOLTAGE
1434	bool "CPU Voltage scaling"
1435	depends on CPU_FREQ
1436	default n
1437	help
1438	  Say Y here if you want CPU voltage scaling according to the CPU frequency.
1439	  This option violates the PLL BYPASS recommendation in the Blackfin Processor
1440	  manuals. There is a theoretical risk that during VDDINT transitions
1441	  the PLL may unlock.
1442
1443endmenu
1444
1445source "net/Kconfig"
1446
1447source "drivers/Kconfig"
1448
1449source "drivers/firmware/Kconfig"
1450
1451source "fs/Kconfig"
1452
1453source "arch/blackfin/Kconfig.debug"
1454
1455source "security/Kconfig"
1456
1457source "crypto/Kconfig"
1458
1459source "lib/Kconfig"
1460