1Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
2
3The device node has following properties.
4
5Required properties:
6 - compatible: Can be "rockchip,rk3288-gmac".
7 - reg: addresses and length of the register sets for the device.
8 - interrupts: Should contain the GMAC interrupts.
9 - interrupt-names: Should contain the interrupt names "macirq".
10 - rockchip,grf: phandle to the syscon grf used to control speed and mode.
11 - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.
12	   <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC
13	   <&cru SCLK_MAC_RX>: clock gate for RX
14	   <&cru SCLK_MAC_TX>: clock gate for TX
15	   <&cru SCLK_MACREF>: clock gate for RMII referce clock
16	   <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
17	   <&cru ACLK_GMAC>: AXI clock gate for GMAC
18	   <&cru PCLK_GMAC>: APB clock gate for GMAC
19 - clock-names: One name for each entry in the clocks property.
20 - phy-mode: See ethernet.txt file in the same directory.
21 - pinctrl-names: Names corresponding to the numbered pinctrl states.
22 - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
23 - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
24   is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
25   PHY provides the reference clock(50MHz), "output" means GMAC provides the
26   reference clock.
27 - snps,reset-gpio       gpio number for phy reset.
28 - snps,reset-active-low boolean flag to indicate if phy reset is active low.
29 - assigned-clocks: main clock, should be <&cru SCLK_MAC>;
30 - assigned-clock-parents = parent of main clock.
31   can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
32
33Optional properties:
34 - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
35 - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
36 - phy-supply: phandle to a regulator if the PHY needs one
37
38Example:
39
40gmac: ethernet@ff290000 {
41	compatible = "rockchip,rk3288-gmac";
42	reg = <0xff290000 0x10000>;
43	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
44	interrupt-names = "macirq";
45	rockchip,grf = <&grf>;
46	clocks = <&cru SCLK_MAC>,
47		<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
48		<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
49		<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
50	clock-names = "stmmaceth",
51		"mac_clk_rx", "mac_clk_tx",
52		"clk_mac_ref", "clk_mac_refout",
53		"aclk_mac", "pclk_mac";
54	phy-mode = "rgmii";
55	pinctrl-names = "default";
56	pinctrl-0 = <&rgmii_pins /*&rmii_pins*/>;
57
58	clock_in_out = "input";
59	snps,reset-gpio = <&gpio4 7 0>;
60	snps,reset-active-low;
61
62	assigned-clocks = <&cru SCLK_MAC>;
63	assigned-clock-parents = <&ext_gmac>;
64	tx_delay = <0x30>;
65	rx_delay = <0x10>;
66
67	status = "ok";
68};
69