Searched refs:ushort (Results 1 - 142 of 142) sorted by relevance

/linux-4.1.27/arch/powerpc/include/asm/
H A Dcpm1.h27 #define CPM_CR_RST ((ushort)0x8000)
28 #define CPM_CR_OPCODE ((ushort)0x0f00)
29 #define CPM_CR_CHAN ((ushort)0x00f0)
30 #define CPM_CR_FLG ((ushort)0x0001)
34 #define CPM_CR_CH_SCC1 ((ushort)0x0000)
35 #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
36 #define CPM_CR_CH_SCC2 ((ushort)0x0004)
37 #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
39 #define CPM_CR_CH_SCC3 ((ushort)0x0008)
40 #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
41 #define CPM_CR_CH_SCC4 ((ushort)0x000c)
42 #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
77 ushort smc_rbase; /* Rx Buffer descriptor base address */
78 ushort smc_tbase; /* Tx Buffer descriptor base address */
81 ushort smc_mrblr; /* Max receive buffer length */
84 ushort smc_rbptr; /* Internal */
85 ushort smc_ibc; /* Internal */
89 ushort smc_tbptr; /* Internal */
90 ushort smc_tbc; /* Internal */
92 ushort smc_maxidl; /* Maximum idle characters */
93 ushort smc_tmpidl; /* Temporary idle counter */
94 ushort smc_brklen; /* Last received break length */
95 ushort smc_brkec; /* rcv'd break condition counter */
96 ushort smc_brkcr; /* xmt break count register */
97 ushort smc_rmask; /* Temporary bit mask */
99 ushort smc_rpbase; /* Relocation pointer */
108 #define SMCMR_REN ((ushort)0x0001)
109 #define SMCMR_TEN ((ushort)0x0002)
110 #define SMCMR_DM ((ushort)0x000c)
111 #define SMCMR_SM_GCI ((ushort)0x0000)
112 #define SMCMR_SM_UART ((ushort)0x0020)
113 #define SMCMR_SM_TRANS ((ushort)0x0030)
114 #define SMCMR_SM_MASK ((ushort)0x0030)
115 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
117 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
119 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
120 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
129 ushort scent_rbase;
130 ushort scent_tbase;
133 ushort scent_mrblr;
136 ushort scent_rbptr;
137 ushort scent_r_cnt;
141 ushort scent_tbptr;
142 ushort scent_t_cnt;
144 ushort scent_max_sl;
145 ushort scent_sl_cnt;
146 ushort scent_character1;
147 ushort scent_character2;
148 ushort scent_character3;
149 ushort scent_character4;
150 ushort scent_character5;
151 ushort scent_character6;
152 ushort scent_character7;
153 ushort scent_character8;
154 ushort scent_rccm;
155 ushort scent_rccr;
278 #define SCC_TODR_TOD ((ushort)0x8000)
288 ushort scc_rbase; /* Rx Buffer descriptor base address */
289 ushort scc_tbase; /* Tx Buffer descriptor base address */
292 ushort scc_mrblr; /* Max receive buffer length */
295 ushort scc_rbptr; /* Internal */
296 ushort scc_ibc; /* Internal */
300 ushort scc_tbptr; /* Internal */
301 ushort scc_tbc; /* Internal */
320 ushort sen_pads; /* Tx short frame pad character */
321 ushort sen_retlim; /* Retry limit threshold */
322 ushort sen_retcnt; /* Retry limit counter */
323 ushort sen_maxflr; /* maximum frame length register */
324 ushort sen_minflr; /* minimum frame length register */
325 ushort sen_maxd1; /* maximum DMA1 length */
326 ushort sen_maxd2; /* maximum DMA2 length */
327 ushort sen_maxd; /* Rx max DMA */
328 ushort sen_dmacnt; /* Rx DMA counter */
329 ushort sen_maxb; /* Max BD byte count */
330 ushort sen_gaddr1; /* Group address filter */
331 ushort sen_gaddr2;
332 ushort sen_gaddr3;
333 ushort sen_gaddr4;
338 ushort sen_tbuf0bcnt; /* Internal */
339 ushort sen_paddrh; /* physical address (MSB) */
340 ushort sen_paddrm;
341 ushort sen_paddrl; /* physical address (LSB) */
342 ushort sen_pper; /* persistence */
343 ushort sen_rfbdptr; /* Rx first BD pointer */
344 ushort sen_tfbdptr; /* Tx first BD pointer */
345 ushort sen_tlbdptr; /* Tx last BD pointer */
350 ushort sen_tbuf1bcnt; /* Internal */
351 ushort sen_txlen; /* Tx Frame length counter */
352 ushort sen_iaddr1; /* Individual address filter */
353 ushort sen_iaddr2;
354 ushort sen_iaddr3;
355 ushort sen_iaddr4;
356 ushort sen_boffcnt; /* Backoff counter */
361 ushort sen_taddrh; /* temp address (MSB) */
362 ushort sen_taddrm;
363 ushort sen_taddrl; /* temp address (LSB) */
368 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
369 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
370 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
371 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
372 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
373 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
377 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
378 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
379 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
380 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
381 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
382 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
383 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
384 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
385 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
386 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
387 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
388 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
389 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
396 ushort scc_maxidl; /* Maximum idle chars */
397 ushort scc_idlc; /* temp idle counter */
398 ushort scc_brkcr; /* Break count register */
399 ushort scc_parec; /* receive parity error counter */
400 ushort scc_frmec; /* receive framing error counter */
401 ushort scc_nosec; /* receive noise counter */
402 ushort scc_brkec; /* receive break condition counter */
403 ushort scc_brkln; /* last received break length */
404 ushort scc_uaddr1; /* UART address character 1 */
405 ushort scc_uaddr2; /* UART address character 2 */
406 ushort scc_rtemp; /* Temp storage */
407 ushort scc_toseq; /* Transmit out of sequence char */
408 ushort scc_char1; /* control character 1 */
409 ushort scc_char2; /* control character 2 */
410 ushort scc_char3; /* control character 3 */
411 ushort scc_char4; /* control character 4 */
412 ushort scc_char5; /* control character 5 */
413 ushort scc_char6; /* control character 6 */
414 ushort scc_char7; /* control character 7 */
415 ushort scc_char8; /* control character 8 */
416 ushort scc_rccm; /* receive control character mask */
417 ushort scc_rccr; /* receive control character register */
418 ushort scc_rlbc; /* receive last break character */
423 #define UART_SCCM_GLR ((ushort)0x1000)
424 #define UART_SCCM_GLT ((ushort)0x0800)
425 #define UART_SCCM_AB ((ushort)0x0200)
426 #define UART_SCCM_IDL ((ushort)0x0100)
427 #define UART_SCCM_GRA ((ushort)0x0080)
428 #define UART_SCCM_BRKE ((ushort)0x0040)
429 #define UART_SCCM_BRKS ((ushort)0x0020)
430 #define UART_SCCM_CCR ((ushort)0x0008)
431 #define UART_SCCM_BSY ((ushort)0x0004)
432 #define UART_SCCM_TX ((ushort)0x0002)
433 #define UART_SCCM_RX ((ushort)0x0001)
437 #define SCU_PSMR_FLC ((ushort)0x8000)
438 #define SCU_PSMR_SL ((ushort)0x4000)
439 #define SCU_PSMR_CL ((ushort)0x3000)
440 #define SCU_PSMR_UM ((ushort)0x0c00)
441 #define SCU_PSMR_FRZ ((ushort)0x0200)
442 #define SCU_PSMR_RZS ((ushort)0x0100)
443 #define SCU_PSMR_SYN ((ushort)0x0080)
444 #define SCU_PSMR_DRT ((ushort)0x0040)
445 #define SCU_PSMR_PEN ((ushort)0x0010)
446 #define SCU_PSMR_RPM ((ushort)0x000c)
447 #define SCU_PSMR_REVP ((ushort)0x0008)
448 #define SCU_PSMR_TPM ((ushort)0x0003)
449 #define SCU_PSMR_TEVP ((ushort)0x0002)
462 ushort iic_rbase; /* Rx Buffer descriptor base address */
463 ushort iic_tbase; /* Tx Buffer descriptor base address */
466 ushort iic_mrblr; /* Max receive buffer length */
469 ushort iic_rbptr; /* Internal */
470 ushort iic_rbc; /* Internal */
474 ushort iic_tbptr; /* Internal */
475 ushort iic_tbc; /* Internal */
478 ushort iic_rpbase; /* Relocation pointer */
516 #define CPMVEC_PIO_PC15 ((ushort)0x1f)
517 #define CPMVEC_SCC1 ((ushort)0x1e)
518 #define CPMVEC_SCC2 ((ushort)0x1d)
519 #define CPMVEC_SCC3 ((ushort)0x1c)
520 #define CPMVEC_SCC4 ((ushort)0x1b)
521 #define CPMVEC_PIO_PC14 ((ushort)0x1a)
522 #define CPMVEC_TIMER1 ((ushort)0x19)
523 #define CPMVEC_PIO_PC13 ((ushort)0x18)
524 #define CPMVEC_PIO_PC12 ((ushort)0x17)
525 #define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
526 #define CPMVEC_IDMA1 ((ushort)0x15)
527 #define CPMVEC_IDMA2 ((ushort)0x14)
528 #define CPMVEC_TIMER2 ((ushort)0x12)
529 #define CPMVEC_RISCTIMER ((ushort)0x11)
530 #define CPMVEC_I2C ((ushort)0x10)
531 #define CPMVEC_PIO_PC11 ((ushort)0x0f)
532 #define CPMVEC_PIO_PC10 ((ushort)0x0e)
533 #define CPMVEC_TIMER3 ((ushort)0x0c)
534 #define CPMVEC_PIO_PC9 ((ushort)0x0b)
535 #define CPMVEC_PIO_PC8 ((ushort)0x0a)
536 #define CPMVEC_PIO_PC7 ((ushort)0x09)
537 #define CPMVEC_TIMER4 ((ushort)0x07)
538 #define CPMVEC_PIO_PC6 ((ushort)0x06)
539 #define CPMVEC_SPI ((ushort)0x05)
540 #define CPMVEC_SMC1 ((ushort)0x04)
541 #define CPMVEC_SMC2 ((ushort)0x03)
542 #define CPMVEC_PIO_PC5 ((ushort)0x02)
543 #define CPMVEC_PIO_PC4 ((ushort)0x01)
544 #define CPMVEC_ERROR ((ushort)0x00)
H A D8xx_immap.h23 ushort sc_swsr;
89 ushort memc_mstat;
90 ushort memc_mptpr;
150 ushort sit_tbscr;
155 ushort sit_rtcsc;
161 ushort sit_piscr;
168 #define TBSCR_TBIRQ_MASK ((ushort)0xff00)
169 #define TBSCR_REFA ((ushort)0x0080)
170 #define TBSCR_REFB ((ushort)0x0040)
171 #define TBSCR_REFAE ((ushort)0x0008)
172 #define TBSCR_REFBE ((ushort)0x0004)
173 #define TBSCR_TBF ((ushort)0x0002)
174 #define TBSCR_TBE ((ushort)0x0001)
176 #define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
177 #define RTCSC_SEC ((ushort)0x0080)
178 #define RTCSC_ALR ((ushort)0x0040)
179 #define RTCSC_38K ((ushort)0x0010)
180 #define RTCSC_SIE ((ushort)0x0008)
181 #define RTCSC_ALE ((ushort)0x0004)
182 #define RTCSC_RTF ((ushort)0x0002)
183 #define RTCSC_RTE ((ushort)0x0001)
185 #define PISCR_PIRQ_MASK ((ushort)0xff00)
186 #define PISCR_PS ((ushort)0x0080)
187 #define PISCR_PIE ((ushort)0x0004)
188 #define PISCR_PTF ((ushort)0x0002)
189 #define PISCR_PTE ((ushort)0x0001)
234 ushort vid_vccr;
235 ushort res1;
303 ushort cpic_civr;
314 ushort iop_padir;
315 ushort iop_papar;
316 ushort iop_paodr;
317 ushort iop_padat;
319 ushort iop_pcdir;
320 ushort iop_pcpar;
321 ushort iop_pcso;
322 ushort iop_pcdat;
323 ushort iop_pcint;
325 ushort iop_pddir;
326 ushort iop_pdpar;
328 ushort iop_pddat;
336 ushort cpmt_tgcr;
338 ushort cpmt_tmr1;
339 ushort cpmt_tmr2;
340 ushort cpmt_trr1;
341 ushort cpmt_trr2;
342 ushort cpmt_tcr1;
343 ushort cpmt_tcr2;
344 ushort cpmt_tcn1;
345 ushort cpmt_tcn2;
346 ushort cpmt_tmr3;
347 ushort cpmt_tmr4;
348 ushort cpmt_trr3;
349 ushort cpmt_trr4;
350 ushort cpmt_tcr3;
351 ushort cpmt_tcr4;
352 ushort cpmt_tcn3;
353 ushort cpmt_tcn4;
354 ushort cpmt_ter1;
355 ushort cpmt_ter2;
356 ushort cpmt_ter3;
357 ushort cpmt_ter4;
366 ushort scc_psmr;
368 ushort scc_todr;
369 ushort scc_dsr;
370 ushort scc_scce;
372 ushort scc_sccm;
380 ushort smc_smcmr;
394 ushort fec_addr_high; /* upper 16 bits of station address */
395 ushort res1; /* reserved */
437 ushort cp_cpcr;
439 ushort cp_rccr;
443 ushort cp_cpmcr1;
444 ushort cp_cpmcr2;
445 ushort cp_cpmcr3;
446 ushort cp_cpmcr4;
448 ushort cp_rter;
450 ushort cp_rtmr;
470 ushort cp_spmode;
482 ushort cp_pipc;
484 ushort cp_ptpr;
488 ushort cp_pbodr;
H A Dcpm2.h73 #define CPM_CR_START_IDMA ((ushort)0x0009)
167 ushort smc_rbase; /* Rx Buffer descriptor base address */
168 ushort smc_tbase; /* Tx Buffer descriptor base address */
171 ushort smc_mrblr; /* Max receive buffer length */
174 ushort smc_rbptr; /* Internal */
175 ushort smc_ibc; /* Internal */
179 ushort smc_tbptr; /* Internal */
180 ushort smc_tbc; /* Internal */
182 ushort smc_maxidl; /* Maximum idle characters */
183 ushort smc_tmpidl; /* Temporary idle counter */
184 ushort smc_brklen; /* Last received break length */
185 ushort smc_brkec; /* rcv'd break condition counter */
186 ushort smc_brkcr; /* xmt break count register */
187 ushort smc_rmask; /* Temporary bit mask */
193 #define SMCMR_REN ((ushort)0x0001)
194 #define SMCMR_TEN ((ushort)0x0002)
195 #define SMCMR_DM ((ushort)0x000c)
196 #define SMCMR_SM_GCI ((ushort)0x0000)
197 #define SMCMR_SM_UART ((ushort)0x0020)
198 #define SMCMR_SM_TRANS ((ushort)0x0030)
199 #define SMCMR_SM_MASK ((ushort)0x0030)
200 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
202 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
204 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
205 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
299 #define SCC_TODR_TOD ((ushort)0x8000)
309 ushort scc_rbase; /* Rx Buffer descriptor base address */
310 ushort scc_tbase; /* Tx Buffer descriptor base address */
313 ushort scc_mrblr; /* Max receive buffer length */
316 ushort scc_rbptr; /* Internal */
317 ushort scc_ibc; /* Internal */
321 ushort scc_tbptr; /* Internal */
322 ushort scc_tbc; /* Internal */
342 ushort sen_pads; /* Tx short frame pad character */
343 ushort sen_retlim; /* Retry limit threshold */
344 ushort sen_retcnt; /* Retry limit counter */
345 ushort sen_maxflr; /* maximum frame length register */
346 ushort sen_minflr; /* minimum frame length register */
347 ushort sen_maxd1; /* maximum DMA1 length */
348 ushort sen_maxd2; /* maximum DMA2 length */
349 ushort sen_maxd; /* Rx max DMA */
350 ushort sen_dmacnt; /* Rx DMA counter */
351 ushort sen_maxb; /* Max BD byte count */
352 ushort sen_gaddr1; /* Group address filter */
353 ushort sen_gaddr2;
354 ushort sen_gaddr3;
355 ushort sen_gaddr4;
360 ushort sen_tbuf0bcnt; /* Internal */
361 ushort sen_paddrh; /* physical address (MSB) */
362 ushort sen_paddrm;
363 ushort sen_paddrl; /* physical address (LSB) */
364 ushort sen_pper; /* persistence */
365 ushort sen_rfbdptr; /* Rx first BD pointer */
366 ushort sen_tfbdptr; /* Tx first BD pointer */
367 ushort sen_tlbdptr; /* Tx last BD pointer */
372 ushort sen_tbuf1bcnt; /* Internal */
373 ushort sen_txlen; /* Tx Frame length counter */
374 ushort sen_iaddr1; /* Individual address filter */
375 ushort sen_iaddr2;
376 ushort sen_iaddr3;
377 ushort sen_iaddr4;
378 ushort sen_boffcnt; /* Backoff counter */
383 ushort sen_taddrh; /* temp address (MSB) */
384 ushort sen_taddrm;
385 ushort sen_taddrl; /* temp address (LSB) */
391 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
392 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
393 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
394 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
395 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
396 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
400 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
401 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
402 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
403 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
404 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
405 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
406 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
407 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
408 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
409 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
410 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
411 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
412 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
420 ushort scc_maxidl; /* Maximum idle chars */
421 ushort scc_idlc; /* temp idle counter */
422 ushort scc_brkcr; /* Break count register */
423 ushort scc_parec; /* receive parity error counter */
424 ushort scc_frmec; /* receive framing error counter */
425 ushort scc_nosec; /* receive noise counter */
426 ushort scc_brkec; /* receive break condition counter */
427 ushort scc_brkln; /* last received break length */
428 ushort scc_uaddr1; /* UART address character 1 */
429 ushort scc_uaddr2; /* UART address character 2 */
430 ushort scc_rtemp; /* Temp storage */
431 ushort scc_toseq; /* Transmit out of sequence char */
432 ushort scc_char1; /* control character 1 */
433 ushort scc_char2; /* control character 2 */
434 ushort scc_char3; /* control character 3 */
435 ushort scc_char4; /* control character 4 */
436 ushort scc_char5; /* control character 5 */
437 ushort scc_char6; /* control character 6 */
438 ushort scc_char7; /* control character 7 */
439 ushort scc_char8; /* control character 8 */
440 ushort scc_rccm; /* receive control character mask */
441 ushort scc_rccr; /* receive control character register */
442 ushort scc_rlbc; /* receive last break character */
447 #define UART_SCCM_GLR ((ushort)0x1000)
448 #define UART_SCCM_GLT ((ushort)0x0800)
449 #define UART_SCCM_AB ((ushort)0x0200)
450 #define UART_SCCM_IDL ((ushort)0x0100)
451 #define UART_SCCM_GRA ((ushort)0x0080)
452 #define UART_SCCM_BRKE ((ushort)0x0040)
453 #define UART_SCCM_BRKS ((ushort)0x0020)
454 #define UART_SCCM_CCR ((ushort)0x0008)
455 #define UART_SCCM_BSY ((ushort)0x0004)
456 #define UART_SCCM_TX ((ushort)0x0002)
457 #define UART_SCCM_RX ((ushort)0x0001)
461 #define SCU_PSMR_FLC ((ushort)0x8000)
462 #define SCU_PSMR_SL ((ushort)0x4000)
463 #define SCU_PSMR_CL ((ushort)0x3000)
464 #define SCU_PSMR_UM ((ushort)0x0c00)
465 #define SCU_PSMR_FRZ ((ushort)0x0200)
466 #define SCU_PSMR_RZS ((ushort)0x0100)
467 #define SCU_PSMR_SYN ((ushort)0x0080)
468 #define SCU_PSMR_DRT ((ushort)0x0040)
469 #define SCU_PSMR_PEN ((ushort)0x0010)
470 #define SCU_PSMR_RPM ((ushort)0x000c)
471 #define SCU_PSMR_REVP ((ushort)0x0008)
472 #define SCU_PSMR_TPM ((ushort)0x0003)
473 #define SCU_PSMR_TEVP ((ushort)0x0002)
517 ushort fcc_riptr; /* Rx Internal temp pointer */
518 ushort fcc_tiptr; /* Tx Internal temp pointer */
519 ushort fcc_res1;
520 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
523 ushort fcc_rbdstat; /* RxBD status */
524 ushort fcc_rbdlen; /* RxBD down counter */
528 ushort fcc_tbdstat; /* TxBD status */
529 ushort fcc_tbdlen; /* TxBD down counter */
550 ushort fen_retlim; /* Retry limit */
551 ushort fen_retcnt; /* Retry counter */
552 ushort fen_pper; /* Persistence */
553 ushort fen_boffcnt; /* backoff counter */
556 ushort fen_tfcstat; /* out of sequence TxBD */
557 ushort fen_tfclen;
559 ushort fen_mflr; /* Maximum frame length (1518) */
560 ushort fen_paddrh; /* MAC address */
561 ushort fen_paddrm;
562 ushort fen_paddrl;
563 ushort fen_ibdcount; /* Internal BD counter */
564 ushort fen_ibdstart; /* Internal BD start pointer */
565 ushort fen_ibdend; /* Internal BD end pointer */
566 ushort fen_txlen; /* Internal Tx frame length counter */
570 ushort fen_minflr; /* Minimum frame length (64) */
571 ushort fen_taddrh; /* Filter transfer MAC address */
572 ushort fen_taddrm;
573 ushort fen_taddrl;
574 ushort fen_padptr; /* Pointer to pad byte buffer */
575 ushort fen_cftype; /* control frame type */
576 ushort fen_cfrange; /* control frame range */
577 ushort fen_maxb; /* maximum BD count */
578 ushort fen_maxd1; /* Max DMA1 length (1520) */
579 ushort fen_maxd2; /* Max DMA2 length (1520) */
580 ushort fen_maxd; /* internal max DMA count */
581 ushort fen_dmacnt; /* internal DMA counter */
597 ushort fen_rfthr; /* Received frames threshold */
598 ushort fen_rfcnt; /* Received frames count */
603 #define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
604 #define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
605 #define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
606 #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
607 #define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
608 #define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
609 #define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
610 #define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
631 ushort iic_rbase; /* Rx Buffer descriptor base address */
632 ushort iic_tbase; /* Tx Buffer descriptor base address */
635 ushort iic_mrblr; /* Max receive buffer length */
638 ushort iic_rbptr; /* Internal */
639 ushort iic_rbc; /* Internal */
643 ushort iic_tbptr; /* Internal */
644 ushort iic_tbc; /* Internal */
651 ushort ibase; /* IDMA buffer descriptor table base address */
652 ushort dcm; /* DMA channel mode */
653 ushort ibdptr; /* IDMA current buffer descriptor pointer */
654 ushort dpr_buf; /* IDMA transfer buffer base address */
655 ushort buf_inv; /* internal buffer inventory */
656 ushort ss_max; /* steady-state maximum transfer size */
657 ushort dpr_in_ptr; /* write pointer inside the internal buffer */
658 ushort sts; /* source transfer size */
659 ushort dpr_out_ptr; /* read pointer inside the internal buffer */
660 ushort seob; /* source end of burst */
661 ushort deob; /* destination end of burst */
662 ushort dts; /* destination transfer size */
663 ushort ret_add; /* return address when working in ERM=1 mode */
664 ushort res0; /* reserved */
674 #define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
675 #define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
676 #define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
677 #define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
678 #define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
679 #define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
680 #define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
681 #define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
682 #define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
683 #define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
684 #define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
685 #define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
686 #define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
687 #define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
688 #define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
689 #define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
690 #define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
691 #define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
H A Dcpm.h73 #define CPM_CR_INIT_TRX ((ushort)0x0000)
74 #define CPM_CR_INIT_RX ((ushort)0x0001)
75 #define CPM_CR_INIT_TX ((ushort)0x0002)
76 #define CPM_CR_HUNT_MODE ((ushort)0x0003)
77 #define CPM_CR_STOP_TX ((ushort)0x0004)
78 #define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
79 #define CPM_CR_RESTART_TX ((ushort)0x0006)
80 #define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
81 #define CPM_CR_SET_GADDR ((ushort)0x0008)
82 #define CPM_CR_SET_TIMER ((ushort)0x0008)
83 #define CPM_CR_STOP_IDMA ((ushort)0x000b)
87 ushort cbd_sc; /* Status and Control */
88 ushort cbd_datlen; /* Data length in buffer */
/linux-4.1.27/arch/m68k/include/asm/
H A Dcommproc.h22 #define CPM_CR_RST ((ushort)0x8000)
23 #define CPM_CR_OPCODE ((ushort)0x0f00)
24 #define CPM_CR_CHAN ((ushort)0x00f0)
25 #define CPM_CR_FLG ((ushort)0x0001)
28 #define CPM_CR_INIT_TRX ((ushort)0x0000)
29 #define CPM_CR_INIT_RX ((ushort)0x0001)
30 #define CPM_CR_INIT_TX ((ushort)0x0002)
31 #define CPM_CR_HUNT_MODE ((ushort)0x0003)
32 #define CPM_CR_STOP_TX ((ushort)0x0004)
33 #define CPM_CR_GRSTOP_TX ((ushort)0x0005)
34 #define CPM_CR_RESTART_TX ((ushort)0x0006)
35 #define CPM_CR_CLOSE_RXBD ((ushort)0x0007)
36 #define CPM_CR_SET_GADDR ((ushort)0x0008)
37 #define CPM_CR_GCI_TIMEOUT ((ushort)0x0009)
38 #define CPM_CR_GCI_ABORT ((ushort)0x000a)
39 #define CPM_CR_RESET_BCS ((ushort)0x000a)
42 #define CPM_CR_CH_SCC1 ((ushort)0x0000)
43 #define CPM_CR_CH_SCC2 ((ushort)0x0004)
44 #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / Timers */
45 #define CPM_CR_CH_TMR ((ushort)0x0005)
46 #define CPM_CR_CH_SCC3 ((ushort)0x0008)
47 #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / IDMA1 */
48 #define CPM_CR_CH_IDMA1 ((ushort)0x0009)
49 #define CPM_CR_CH_SCC4 ((ushort)0x000c)
50 #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / IDMA2 */
51 #define CPM_CR_CH_IDMA2 ((ushort)0x000d)
83 ushort cbd_sc; /* Status and Control */
84 ushort cbd_datlen; /* Data length in buffer */
91 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
92 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */
93 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
94 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */
96 #define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */
97 #define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */
99 #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
100 #define BD_SC_ID ((ushort)0x0100) /* Received too many idles */
102 #define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */
103 #define BD_SC_DE ((ushort)0x0080) /* DPLL Error (HDLC) */
105 #define BD_SC_BR ((ushort)0x0020) /* Break received */
106 #define BD_SC_LG ((ushort)0x0020) /* Frame length violation (HDLC) */
108 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
109 #define BD_SC_NO ((ushort)0x0010) /* Nonoctet aligned frame (HDLC) */
111 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
112 #define BD_SC_AB ((ushort)0x0008) /* Received abort Sequence (HDLC) */
114 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
115 #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
118 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
119 #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
120 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
121 #define BD_SC_UN ((ushort)0x0002) /* Underrun */
154 ushort smc_rbase; /* Rx Buffer descriptor base address */
155 ushort smc_tbase; /* Tx Buffer descriptor base address */
158 ushort smc_mrblr; /* Max receive buffer length */
161 ushort smc_rbptr; /* Internal */
162 ushort smc_ibc; /* Internal */
166 ushort smc_tbptr; /* Internal */
167 ushort smc_tbc; /* Internal */
169 ushort smc_maxidl; /* Maximum idle characters */
170 ushort smc_tmpidl; /* Temporary idle counter */
171 ushort smc_brklen; /* Last received break length */
172 ushort smc_brkec; /* rcv'd break condition counter */
173 ushort smc_brkcr; /* xmt break count register */
174 ushort smc_rmask; /* Temporary bit mask */
183 #define SMCMR_REN ((ushort)0x0001)
184 #define SMCMR_TEN ((ushort)0x0002)
185 #define SMCMR_DM ((ushort)0x000c)
186 #define SMCMR_SM_GCI ((ushort)0x0000)
187 #define SMCMR_SM_UART ((ushort)0x0020)
188 #define SMCMR_SM_TRANS ((ushort)0x0030)
189 #define SMCMR_SM_MASK ((ushort)0x0030)
190 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
192 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
194 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
195 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
204 ushort scent_rbase;
205 ushort scent_tbase;
208 ushort scent_mrblr;
211 ushort scent_rbptr;
212 ushort scent_r_cnt;
216 ushort scent_tbptr;
217 ushort scent_t_cnt;
219 ushort scent_max_sl;
220 ushort scent_sl_cnt;
221 ushort scent_character1;
222 ushort scent_character2;
223 ushort scent_character3;
224 ushort scent_character4;
225 ushort scent_character5;
226 ushort scent_character6;
227 ushort scent_character7;
228 ushort scent_character8;
229 ushort scent_rccm;
230 ushort scent_rccr;
341 #define SCC_TODR_TOD ((ushort)0x8000)
351 ushort scc_rbase; /* Rx Buffer descriptor base address */
352 ushort scc_tbase; /* Tx Buffer descriptor base address */
355 ushort scc_mrblr; /* Max receive buffer length */
358 ushort scc_rbptr; /* Internal */
359 ushort scc_ibc; /* Internal */
363 ushort scc_tbptr; /* Internal */
364 ushort scc_tbc; /* Internal */
385 ushort sen_pads; /* Tx short frame pad character */
386 ushort sen_retlim; /* Retry limit threshold */
387 ushort sen_retcnt; /* Retry limit counter */
388 ushort sen_maxflr; /* maximum frame length register */
389 ushort sen_minflr; /* minimum frame length register */
390 ushort sen_maxd1; /* maximum DMA1 length */
391 ushort sen_maxd2; /* maximum DMA2 length */
392 ushort sen_maxd; /* Rx max DMA */
393 ushort sen_dmacnt; /* Rx DMA counter */
394 ushort sen_maxb; /* Max BD byte count */
395 ushort sen_gaddr1; /* Group address filter */
396 ushort sen_gaddr2;
397 ushort sen_gaddr3;
398 ushort sen_gaddr4;
403 ushort sen_tbuf0bcnt; /* Internal */
404 ushort sen_paddrh; /* physical address (MSB) */
405 ushort sen_paddrm;
406 ushort sen_paddrl; /* physical address (LSB) */
407 ushort sen_pper; /* persistence */
408 ushort sen_rfbdptr; /* Rx first BD pointer */
409 ushort sen_tfbdptr; /* Tx first BD pointer */
410 ushort sen_tlbdptr; /* Tx last BD pointer */
415 ushort sen_tbuf1bcnt; /* Internal */
416 ushort sen_txlen; /* Tx Frame length counter */
417 ushort sen_iaddr1; /* Individual address filter */
418 ushort sen_iaddr2;
419 ushort sen_iaddr3;
420 ushort sen_iaddr4;
421 ushort sen_boffcnt; /* Backoff counter */
426 ushort sen_taddrh; /* temp address (MSB) */
427 ushort sen_taddrm;
428 ushort sen_taddrl; /* temp address (LSB) */
468 #define PA_ENET_RXD ((ushort)0x0001)
469 #define PA_ENET_TXD ((ushort)0x0002)
470 #define PA_ENET_TCLK ((ushort)0x0200)
471 #define PA_ENET_RCLK ((ushort)0x0800)
472 #define PC_ENET_TENA ((ushort)0x0001)
473 #define PC_ENET_CLSN ((ushort)0x0010)
474 #define PC_ENET_RENA ((ushort)0x0020)
485 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
486 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
487 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
488 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
489 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
490 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
494 #define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */
495 #define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */
496 #define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */
497 #define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */
498 #define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
499 #define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */
500 #define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
501 #define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */
502 #define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */
503 #define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */
504 #define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */
505 #define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */
506 #define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */
510 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
511 #define BD_ENET_RX_WRAP ((ushort)0x2000)
512 #define BD_ENET_RX_INTR ((ushort)0x1000)
513 #define BD_ENET_RX_LAST ((ushort)0x0800)
514 #define BD_ENET_RX_FIRST ((ushort)0x0400)
515 #define BD_ENET_RX_MISS ((ushort)0x0100)
516 #define BD_ENET_RX_LG ((ushort)0x0020)
517 #define BD_ENET_RX_NO ((ushort)0x0010)
518 #define BD_ENET_RX_SH ((ushort)0x0008)
519 #define BD_ENET_RX_CR ((ushort)0x0004)
520 #define BD_ENET_RX_OV ((ushort)0x0002)
521 #define BD_ENET_RX_CL ((ushort)0x0001)
522 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
526 #define BD_ENET_TX_READY ((ushort)0x8000)
527 #define BD_ENET_TX_PAD ((ushort)0x4000)
528 #define BD_ENET_TX_WRAP ((ushort)0x2000)
529 #define BD_ENET_TX_INTR ((ushort)0x1000)
530 #define BD_ENET_TX_LAST ((ushort)0x0800)
531 #define BD_ENET_TX_TC ((ushort)0x0400)
532 #define BD_ENET_TX_DEF ((ushort)0x0200)
533 #define BD_ENET_TX_HB ((ushort)0x0100)
534 #define BD_ENET_TX_LC ((ushort)0x0080)
535 #define BD_ENET_TX_RL ((ushort)0x0040)
536 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
537 #define BD_ENET_TX_UN ((ushort)0x0002)
538 #define BD_ENET_TX_CSL ((ushort)0x0001)
539 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
547 ushort scc_maxidl; /* Maximum idle chars */
548 ushort scc_idlc; /* temp idle counter */
549 ushort scc_brkcr; /* Break count register */
550 ushort scc_parec; /* receive parity error counter */
551 ushort scc_frmec; /* receive framing error counter */
552 ushort scc_nosec; /* receive noise counter */
553 ushort scc_brkec; /* receive break condition counter */
554 ushort scc_brkln; /* last received break length */
555 ushort scc_uaddr1; /* UART address character 1 */
556 ushort scc_uaddr2; /* UART address character 2 */
557 ushort scc_rtemp; /* Temp storage */
558 ushort scc_toseq; /* Transmit out of sequence char */
559 ushort scc_char1; /* control character 1 */
560 ushort scc_char2; /* control character 2 */
561 ushort scc_char3; /* control character 3 */
562 ushort scc_char4; /* control character 4 */
563 ushort scc_char5; /* control character 5 */
564 ushort scc_char6; /* control character 6 */
565 ushort scc_char7; /* control character 7 */
566 ushort scc_char8; /* control character 8 */
567 ushort scc_rccm; /* receive control character mask */
568 ushort scc_rccr; /* receive control character register */
569 ushort scc_rlbc; /* receive last break character */
574 #define UART_SCCM_GLR ((ushort)0x1000)
575 #define UART_SCCM_GLT ((ushort)0x0800)
576 #define UART_SCCM_AB ((ushort)0x0200)
577 #define UART_SCCM_IDL ((ushort)0x0100)
578 #define UART_SCCM_GRA ((ushort)0x0080)
579 #define UART_SCCM_BRKE ((ushort)0x0040)
580 #define UART_SCCM_BRKS ((ushort)0x0020)
581 #define UART_SCCM_CCR ((ushort)0x0008)
582 #define UART_SCCM_BSY ((ushort)0x0004)
583 #define UART_SCCM_TX ((ushort)0x0002)
584 #define UART_SCCM_RX ((ushort)0x0001)
588 #define SCU_PMSR_FLC ((ushort)0x8000)
589 #define SCU_PMSR_SL ((ushort)0x4000)
590 #define SCU_PMSR_CL ((ushort)0x3000)
591 #define SCU_PMSR_UM ((ushort)0x0c00)
592 #define SCU_PMSR_FRZ ((ushort)0x0200)
593 #define SCU_PMSR_RZS ((ushort)0x0100)
594 #define SCU_PMSR_SYN ((ushort)0x0080)
595 #define SCU_PMSR_DRT ((ushort)0x0040)
596 #define SCU_PMSR_PEN ((ushort)0x0010)
597 #define SCU_PMSR_RPM ((ushort)0x000c)
598 #define SCU_PMSR_REVP ((ushort)0x0008)
599 #define SCU_PMSR_TPM ((ushort)0x0003)
600 #define SCU_PMSR_TEVP ((ushort)0x0003)
610 #define BD_SCC_TX_LAST ((ushort)0x0800)
622 /* #define CPMVEC_PIO_PC15 ((ushort)0x1f) */
623 /* #define CPMVEC_SCC1 ((ushort)0x1e) */
624 /* #define CPMVEC_SCC2 ((ushort)0x1d) */
625 /* #define CPMVEC_SCC3 ((ushort)0x1c) */
626 /* #define CPMVEC_SCC4 ((ushort)0x1b) */
627 /* #define CPMVEC_PIO_PC14 ((ushort)0x1a) */
628 /* #define CPMVEC_TIMER1 ((ushort)0x19) */
629 /* #define CPMVEC_PIO_PC13 ((ushort)0x18) */
630 /* #define CPMVEC_PIO_PC12 ((ushort)0x17) */
631 /* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */
632 /* #define CPMVEC_IDMA1 ((ushort)0x15) */
633 /* #define CPMVEC_IDMA2 ((ushort)0x14) */
634 /* #define CPMVEC_TIMER2 ((ushort)0x12) */
635 /* #define CPMVEC_RISCTIMER ((ushort)0x11) */
636 /* #define CPMVEC_I2C ((ushort)0x10) */
637 /* #define CPMVEC_PIO_PC11 ((ushort)0x0f) */
638 /* #define CPMVEC_PIO_PC10 ((ushort)0x0e) */
639 /* #define CPMVEC_TIMER3 ((ushort)0x0c) */
640 /* #define CPMVEC_PIO_PC9 ((ushort)0x0b) */
641 /* #define CPMVEC_PIO_PC8 ((ushort)0x0a) */
642 /* #define CPMVEC_PIO_PC7 ((ushort)0x09) */
643 /* #define CPMVEC_TIMER4 ((ushort)0x07) */
644 /* #define CPMVEC_PIO_PC6 ((ushort)0x06) */
645 /* #define CPMVEC_SPI ((ushort)0x05) */
646 /* #define CPMVEC_SMC1 ((ushort)0x04) */
647 /* #define CPMVEC_SMC2 ((ushort)0x03) */
648 /* #define CPMVEC_PIO_PC5 ((ushort)0x02) */
649 /* #define CPMVEC_PIO_PC4 ((ushort)0x01) */
650 /* #define CPMVEC_ERROR ((ushort)0x00) */
H A Dm68360_regs.h219 /* #define CPMVEC_PIO_PC0 ((ushort)0x1f) */
220 /* #define CPMVEC_SCC1 ((ushort)0x1e) */
221 /* #define CPMVEC_SCC2 ((ushort)0x1d) */
222 /* #define CPMVEC_SCC3 ((ushort)0x1c) */
223 /* #define CPMVEC_SCC4 ((ushort)0x1b) */
224 /* #define CPMVEC_PIO_PC1 ((ushort)0x1a) */
225 /* #define CPMVEC_TIMER1 ((ushort)0x19) */
226 /* #define CPMVEC_PIO_PC2 ((ushort)0x18) */
227 /* #define CPMVEC_PIO_PC3 ((ushort)0x17) */
228 /* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */
229 /* #define CPMVEC_IDMA1 ((ushort)0x15) */
230 /* #define CPMVEC_IDMA2 ((ushort)0x14) */
231 /* #define CPMVEC_RESERVED3 ((ushort)0x13) */
232 /* #define CPMVEC_TIMER2 ((ushort)0x12) */
233 /* #define CPMVEC_RISCTIMER ((ushort)0x11) */
234 /* #define CPMVEC_RESERVED2 ((ushort)0x10) */
235 /* #define CPMVEC_PIO_PC4 ((ushort)0x0f) */
236 /* #define CPMVEC_PIO_PC5 ((ushort)0x0e) */
237 /* #define CPMVEC_TIMER3 ((ushort)0x0c) */
238 /* #define CPMVEC_PIO_PC6 ((ushort)0x0b) */
239 /* #define CPMVEC_PIO_PC7 ((ushort)0x0a) */
240 /* #define CPMVEC_PIO_PC8 ((ushort)0x09) */
241 /* #define CPMVEC_RESERVED1 ((ushort)0x08) */
242 /* #define CPMVEC_TIMER4 ((ushort)0x07) */
243 /* #define CPMVEC_PIO_PC9 ((ushort)0x06) */
244 /* #define CPMVEC_SPI ((ushort)0x05) */
245 /* #define CPMVEC_SMC1 ((ushort)0x04) */
246 /* #define CPMVEC_SMC2 ((ushort)0x03) */
247 /* #define CPMVEC_PIO_PC10 ((ushort)0x02) */
248 /* #define CPMVEC_PIO_PC11 ((ushort)0x01) */
249 /* #define CPMVEC_ERROR ((ushort)0x00) */
264 /* #define PA_RXD(n) ((ushort)(0x01<<(2*n))) */
265 /* #define PA_TXD(n) ((ushort)(0x02<<(2*n))) */
267 #define PA_RXD1 ((ushort)0x0001)
268 #define PA_TXD1 ((ushort)0x0002)
269 #define PA_RXD2 ((ushort)0x0004)
270 #define PA_TXD2 ((ushort)0x0008)
271 #define PA_RXD3 ((ushort)0x0010)
272 #define PA_TXD3 ((ushort)0x0020)
273 #define PA_RXD4 ((ushort)0x0040)
274 #define PA_TXD4 ((ushort)0x0080)
276 #define PA_CLK1 ((ushort)0x0100)
277 #define PA_CLK2 ((ushort)0x0200)
278 #define PA_CLK3 ((ushort)0x0400)
279 #define PA_CLK4 ((ushort)0x0800)
280 #define PA_CLK5 ((ushort)0x1000)
281 #define PA_CLK6 ((ushort)0x2000)
282 #define PA_CLK7 ((ushort)0x4000)
283 #define PA_CLK8 ((ushort)0x8000)
293 #define PC_RTS1 ((ushort)0x0001)
294 #define PC_RTS2 ((ushort)0x0002)
295 #define PC__RTS3 ((ushort)0x0004) /* !RTS3 */
296 #define PC__RTS4 ((ushort)0x0008) /* !RTS4 */
298 #define PC_CTS1 ((ushort)0x0010)
299 #define PC_CD1 ((ushort)0x0020)
300 #define PC_CTS2 ((ushort)0x0040)
301 #define PC_CD2 ((ushort)0x0080)
302 #define PC_CTS3 ((ushort)0x0100)
303 #define PC_CD3 ((ushort)0x0200)
304 #define PC_CTS4 ((ushort)0x0400)
305 #define PC_CD4 ((ushort)0x0800)
/linux-4.1.27/drivers/staging/sm750fb/
H A Dsm750_hw.h49 ushort powerMode;
51 ushort chip_clk;
52 ushort mem_clk;
53 ushort master_clk;
54 ushort setAllEngOff;
55 ushort resetMemory;
95 int hw_sm750_setColReg(struct lynxfb_crtc*,ushort,ushort,ushort,ushort);
H A Dsm750.h120 int(*proc_setColReg)(struct lynxfb_crtc*,ushort,ushort,ushort,ushort);
H A Dsm750_hw.c424 int hw_sm750_setColReg(struct lynxfb_crtc* crtc, ushort index, hw_sm750_setColReg()
425 ushort red, ushort green, ushort blue) hw_sm750_setColReg()
/linux-4.1.27/drivers/isdn/pcbit/
H A Dcapi.c56 ushort len; capi_conn_req()
86 *((ushort *)skb_put(*skb, 2)) = AppInfoMask; capi_conn_req()
143 *((ushort *)skb_put(*skb, 2)) = chan->callref; capi_conn_resp()
163 *((ushort *)skb_put(*skb, 2)) = chan->callref; capi_conn_active_req()
191 *((ushort *)skb_put(*skb, 2)) = chan->callref; capi_conn_active_resp()
211 *((ushort *)skb_put(*skb, 2)) = chan->callref; capi_select_proto_req()
239 *((ushort *) skb_put(*skb, 2)) = MRU; capi_select_proto_req()
272 *((ushort *)skb_put(*skb, 2)) = chan->callref; capi_activate_transp_req()
278 *((ushort *) skb_put(*skb, 2)) = MRU; capi_activate_transp_req()
287 ushort data_len; capi_tdata_req()
330 *((ushort *)skb_put(*skb, 2)) = chan->callref; capi_tdata_resp()
338 int capi_disc_req(ushort callref, struct sk_buff **skb, u_char cause) capi_disc_req()
347 *((ushort *)skb_put(*skb, 2)) = callref; capi_disc_req()
370 *((ushort *)skb_put(*skb, 2)) = chan->callref; capi_disc_resp()
388 chan->callref = *((ushort *)skb->data); capi_decode_conn_ind()
498 chan->callref = *((ushort *)skb->data); /* Update CallReference */ capi_decode_conn_conf()
501 errcode = *((ushort *) skb->data); /* read errcode */ capi_decode_conn_conf()
530 ushort len; capi_decode_conn_actv_ind()
568 ushort errcode; capi_decode_conn_actv_conf()
570 errcode = *((ushort *)skb->data); capi_decode_conn_actv_conf()
582 ushort errcode; capi_decode_sel_proto_conf()
587 errcode = *((ushort *)skb->data); capi_decode_sel_proto_conf()
595 ushort errcode; capi_decode_actv_trans_conf()
602 errcode = *((ushort *)skb->data); capi_decode_actv_trans_conf()
610 ushort len; capi_decode_disc_ind()
632 int capi_decode_debug_188(u_char *hdr, ushort hdrlen) capi_decode_debug_188()
H A Dpcbit.h61 ushort ll_hdrlen;
62 ushort hl_hdrlen;
85 ushort loadptr;
120 ushort addr;
121 ushort value;
173 ushort hdr_len, ushort refnum);
H A Dcapi.h56 extern int capi_disc_req(ushort callref, struct sk_buff **skb, u_char cause);
62 extern int capi_decode_debug_188(u_char *hdr, ushort hdrlen);
68 ushort callref; capi_channel()
70 callref = *((ushort *)skb->data); capi_channel()
H A Dcallbacks.c35 ushort last_ref_num = 1;
47 ushort refnum; cb_out_1()
90 ushort refnum; cb_out_2()
247 ushort refnum; cb_disc_1()
276 ushort refnum; cb_disc_2()
319 ushort refnum; cb_selp_1()
H A Dedss1.h97 char *strisdnevent(ushort ev);
H A Ddrv.c44 extern ushort last_ref_num;
330 ushort hdrlen; pcbit_xmit()
469 ushort hdr_len, ushort refnum) pcbit_l3_receive()
504 if ((*((ushort *)(skb->data + 2))) != 0) { pcbit_l3_receive()
537 if ((len = capi_disc_req(*(ushort *)(skb->data), &skb2, CAUSE_NOCHAN)) > 0) pcbit_l3_receive()
H A Dlayer2.c75 pcbit_l2_write(struct pcbit_dev *dev, ulong msg, ushort refnum, pcbit_l2_write()
121 pcbit_tx_update(struct pcbit_dev *dev, ushort len) pcbit_tx_update()
234 tt = ((ushort) (flen - 2)) | 0x8000U; /* Type 1 */ pcbit_transmit()
302 frame->refnum = *((ushort *)frame->skb->data + 4); pcbit_deliver()
H A Dedss1.c167 char *strisdnevent(ushort ev) strisdnevent()
H A Dlayer2.h124 extern int pcbit_l2_write(struct pcbit_dev *dev, ulong msg, ushort refnum,
/linux-4.1.27/drivers/net/ethernet/freescale/
H A Dfec.h221 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
222 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
223 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
224 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
225 #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
226 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
227 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
228 #define BD_SC_BR ((ushort)0x0020) /* Break received */
229 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
230 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
231 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
232 #define BD_SC_CD ((ushort)0x0001) /* ?? */
236 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
237 #define BD_ENET_RX_WRAP ((ushort)0x2000)
238 #define BD_ENET_RX_INTR ((ushort)0x1000)
239 #define BD_ENET_RX_LAST ((ushort)0x0800)
240 #define BD_ENET_RX_FIRST ((ushort)0x0400)
241 #define BD_ENET_RX_MISS ((ushort)0x0100)
242 #define BD_ENET_RX_LG ((ushort)0x0020)
243 #define BD_ENET_RX_NO ((ushort)0x0010)
244 #define BD_ENET_RX_SH ((ushort)0x0008)
245 #define BD_ENET_RX_CR ((ushort)0x0004)
246 #define BD_ENET_RX_OV ((ushort)0x0002)
247 #define BD_ENET_RX_CL ((ushort)0x0001)
248 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
255 #define BD_ENET_TX_READY ((ushort)0x8000)
256 #define BD_ENET_TX_PAD ((ushort)0x4000)
257 #define BD_ENET_TX_WRAP ((ushort)0x2000)
258 #define BD_ENET_TX_INTR ((ushort)0x1000)
259 #define BD_ENET_TX_LAST ((ushort)0x0800)
260 #define BD_ENET_TX_TC ((ushort)0x0400)
261 #define BD_ENET_TX_DEF ((ushort)0x0200)
262 #define BD_ENET_TX_HB ((ushort)0x0100)
263 #define BD_ENET_TX_LC ((ushort)0x0080)
264 #define BD_ENET_TX_RL ((ushort)0x0040)
265 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
266 #define BD_ENET_TX_UN ((ushort)0x0002)
267 #define BD_ENET_TX_CSL ((ushort)0x0001)
268 #define BD_ENET_TX_STATS ((ushort)0x0fff) /* All status bits */
339 #define BD_ENET_RX_PTP ((ushort)0x0400)
H A Dfec_main.c1366 ushort pkt_len; fec_enet_rx_queue()
/linux-4.1.27/arch/alpha/lib/
H A Dev6-csum_ipv6_magic.S39 * add 4 ushorts, resulting in ushort/carry
40 * add carry bits + ushort --> ushort
41 * add carry bits + ushort --> ushort (in case the carry results in an overflow)
42 * Truncate to a ushort. (took 13 instructions)
134 extwl $1,2,$2 # U : ushort[1] (1 cycle stall on $1)
135 zapnot $1,3,$0 # U : ushort[0] (1 cycle stall on $1)
136 extwl $1,4,$1 # U : ushort[2] (1 cycle stall on $1)
141 extwl $3,2,$1 # U : ushort[1] (1 cycle stall on $3)
/linux-4.1.27/drivers/scsi/
H A Dadvansys.c323 ushort vm_id;
339 ushort x_req_count;
340 ushort x_reconnect_rtn;
363 ushort entry_cnt;
364 ushort queue_cnt;
365 ushort entry_to_copy;
366 ushort res;
375 ushort remain_sg_entry_cnt;
376 ushort next_sg_index;
529 ushort mcode_date;
530 ushort mcode_version;
559 ushort err_code;
560 ushort dvc_cntl;
561 ushort bug_fix_cntl;
562 ushort bus_type;
578 ushort init_state;
587 ushort res2;
613 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
614 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
615 #define ASC_CNTL_INITIATOR (ushort)0x0001
616 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
617 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
618 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
619 #define ASC_CNTL_NO_SCAM (ushort)0x0010
620 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
621 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
622 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
623 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
624 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
625 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
626 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
627 #define ASC_CNTL_BURST_MODE (ushort)0x2000
628 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
650 ushort cfg_lsw;
651 ushort cfg_msw;
665 ushort cntl;
666 ushort chksum;
676 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
682 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
683 #define ASCV_BREAK_ADDR (ushort)0x0028
684 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
685 #define ASCV_BREAK_CONTROL (ushort)0x002C
686 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
688 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
689 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
690 #define ASCV_MCODE_SIZE_W (ushort)0x0034
691 #define ASCV_STOP_CODE_B (ushort)0x0036
692 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
693 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
694 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
695 #define ASCV_HALTCODE_W (ushort)0x0040
696 #define ASCV_CHKSUM_W (ushort)0x0042
697 #define ASCV_MC_DATE_W (ushort)0x0044
698 #define ASCV_MC_VER_W (ushort)0x0046
699 #define ASCV_NEXTRDY_B (ushort)0x0048
700 #define ASCV_DONENEXT_B (ushort)0x0049
701 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
702 #define ASCV_SCSIBUSY_B (ushort)0x004B
703 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
704 #define ASCV_CURCDB_B (ushort)0x004D
705 #define ASCV_RCLUN_B (ushort)0x004E
706 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
707 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
708 #define ASCV_DISC_ENABLE_B (ushort)0x0052
709 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
710 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
711 #define ASCV_MCODE_CNTL_B (ushort)0x0056
712 #define ASCV_NULL_TARGET_B (ushort)0x0057
713 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
714 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
715 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
716 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
717 #define ASCV_HOST_FLAG_B (ushort)0x005D
718 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
719 #define ASCV_VER_SERIAL_B (ushort)0x0065
720 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
721 #define ASCV_WTM_FLAG_B (ushort)0x0068
722 #define ASCV_RISC_FLAG_B (ushort)0x006A
723 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
779 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
780 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
781 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
782 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
783 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
784 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
785 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
787 #define ASC_DATA_SEC_BEG (ushort)0x0080
788 #define ASC_DATA_SEC_END (ushort)0x0080
789 #define ASC_CODE_SEC_BEG (ushort)0x0080
790 #define ASC_CODE_SEC_END (ushort)0x0080
792 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
793 #define ASC_QADR_END (ushort)0x7FFF
794 #define ASC_QLAST_ADR (ushort)0x7FC0
852 #define INS_HALTINT (ushort)0x6281
853 #define INS_HALT (ushort)0x6280
854 #define INS_SINT (ushort)0x6200
855 #define INS_RFLAG_WTM (ushort)0x7380
860 ushort data[ASC_MC_SAVE_DATA_WSIZE];
861 ushort code[ASC_MC_SAVE_CODE_WSIZE];
874 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
875 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
876 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
877 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
879 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
881 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
882 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
887 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
889 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
891 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
902 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
907 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
911 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
915 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
917 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
921 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
923 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
925 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
927 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
1019 ushort cfg_lsw; /* 00 power up initialization */
1023 ushort cfg_msw; /* 01 unused */
1024 ushort disc_enable; /* 02 disconnect enable */
1025 ushort wdtr_able; /* 03 Wide DTR able */
1026 ushort sdtr_able; /* 04 Synchronous DTR able */
1027 ushort start_motor; /* 05 send start up motor */
1028 ushort tagqng_able; /* 06 tag queuing able */
1029 ushort bios_scan; /* 07 BIOS device control */
1030 ushort scam_tolerant; /* 08 no scam */
1048 ushort bios_ctrl; /* 12 BIOS control bits */
1065 ushort ultra_able; /* 13 ULTRA speed able */
1066 ushort reserved2; /* 14 reserved */
1069 ushort dvc_cntl; /* 16 control bit for driver */
1070 ushort bug_fix; /* 17 control bit for bug fix */
1071 ushort serial_number_word1; /* 18 Board serial number word 1 */
1072 ushort serial_number_word2; /* 19 Board serial number word 2 */
1073 ushort serial_number_word3; /* 20 Board serial number word 3 */
1074 ushort check_sum; /* 21 EEP check sum */
1076 ushort dvc_err_code; /* 30 last device driver error code */
1077 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1078 ushort adv_err_addr; /* 32 last uc error address */
1079 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1080 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1081 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1082 ushort num_of_err; /* 36 number of error */
1088 ushort cfg_lsw; /* 00 power up initialization */
1092 ushort cfg_msw; /* 01 unused */
1093 ushort disc_enable; /* 02 disconnect enable */
1094 ushort wdtr_able; /* 03 Wide DTR able */
1095 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1096 ushort start_motor; /* 05 send start up motor */
1097 ushort tagqng_able; /* 06 tag queuing able */
1098 ushort bios_scan; /* 07 BIOS device control */
1099 ushort scam_tolerant; /* 08 no scam */
1121 ushort bios_ctrl; /* 12 BIOS control bits */
1138 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1139 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1142 ushort dvc_cntl; /* 16 control bit for driver */
1143 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1144 ushort serial_number_word1; /* 18 Board serial number word 1 */
1145 ushort serial_number_word2; /* 19 Board serial number word 2 */
1146 ushort serial_number_word3; /* 20 Board serial number word 3 */
1147 ushort check_sum; /* 21 EEP check sum */
1149 ushort dvc_err_code; /* 30 last device driver error code */
1150 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1151 ushort adv_err_addr; /* 32 last uc error address */
1152 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1153 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1154 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1155 ushort reserved36; /* 36 reserved */
1156 ushort reserved37; /* 37 reserved */
1157 ushort reserved38; /* 38 reserved */
1158 ushort reserved39; /* 39 reserved */
1159 ushort reserved40; /* 40 reserved */
1160 ushort reserved41; /* 41 reserved */
1161 ushort reserved42; /* 42 reserved */
1162 ushort reserved43; /* 43 reserved */
1163 ushort reserved44; /* 44 reserved */
1164 ushort reserved45; /* 45 reserved */
1165 ushort reserved46; /* 46 reserved */
1166 ushort reserved47; /* 47 reserved */
1167 ushort reserved48; /* 48 reserved */
1168 ushort reserved49; /* 49 reserved */
1169 ushort reserved50; /* 50 reserved */
1170 ushort reserved51; /* 51 reserved */
1171 ushort reserved52; /* 52 reserved */
1172 ushort reserved53; /* 53 reserved */
1173 ushort reserved54; /* 54 reserved */
1174 ushort reserved55; /* 55 reserved */
1175 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1176 ushort cisprt_msw; /* 57 CIS PTR MSW */
1177 ushort subsysvid; /* 58 SubSystem Vendor ID */
1178 ushort subsysid; /* 59 SubSystem ID */
1179 ushort reserved60; /* 60 reserved */
1180 ushort reserved61; /* 61 reserved */
1181 ushort reserved62; /* 62 reserved */
1182 ushort reserved63; /* 63 reserved */
1188 ushort cfg_lsw; /* 00 power up initialization */
1194 ushort cfg_msw; /* 01 unused */
1195 ushort disc_enable; /* 02 disconnect enable */
1196 ushort wdtr_able; /* 03 Wide DTR able */
1197 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1198 ushort start_motor; /* 05 send start up motor */
1199 ushort tagqng_able; /* 06 tag queuing able */
1200 ushort bios_scan; /* 07 BIOS device control */
1201 ushort scam_tolerant; /* 08 no scam */
1223 ushort bios_ctrl; /* 12 BIOS control bits */
1240 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1241 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1244 ushort dvc_cntl; /* 16 control bit for driver */
1245 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1246 ushort serial_number_word1; /* 18 Board serial number word 1 */
1247 ushort serial_number_word2; /* 19 Board serial number word 2 */
1248 ushort serial_number_word3; /* 20 Board serial number word 3 */
1249 ushort check_sum; /* 21 EEP check sum */
1251 ushort dvc_err_code; /* 30 last device driver error code */
1252 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1253 ushort adv_err_addr; /* 32 last uc error address */
1254 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1255 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1256 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1257 ushort reserved36; /* 36 reserved */
1258 ushort reserved37; /* 37 reserved */
1259 ushort reserved38; /* 38 reserved */
1260 ushort reserved39; /* 39 reserved */
1261 ushort reserved40; /* 40 reserved */
1262 ushort reserved41; /* 41 reserved */
1263 ushort reserved42; /* 42 reserved */
1264 ushort reserved43; /* 43 reserved */
1265 ushort reserved44; /* 44 reserved */
1266 ushort reserved45; /* 45 reserved */
1267 ushort reserved46; /* 46 reserved */
1268 ushort reserved47; /* 47 reserved */
1269 ushort reserved48; /* 48 reserved */
1270 ushort reserved49; /* 49 reserved */
1271 ushort reserved50; /* 50 reserved */
1272 ushort reserved51; /* 51 reserved */
1273 ushort reserved52; /* 52 reserved */
1274 ushort reserved53; /* 53 reserved */
1275 ushort reserved54; /* 54 reserved */
1276 ushort reserved55; /* 55 reserved */
1277 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1278 ushort cisprt_msw; /* 57 CIS PTR MSW */
1279 ushort subsysvid; /* 58 SubSystem Vendor ID */
1280 ushort subsysid; /* 59 SubSystem ID */
1281 ushort reserved60; /* 60 reserved */
1282 ushort reserved61; /* 61 reserved */
1283 ushort reserved62; /* 62 reserved */
1284 ushort reserved63; /* 63 reserved */
1805 ushort disc_enable; /* enable disconnection */
1808 ushort control_flag; /* Microcode Control Flag */
1809 ushort mcode_date; /* Microcode date */
1810 ushort mcode_version; /* Microcode version */
1811 ushort serial1; /* EEPROM serial number word 1 */
1812 ushort serial2; /* EEPROM serial number word 2 */
1813 ushort serial3; /* EEPROM serial number word 3 */
1919 ushort err_code; /* fatal error code */
1920 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1921 ushort wdtr_able; /* try WDTR for a device */
1922 ushort sdtr_able; /* try SDTR for a device */
1923 ushort ultra_able; /* try SDTR Ultra speed for a device */
1924 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1925 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1926 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1927 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1928 ushort tagqng_able; /* try tagged queuing with a device */
1929 ushort ppr_able; /* PPR message capable per TID bitmask. */
1931 ushort start_motor; /* start motor command allowed */
1935 ushort no_scam; /* scam_tolerant of EEPROM */
1944 ushort carr_pending_cnt; /* Count of pending carriers. */
2037 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2040 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2083 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2098 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2104 #define ADV_SCSI_BIT_ID_TYPE ushort
2358 ushort asc_n_io_port; /* Number I/O ports. */
2360 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2362 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2382 ushort ioport; /* I/O Port address. */
2385 ushort bios_signature; /* BIOS Signature. */
2386 ushort bios_version; /* BIOS Version. */
2387 ushort bios_codeseg; /* BIOS Code Segment. */
2388 ushort bios_codelen; /* BIOS Code Segment Length. */
2897 ushort major, minor, letter; asc_prt_adv_bios()
2953 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp) asc_get_eeprom_string()
2955 ushort w, num; asc_get_eeprom_string()
2957 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) { asc_get_eeprom_string()
3051 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr) asc_prt_asc_board_eeprom()
3117 ushort word; asc_prt_adv_board_eeprom()
3118 ushort *wordp; asc_prt_adv_board_eeprom()
3119 ushort sdtr_speed = 0; asc_prt_adv_board_eeprom()
3507 ushort chip_scsi_id; asc_prt_adv_board_info()
3508 ushort lramword; asc_prt_adv_board_info()
3510 ushort tagqng_able; asc_prt_adv_board_info()
3511 ushort sdtr_able, wdtr_able; asc_prt_adv_board_info()
3512 ushort wdtr_done, sdtr_done; asc_prt_adv_board_info()
3513 ushort period = 0; asc_prt_adv_board_info()
3831 static void AscSetChipIH(PortAddr iop_base, ushort ins_code) AscSetChipIH()
3898 ushort sig_word; AscFindSignature()
3906 if ((sig_word == (ushort)ASC_1000_ID0W) || AscFindSignature()
3907 (sig_word == (ushort)ASC_1000_ID0W_FIX)) { AscFindSignature()
3916 ushort cfg; AscEnableInterrupt()
3924 ushort cfg; AscDisableInterrupt()
3930 static uchar AscReadLramByte(PortAddr iop_base, ushort addr) AscReadLramByte()
3947 static ushort AscReadLramWord(PortAddr iop_base, ushort addr) AscReadLramWord()
3949 ushort word_data; AscReadLramWord()
3957 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr) AscReadLramDWord()
3959 ushort val_low, val_high; AscReadLramDWord()
3971 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words) AscMemWordSetLram()
3981 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val) AscWriteLramWord()
3987 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val) AscWriteLramByte()
3989 ushort word_data; AscWriteLramByte()
3995 word_data |= (((ushort)byte_val << 8) & 0xFF00); AscWriteLramByte()
3999 word_data |= ((ushort)byte_val & 0x00FF); AscWriteLramByte()
4011 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr, AscMemWordCopyPtrToLram()
4020 * produces a little-endian ushort which is written to AscMemWordCopyPtrToLram()
4022 * the second argument produces a big-endian ushort which AscMemWordCopyPtrToLram()
4027 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); AscMemWordCopyPtrToLram()
4039 ushort s_addr, uchar *s_buffer, int dwords) AscMemDWordCopyPtrToLram()
4045 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */ AscMemDWordCopyPtrToLram()
4046 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */ AscMemDWordCopyPtrToLram()
4058 ushort s_addr, uchar *d_buffer, int words) AscMemWordCopyPtrFromLram()
4061 ushort word; AscMemWordCopyPtrFromLram()
4071 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words) AscMemSumLramWord()
4083 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc) AscInitLram()
4086 ushort s_addr; AscInitLram()
4088 ushort warn_code; AscInitLram()
4093 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) * AscInitLram()
4097 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), AscInitLram()
4099 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), AscInitLram()
4101 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), AscInitLram()
4106 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), AscInitLram()
4108 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), AscInitLram()
4110 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), AscInitLram()
4113 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), AscInitLram()
4115 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), AscInitLram()
4117 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), AscInitLram()
4124 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i); AscInitLram()
4126 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i); AscInitLram()
4128 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i); AscInitLram()
4134 AscLoadMicroCode(PortAddr iop_base, ushort s_addr, AscLoadMicroCode()
4135 const uchar *mcode_buf, ushort mcode_size) AscLoadMicroCode()
4138 ushort mcode_word_size; AscLoadMicroCode()
4139 ushort mcode_chksum; AscLoadMicroCode()
4142 mcode_word_size = (ushort)(mcode_size >> 1); AscLoadMicroCode()
4148 mcode_chksum = (ushort)AscMemSumLramWord(iop_base, AscLoadMicroCode()
4149 (ushort)ASC_CODE_SEC_BEG, AscLoadMicroCode()
4150 (ushort)((mcode_size - AscLoadMicroCode()
4151 s_addr - (ushort) AscLoadMicroCode()
4164 ushort lram_addr; AscInitQLinkVar()
4175 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B, AscInitQLinkVar()
4189 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc) AscInitMicroCodeVar()
4192 ushort warn_code; AscInitMicroCodeVar()
4227 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W); AscInitMicroCodeVar()
4229 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W); AscInitMicroCodeVar()
4253 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc) AscInitAsc1000Driver()
4259 ushort warn_code; AscInitAsc1000Driver()
4435 ushort idle_cmd, ADV_DCNT idle_cmd_parameter) AdvSendIdleCmd()
4448 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0); AdvSendIdleCmd()
4506 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L); AdvResetSB()
4523 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L); AdvResetSB()
4548 ushort warn_code; AdvInitAsc3550Driver()
4551 ushort code_sum; AdvInitAsc3550Driver()
4556 ushort scsi_cfg1; AdvInitAsc3550Driver()
4558 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ AdvInitAsc3550Driver()
4559 ushort wdtr_able = 0, sdtr_able, tagqng_able; AdvInitAsc3550Driver()
4594 ushort bios_version, major, minor; AdvInitAsc3550Driver()
5007 ushort warn_code; AdvInitAsc38C0800Driver()
5010 ushort code_sum; AdvInitAsc38C0800Driver()
5015 ushort scsi_cfg1; AdvInitAsc38C0800Driver()
5018 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ AdvInitAsc38C0800Driver()
5019 ushort wdtr_able, sdtr_able, tagqng_able; AdvInitAsc38C0800Driver()
5507 ushort warn_code; AdvInitAsc38C1600Driver()
5510 ushort code_sum; AdvInitAsc38C1600Driver()
5515 ushort scsi_cfg1; AdvInitAsc38C1600Driver()
5518 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ AdvInitAsc38C1600Driver()
5519 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able; AdvInitAsc38C1600Driver()
6012 ushort wdtr_able, sdtr_able, tagqng_able; AdvResetChipAndSB()
6013 ushort ppr_able = 0; AdvResetChipAndSB()
6016 ushort bios_sig; AdvResetChipAndSB()
6313 ushort target_bit; AdvISR()
6421 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code) AscSetLibErrorCode()
6435 ushort loop; AscAckInterrupt()
6563 ushort halt_q_addr; AscIsrChipHalted()
6565 ushort int_halt_code; AscIsrChipHalted()
6589 (ushort)(halt_q_addr + AscIsrChipHalted()
6590 (ushort)ASC_SCSIQ_B_TARGET_IX)); AscIsrChipHalted()
6592 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL)); AscIsrChipHalted()
6695 (ushort)(halt_q_addr + AscIsrChipHalted()
6696 (ushort)ASC_SCSIQ_B_CNTL), AscIsrChipHalted()
6711 (ushort)(halt_q_addr + AscIsrChipHalted()
6712 (ushort)ASC_SCSIQ_B_CNTL), AscIsrChipHalted()
6725 (ushort)(halt_q_addr + AscIsrChipHalted()
6726 (ushort)ASC_SCSIQ_B_CNTL), AscIsrChipHalted()
6752 (ushort)(halt_q_addr + AscIsrChipHalted()
6753 (ushort)ASC_SCSIQ_B_CNTL), q_cntl); AscIsrChipHalted()
6756 (ushort)(halt_q_addr + (ushort) AscIsrChipHalted()
6768 (ushort)(halt_q_addr + AscIsrChipHalted()
6769 (ushort)ASC_SCSIQ_B_TAG_CODE), AscIsrChipHalted()
6773 (ushort)(halt_q_addr + (ushort) AscIsrChipHalted()
6777 (ushort)(halt_q_addr + AscIsrChipHalted()
6778 (ushort)ASC_SCSIQ_B_STATUS), AscIsrChipHalted()
6781 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B); AscIsrChipHalted()
6783 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy); AscIsrChipHalted()
6805 (ushort)(halt_q_addr + AscIsrChipHalted()
6806 (ushort)ASC_SCSIQ_B_CNTL), q_cntl); AscIsrChipHalted()
6812 (ushort)((ushort)halt_q_addr + AscIsrChipHalted()
6813 (ushort) AscIsrChipHalted()
6817 (ushort)((ushort)ASC_QADR_BEG + AscIsrChipHalted()
6818 (ushort)target_ix)); AscIsrChipHalted()
6822 (ushort)ASCV_SCSIBUSY_B); AscIsrChipHalted()
6825 (ushort)ASCV_SCSIBUSY_B, scsi_busy); AscIsrChipHalted()
6835 (ushort)((ushort) AscIsrChipHalted()
6837 + (ushort) AscIsrChipHalted()
6858 ushort q_addr; AscIsrChipHalted()
6864 ushort sg_list_dwords; AscIsrChipHalted()
6865 ushort sg_entry_cnt; AscIsrChipHalted()
6869 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP); AscIsrChipHalted()
6884 (ushort) AscIsrChipHalted()
6892 (ushort)(q_addr + AscIsrChipHalted()
6896 (ushort)(q_addr + AscIsrChipHalted()
6904 (ushort)(q_addr + AscIsrChipHalted()
6905 (ushort)ASC_SCSIQ_B_SG_WK_QP), AscIsrChipHalted()
6999 (ushort)(q_addr + AscIsrChipHalted()
7017 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
7026 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words) DvcGetQinfo()
7029 ushort word; DvcGetQinfo()
7045 ushort q_addr, _AscCopyLramScsiDoneQ()
7048 ushort _val; _AscCopyLramScsiDoneQ()
7057 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS)); _AscCopyLramScsiDoneQ()
7061 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL)); _AscCopyLramScsiDoneQ()
7065 (ushort)(q_addr + _AscCopyLramScsiDoneQ()
7066 (ushort)ASC_SCSIQ_B_SENSE_LEN)); _AscCopyLramScsiDoneQ()
7074 (ushort)(q_addr + _AscCopyLramScsiDoneQ()
7075 (ushort) _AscCopyLramScsiDoneQ()
7082 (ushort)(q_addr + (ushort) _AscCopyLramScsiDoneQ()
7218 ushort q_addr; AscIsrQDone()
7219 ushort sg_q_addr; AscIsrQDone()
7231 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD)); AscIsrQDone()
7238 (ushort)(q_addr + AscIsrQDone()
7239 (ushort)ASC_SCSIQ_B_STATUS), AscIsrQDone()
7250 (ushort)(sg_q_addr AscIsrQDone()
7251 + (ushort) AscIsrQDone()
7263 (ushort)(sg_q_addr + (ushort) AscIsrQDone()
7272 (ushort)((ushort) AscIsrQDone()
7274 + (ushort) AscIsrQDone()
7278 scsi_busy = AscReadLramByte(iop_base, (ushort) AscIsrQDone()
7282 (ushort)ASCV_SCSIBUSY_B, AscIsrQDone()
7340 (ushort)(q_addr + (ushort) AscIsrQDone()
7367 ushort saved_ram_addr; AscISR()
7713 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id), advansys_narrow_slave_configure()
8259 ushort q_addr; AscAllocFreeQueue()
8265 (ushort)(q_addr + AscAllocFreeQueue()
8267 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD)); AscAllocFreeQueue()
8288 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8297 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) DvcPutScsiQ()
8308 ((ushort)outbuf[i + 1] << 8) | outbuf[i]); DvcPutScsiQ()
8314 ushort q_addr; AscPutReadyQueue()
8348 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS), AscPutReadyQueue()
8349 (ushort)(((ushort)scsiq->q1. AscPutReadyQueue()
8350 q_no << 8) | (ushort)QS_READY)); AscPutReadyQueue()
8364 ushort sg_list_dwords; AscPutReadySgListQueue()
8365 ushort sg_index; AscPutReadySgListQueue()
8366 ushort sg_entry_cnt; AscPutReadySgListQueue()
8367 ushort q_addr; AscPutReadySgListQueue()
8463 (ushort)(q_addr + AscPutReadySgListQueue()
8556 ushort sg_entry_cnt = 0; AscExeScsiQueue()
8557 ushort sg_entry_cnt_minus_one = 0; AscExeScsiQueue()
8675 (uchar)((ushort)addr & 0x0003); AscExeScsiQueue()
8733 (uchar)((ushort)addr & 0x0003); AscExeScsiQueue()
8743 if (((ushort)data_cnt & 0x01FF) AscExeScsiQueue()
9013 static ushort AscGetEisaChipCfg(PortAddr iop_base) AscGetEisaChipCfg()
9058 ushort cfg_lsw; AscSetChipScsiID()
9065 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8); AscSetChipScsiID()
9098 outp(0x000B, (ushort)(0xC0 | dma_channel)); AscEnableIsaDma()
9101 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4))); AscEnableIsaDma()
9102 outp(0x00D4, (ushort)(dma_channel - 4)); AscEnableIsaDma()
9125 static ASC_DCNT AscGetMaxDmaCount(ushort bus_type) AscGetMaxDmaCount()
9135 static ushort AscGetIsaDmaChannel(PortAddr iop_base) AscGetIsaDmaChannel()
9137 ushort channel; AscGetIsaDmaChannel()
9147 static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel) AscSetIsaDmaChannel()
9149 ushort cfg_lsw; AscSetIsaDmaChannel()
9186 static ushort AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc) AscInitAscDvcVar()
9190 ushort warn_code; AscInitAscDvcVar()
9293 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr) AscReadEEPWord()
9295 ushort read_wval; AscReadEEPWord()
9308 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, AscGetEEPConfig()
9309 ushort bus_type) AscGetEEPConfig()
9311 ushort wval; AscGetEEPConfig()
9312 ushort sum; AscGetEEPConfig()
9313 ushort *wbuf; AscGetEEPConfig()
9319 wbuf = (ushort *)cfg_buf; AscGetEEPConfig()
9358 ushort q_addr; AscTestExternalLram()
9359 ushort saved_word; AscTestExternalLram()
9382 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg) AscWriteEEPDataReg()
9384 ushort read_back; AscWriteEEPDataReg()
9401 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val) AscWriteEEPWord()
9403 ushort read_wval; AscWriteEEPWord()
9422 ushort bus_type) AscSetEEPConfigOnce()
9425 ushort *wbuf; AscSetEEPConfigOnce()
9426 ushort word; AscSetEEPConfigOnce()
9427 ushort sum; AscSetEEPConfigOnce()
9433 wbuf = (ushort *)cfg_buf; AscSetEEPConfigOnce()
9477 wbuf = (ushort *)cfg_buf; AscSetEEPConfigOnce()
9518 ushort bus_type) AscSetEEPConfig()
9536 static ushort AscInitFromEEP(ASC_DVC_VAR *asc_dvc) AscInitFromEEP()
9541 ushort chksum; AscInitFromEEP()
9542 ushort warn_code; AscInitFromEEP()
9543 ushort cfg_msw, cfg_lsw; AscInitFromEEP()
10228 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr) AdvReadEEPWord()
10242 ushort *wbuf; AdvSet3550EEPConfig()
10243 ushort addr, chksum; AdvSet3550EEPConfig()
10244 ushort *charfields; AdvSet3550EEPConfig()
10246 wbuf = (ushort *)cfg_buf; AdvSet3550EEPConfig()
10247 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar; AdvSet3550EEPConfig()
10258 ushort word; AdvSet3550EEPConfig()
10287 ushort word; AdvSet3550EEPConfig()
10309 ushort *wbuf; AdvSet38C0800EEPConfig()
10310 ushort *charfields; AdvSet38C0800EEPConfig()
10311 ushort addr, chksum; AdvSet38C0800EEPConfig()
10313 wbuf = (ushort *)cfg_buf; AdvSet38C0800EEPConfig()
10314 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar; AdvSet38C0800EEPConfig()
10325 ushort word; AdvSet38C0800EEPConfig()
10354 ushort word; AdvSet38C0800EEPConfig()
10376 ushort *wbuf; AdvSet38C1600EEPConfig()
10377 ushort *charfields; AdvSet38C1600EEPConfig()
10378 ushort addr, chksum; AdvSet38C1600EEPConfig()
10380 wbuf = (ushort *)cfg_buf; AdvSet38C1600EEPConfig()
10381 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar; AdvSet38C1600EEPConfig()
10392 ushort word; AdvSet38C1600EEPConfig()
10421 ushort word; AdvSet38C1600EEPConfig()
10442 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base, AdvGet3550EEPConfig()
10445 ushort wval, chksum; AdvGet3550EEPConfig()
10446 ushort *wbuf; AdvGet3550EEPConfig()
10448 ushort *charfields; AdvGet3550EEPConfig()
10450 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar; AdvGet3550EEPConfig()
10451 wbuf = (ushort *)cfg_buf; AdvGet3550EEPConfig()
10485 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base, AdvGet38C0800EEPConfig()
10488 ushort wval, chksum; AdvGet38C0800EEPConfig()
10489 ushort *wbuf; AdvGet38C0800EEPConfig()
10491 ushort *charfields; AdvGet38C0800EEPConfig()
10493 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar; AdvGet38C0800EEPConfig()
10494 wbuf = (ushort *)cfg_buf; AdvGet38C0800EEPConfig()
10528 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base, AdvGet38C1600EEPConfig()
10531 ushort wval, chksum; AdvGet38C1600EEPConfig()
10532 ushort *wbuf; AdvGet38C1600EEPConfig()
10534 ushort *charfields; AdvGet38C1600EEPConfig()
10536 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar; AdvGet38C1600EEPConfig()
10537 wbuf = (ushort *)cfg_buf; AdvGet38C1600EEPConfig()
10581 ushort warn_code; AdvInitFrom3550EEP()
10731 ushort warn_code; AdvInitFrom38C0800EEP()
10734 ushort sdtr_speed = 0; AdvInitFrom38C0800EEP()
10930 ushort warn_code; AdvInitFrom38C1600EEP()
10933 ushort sdtr_speed = 0; AdvInitFrom38C1600EEP()
11173 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1), AdvInitGetConfig()
11174 (ushort)ADV_CHIP_ID_BYTE); AdvInitGetConfig()
11177 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0), AdvInitGetConfig()
11178 (ushort)ADV_CHIP_ID_WORD); AdvInitGetConfig()
11422 (ushort)inp(iop + 1), (ushort)inpw(iop)); advansys_board_found()
H A Deata.c647 ushort cp_pad_len; /* Number of pad bytes after cp_len */
651 ushort queue_size; /* Max number of cp that can be queued */
652 ushort unused;
653 ushort scatt_size; /* Max number of entries in scatter/gather table */
703 ushort ipad[247];
708 ushort len; /* Number of bytes following this field */
1009 static int read_pio(unsigned long iobase, ushort * start, ushort * end) read_pio()
1012 ushort *p; read_pio()
1106 if (read_pio(port_base, (ushort *) & info, (ushort *) & info.ipad[0])) { port_detect()
1247 cf->len = (ushort) H2DEV16((ushort) 510); port_detect()
1273 shost->sg_tablesize = (ushort) info.scatt_size; port_detect()
1274 shost->this_id = (ushort) info.host_addr[3]; port_detect()
1275 shost->can_queue = (ushort) info.queue_size; port_detect()
H A Dpas16.c591 module_param(pas16_addr, ushort, 0);
H A Daha1740.c123 ushort don:1, /* Command Done - No Error */ aha1740_makecode()
H A Dmegaraid.c72 module_param(max_sectors_per_io, ushort, 0);
77 module_param(max_mbox_busy_wait, ushort, 0);
/linux-4.1.27/drivers/staging/slicoss/
H A Dslic.h108 ushort index;
109 ushort bottombits; /* to denote num bufs to card */
117 ushort type;
119 ushort offset;
144 ushort numbufs;
290 ushort ether_type;
327 ushort reg_type[32];
328 ushort reg_offset[32];
410 ushort vendid;
411 ushort devid;
412 ushort subsysid;
435 ushort devflags_prev;
461 ushort slic_handle_ix;
H A Dslicoss.c1335 pslic_handle->offset = (ushort) adapter->slic_handle_ix++; slic_cmdq_addcmdpage()
2657 ushort eecodesize; slic_card_init()
2658 ushort dramsize; slic_card_init()
2659 ushort ee_chksum; slic_card_init()
2660 ushort calc_chksum; slic_card_init()
2866 ushort index; slic_init_adapter()
2929 ushort card_hostid; slic_card_locate()
2950 card_hostid = (ushort) readw(hostid_reg); slic_card_locate()
/linux-4.1.27/fs/xfs/libxfs/
H A Dxfs_inode_buf.h31 ushort im_len; /* length in BBs of inode chunk */
32 ushort im_boffset; /* inode offset in block in bytes */
H A Dxfs_log_recover.h55 #define ITEM_TYPE(i) (*(ushort *)(i)->ri_buf[0].i_addr)
H A Dxfs_log_format.h459 ushort blf_flags; /* misc state */
460 ushort blf_len; /* number of blocks in this buf */
H A Dxfs_ialloc.c1893 imap->im_boffset = (ushort)(offset << mp->m_sb.sb_inodelog); xfs_imap()
1921 imap->im_boffset = (ushort)(offset << mp->m_sb.sb_inodelog); xfs_imap()
/linux-4.1.27/drivers/block/aoe/
H A Daoe.h135 ushort nframes; /* cap on frames to use */
140 ushort nout; /* number of AoE commands outstanding */
141 ushort maxout; /* current value for max outstanding */
142 ushort next_cwnd; /* incr maxout after decrementing to zero */
143 ushort ssthresh; /* slow start threshold */
212 void aoecmd_cfg(ushort aoemajor, unsigned char aoeminor);
H A Daoecmd.c414 aoecmd_cfg_pkts(ushort aoemajor, unsigned char aoeminor, struct sk_buff_head *queue) aoecmd_cfg_pkts()
1428 aoecmd_cfg(ushort aoemajor, unsigned char aoeminor) aoecmd_cfg()
/linux-4.1.27/include/linux/
H A Dvt_kern.h70 int con_set_unimap(struct vc_data *vc, ushort ct, struct unipair __user *list);
71 int con_get_unimap(struct vc_data *vc, ushort ct, ushort __user *uct, struct unipair __user *list);
100 int con_set_unimap(struct vc_data *vc, ushort ct, struct unipair __user *list) con_set_unimap()
105 int con_get_unimap(struct vc_data *vc, ushort ct, ushort __user *uct, con_get_unimap()
H A Dtypes.h90 typedef unsigned short ushort; typedef
H A Dmoduleparam.h119 * byte, short, ushort, int, uint, long, ulong
H A Djbd2.h58 extern ushort jbd2_journal_enable_debug;
/linux-4.1.27/drivers/net/ethernet/realtek/
H A Datp.h9 ushort pad; /* Pad. */
10 ushort rx_count;
11 ushort rx_status; /* Unknown bit assignments :-<. */
12 ushort cur_addr; /* Apparently the current buffer address(?) */
/linux-4.1.27/drivers/staging/unisys/common-spar/include/channels/
H A Dcontrolframework.h46 /* Note: don't use high bit unless we need to switch to ushort
/linux-4.1.27/drivers/staging/dgnc/
H A Ddgnc_driver.h348 ushort ch_r_head; /* Head location of the read queue */
349 ushort ch_r_tail; /* Tail location of the read queue */
352 ushort ch_e_head; /* Head location of the error queue */
353 ushort ch_e_tail; /* Tail location of the error queue */
356 ushort ch_w_head; /* Head location of the write queue */
357 ushort ch_w_tail; /* Tail location of the write queue */
H A Ddgnc_cls.c824 ushort head; cls_copy_data_from_uart_to_queue()
825 ushort tail; cls_copy_data_from_uart_to_queue()
978 ushort head; cls_copy_data_from_queue_to_uart()
979 ushort tail; cls_copy_data_from_queue_to_uart()
H A Ddgnc_tty.c496 ushort head; dgnc_input()
497 ushort tail; dgnc_input()
1518 ushort thead; dgnc_tty_chars_in_buffer()
1519 ushort ttail; dgnc_tty_chars_in_buffer()
1621 ushort head; dgnc_tty_write_room()
1622 ushort tail; dgnc_tty_write_room()
1623 ushort tmask; dgnc_tty_write_room()
1704 ushort head; dgnc_tty_write()
1705 ushort tail; dgnc_tty_write()
1706 ushort tmask; dgnc_tty_write()
H A Ddgnc_neo.c1108 ushort head; neo_copy_data_from_uart_to_queue()
1109 ushort tail; neo_copy_data_from_uart_to_queue()
1409 ushort head; neo_copy_data_from_queue_to_uart()
1410 ushort tail; neo_copy_data_from_queue_to_uart()
/linux-4.1.27/drivers/block/
H A Damiflop.c606 ushort adk; raw_write()
664 ushort *ptr = (ushort *)raw, *endp = (ushort *)end; scan_sync()
861 *(ushort *)ptr = (ptr[-1]&1) ? 0x2AA8 : 0xAAA8; amiga_write()
932 static ushort dos_crc(void * data_a3, int data_d0, int data_d1, int data_d3) dos_crc()
989 static inline ushort dos_hdr_crc (struct dos_header *hdr) dos_hdr_crc()
994 static inline ushort dos_data_crc(unsigned char *data) dos_data_crc()
999 static inline unsigned char dos_decode_byte(ushort word) dos_decode_byte()
1001 register ushort w2; dos_decode_byte()
1056 } while (*((ushort *)raw)!=0x5554); /* loop usually only once done */ dos_read()
1058 raw = dos_decode((unsigned char *)&hdr,(ushort *) raw,8); dos_read()
1103 if (*((ushort *)raw)!=0x5545) { dos_read()
1111 raw = dos_decode((unsigned char *)(unit[drive].trackbuf + (hdr.sec - 1) * 512), (ushort *) raw, 512); dos_read()
1112 raw = dos_decode((unsigned char *)data_crc,(ushort *) raw,4); dos_read()
1130 static inline ushort dos_encode_byte(unsigned char byte) dos_encode_byte()
1133 register ushort word; dos_encode_byte()
1143 static void dos_encode_block(ushort *dest, unsigned char *src, int len) dos_encode_block()
1159 static ushort crc[2]={0,0x4e4e}; ms_putsec()
1177 dos_encode_block((ushort *)raw,(unsigned char *) &hdr.track,28); ms_putsec()
1189 dos_encode_block((ushort *)raw, ms_putsec()
1195 dos_encode_block((ushort *) raw,(unsigned char *)crc,4); ms_putsec()
1235 *(ushort *)ptr = 0xaaa8; /* MFM word before is always 0x9254 */ dos_write()
H A Dcpqarray.c607 ushort vendor_id, device_id, command; cpqarray_pci_init()
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-cpm.c59 ushort rbase; /* Rx Buffer descriptor base address */
60 ushort tbase; /* Tx Buffer descriptor base address */
63 ushort mrblr; /* Max receive buffer length */
66 ushort rbptr; /* Rx Buffer descriptor pointer */
67 ushort rbc; /* Internal */
71 ushort tbptr; /* Tx Buffer descriptor pointer */
72 ushort tbc; /* Internal */
75 ushort rpbase; /* Relocation pointer */
H A Di2c-parport-light.c41 module_param(base, ushort, 0);
H A Di2c-tiny-usb.c39 module_param(delay, ushort, 0);
H A Di2c-sis5595.c122 module_param(force_addr, ushort, 0);
H A Di2c-ali15x3.c122 module_param(force_addr, ushort, 0);
H A Di2c-viapro.c97 module_param(force_addr, ushort, 0);
/linux-4.1.27/include/net/
H A Dping.h27 * gid_t is either uint or ushort. We want to pass it to
/linux-4.1.27/net/netfilter/
H A Dnf_conntrack_tftp.c30 module_param_array(ports, ushort, &ports_c, 0400);
H A Dnf_conntrack_sane.c43 module_param_array(ports, ushort, &ports_c, 0400);
H A Dnf_conntrack_irc.c49 module_param_array(ports, ushort, &ports_c, 0400);
H A Dnf_conntrack_ftp.c44 module_param_array(ports, ushort, &ports_c, 0400);
H A Dnf_conntrack_sip.c38 module_param_array(ports, ushort, &ports_c, 0400);
/linux-4.1.27/drivers/usb/atm/
H A Dxusbatm.c36 XUSBATM_PARM(vendor, unsigned short, ushort, "USB device vendor");
37 XUSBATM_PARM(product, unsigned short, ushort, "USB device product");
/linux-4.1.27/drivers/video/fbdev/
H A Ddnfb.c153 ushort *src, dummy; dnfb_copyarea()
158 src = (ushort *)(info->screen_base + area->sy * info->fix.line_length + dnfb_copyarea()
H A Duvesafb.c2006 module_param(maxclk, ushort, 0);
2008 module_param(maxhf, ushort, 0);
2011 module_param(maxvf, ushort, 0);
2017 module_param(vbemode, ushort, 0);
/linux-4.1.27/drivers/tty/vt/
H A Dconsolemap.c344 int con_set_trans_new(ushort __user * arg) con_set_trans_new()
364 int con_get_trans_new(ushort __user * arg) con_get_trans_new()
530 int con_set_unimap(struct vc_data *vc, ushort ct, struct unipair __user *list) con_set_unimap()
727 int con_get_unimap(struct vc_data *vc, ushort ct, ushort __user *uct, struct unipair __user *list) con_get_unimap()
H A Dvt_ioctl.c825 ushort ll,cc; vt_ioctl()
850 ushort ll,cc,vlin,clin,vcol,ccol; vt_ioctl()
H A Dvt.c2531 const ushort *start; vt_console_print()
2532 ushort cnt = 0; vt_console_print()
2533 ushort myx; vt_console_print()
2563 start = (ushort *)vc->vc_pos; vt_console_print()
2580 start = (ushort *)vc->vc_pos; vt_console_print()
2587 start = (ushort *)vc->vc_pos; vt_console_print()
H A Dkeyboard.c1773 ushort *key_map, *new_map, val, ov; vt_do_kdsk_ioctl()
/linux-4.1.27/drivers/scsi/isci/
H A Dinit.c103 module_param(ssp_max_occ_to, ushort, 0);
107 module_param(stp_max_occ_to, ushort, 0);
111 module_param(ssp_inactive_to, ushort, 0);
115 module_param(stp_inactive_to, ushort, 0);
/linux-4.1.27/drivers/s390/char/
H A Ddefkeymap.c87 ushort *key_maps[MAX_NR_KEYMAPS] = {
H A Dkeyboard.c259 to_utf8(struct tty_port *port, ushort c) to_utf8()
336 ushort *key_map, val, ov; do_kdsk_ioctl()
/linux-4.1.27/fs/ext4/
H A Dmballoc.h40 extern ushort ext4_mballoc_debug;
H A Dmballoc.c32 ushort ext4_mballoc_debug __read_mostly;
34 module_param_named(mballoc_debug, ext4_mballoc_debug, ushort, 0644);
/linux-4.1.27/drivers/hwmon/pmbus/
H A Dzl6100.c60 static ushort delay = ZL6100_WAIT_TIME;
61 module_param(delay, ushort, 0644);
/linux-4.1.27/drivers/char/hw_random/
H A Dcore.c66 module_param(current_quality, ushort, 0644);
69 module_param(default_quality, ushort, 0644);
/linux-4.1.27/ipc/
H A Dsem.c1050 static int count_semcnt(struct sem_array *sma, ushort semnum, count_semcnt()
1344 ushort fast_sem_io[SEMMSL_FAST]; semctl_main()
1345 ushort *sem_io = fast_sem_io; semctl_main()
1371 ushort __user *array = p; semctl_main()
1386 sem_io = ipc_alloc(sizeof(ushort)*nsems); semctl_main()
1404 if (copy_to_user(array, sem_io, nsems*sizeof(ushort))) semctl_main()
1420 sem_io = ipc_alloc(sizeof(ushort)*nsems); semctl_main()
1427 if (copy_from_user(sem_io, p, nsems*sizeof(ushort))) { semctl_main()
1496 ipc_free(sem_io, sizeof(ushort)*nsems); semctl_main()
/linux-4.1.27/drivers/message/fusion/
H A Dmptctl.h388 ushort host_no; /* SCSI Host number, if scsi driver not loaded*/
411 ushort host_no; /* SCSI Host number, if scsi driver not loaded*/
H A Dmptbase.h587 ushort sel_timeout[MPT_MAX_FC_DEVICES];
/linux-4.1.27/drivers/usb/gadget/udc/
H A Dnet2272.c84 static ushort dma_ep = 1;
85 module_param(dma_ep, ushort, 0644);
93 static ushort dma_mode = 2;
94 module_param(dma_mode, ushort, 0644);
108 static ushort fifo_mode = 0;
109 module_param(fifo_mode, ushort, 0644);
117 static ushort enable_suspend = 0;
118 module_param(enable_suspend, ushort, 0644);
H A Dnet2280.c94 static ushort fifo_mode;
97 module_param(fifo_mode, ushort, 0644);
/linux-4.1.27/drivers/usb/serial/
H A Dgeneric.c31 module_param(vendor, ushort, 0);
34 module_param(product, ushort, 0);
/linux-4.1.27/drivers/hwmon/
H A Dsmsc47b397.c45 module_param(force_id, ushort, 0);
H A Dthmc50.c43 module_param_array(adm1022_temp3, ushort, &adm1022_temp3_num, 0);
H A Dgl520sm.c38 module_param(extra_sensor_type, ushort, 0);
H A Dsmsc47m1.c46 module_param(force_id, ushort, 0);
H A Dpc87427.c42 module_param(force_id, ushort, 0);
H A Dsis5595.c76 module_param(force_addr, ushort, 0);
H A Dvia686a.c56 module_param(force_addr, ushort, 0);
H A Dvt1211.c49 module_param(force_id, ushort, 0);
H A Dw83627ehf.c82 module_param(force_id, ushort, 0);
86 module_param(fan_debounce, ushort, 0);
H A Df71805f.c48 module_param(force_id, ushort, 0);
H A Dpc87360.c66 module_param(force_id, ushort, 0);
H A Df71882fg.c109 module_param(force_id, ushort, 0);
H A Dw83627hf.c79 module_param(force_id, ushort, 0);
H A Dnct6775.c79 module_param(force_id, ushort, 0);
83 module_param(fan_debounce, ushort, 0);
H A Ddme1737.c53 module_param(force_id, ushort, 0);
H A Dit87.c76 module_param(force_id, ushort, 0);
/linux-4.1.27/drivers/pci/hotplug/
H A Dcpcihp_generic.c223 module_param(port, ushort, 0);
/linux-4.1.27/drivers/watchdog/
H A Dmpc8xxx_wdt.c57 module_param(timeout, ushort, 0);
H A Dsch311x_wdt.c67 module_param(force_id, ushort, 0);
H A Df71808e_wdt.c83 module_param(force_id, ushort, 0);
/linux-4.1.27/drivers/staging/dgap/
H A Ddgap.h1059 ushort dl_srev; /* Software revision number */
1060 ushort dl_lrev; /* Low revision number */
1061 ushort dl_hrev; /* High revision number */
1062 ushort dl_seg; /* Start segment address */
1063 ushort dl_size; /* Number of bytes to download */
/linux-4.1.27/drivers/media/radio/si470x/
H A Dradio-si470x-common.c128 module_param(space, ushort, 0444);
135 module_param(de, ushort, 0444);
H A Dradio-si470x-i2c.c71 module_param(max_rds_errors, ushort, 0644);
H A Dradio-si470x-usb.c88 module_param(max_rds_errors, ushort, 0644);
/linux-4.1.27/drivers/staging/olpc_dcon/
H A Dolpc_dcon.c37 static ushort resumeline = 898;
38 module_param(resumeline, ushort, 0444);
/linux-4.1.27/drivers/video/fbdev/mbx/
H A Dmbxfb.c237 ushort hbps, ht, hfps, has; mbxfb_set_par()
238 ushort vbps, vt, vfps, vas; mbxfb_set_par()
/linux-4.1.27/drivers/i2c/
H A Di2c-stub.c44 module_param_array(chip_addr, ushort, NULL, S_IRUGO);
/linux-4.1.27/drivers/net/ethernet/3com/
H A D3c509.c189 static ushort id_read_eeprom(int index);
190 static ushort read_eeprom(int ioaddr, int index);
632 static ushort read_eeprom(int ioaddr, int index) read_eeprom()
642 static ushort id_read_eeprom(int index) id_read_eeprom()
/linux-4.1.27/drivers/net/wireless/brcm80211/brcmfmac/
H A Dsdio.h194 ushort max_segment_count;
/linux-4.1.27/drivers/infiniband/hw/ipath/
H A Dipath_init_chip.c53 static ushort ipath_cfgports;
55 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
64 static ushort ipath_kpiobufs;
H A Dipath_kernel.h320 void (*ipath_f_config_ports)(struct ipath_devdata *, ushort);
H A Dipath_iba6110.c1704 static void ipath_ht_config_ports(struct ipath_devdata *dd, ushort cfgports) ipath_ht_config_ports()
/linux-4.1.27/include/linux/usb/
H A Dcomposite.h531 module_param_named(idVendor, coverwrite.idVendor, ushort, S_IRUGO); \
534 module_param_named(idProduct, coverwrite.idProduct, ushort, S_IRUGO); \
537 module_param_named(bcdDevice, coverwrite.bcdDevice, ushort, S_IRUGO); \
/linux-4.1.27/drivers/infiniband/hw/qib/
H A Dqib_init.c70 ushort qib_cfgctxts;
71 module_param_named(cfgctxts, qib_cfgctxts, ushort, S_IRUGO);
83 ushort qib_mini_init;
84 module_param_named(mini_init, qib_mini_init, ushort, S_IRUGO);
H A Dqib_sdma.c42 static ushort sdma_descq_cnt = 256;
43 module_param_named(sdma_descq_cnt, sdma_descq_cnt, ushort, S_IRUGO);
H A Dqib.h1473 extern ushort qib_cfgctxts;
1474 extern ushort qib_num_cfg_vls;
1475 extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */
H A Dqib_iba7322.c110 ushort qib_num_cfg_vls = 2;
111 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
114 static ushort qib_chase = 1;
115 module_param_named(chase, qib_chase, ushort, S_IRUGO);
118 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
119 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
123 static ushort qib_singleport;
124 module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
127 static ushort qib_krcvq01_no_msi;
128 module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO);
5987 static ushort sdma_fetch_prio = 8;
5988 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
/linux-4.1.27/net/netfilter/ipvs/
H A Dip_vs_ftp.c57 module_param_array(ports, ushort, &ports_count, 0444);
/linux-4.1.27/drivers/net/phy/
H A Ddp83640.c169 static ushort gpio_tab[GPIO_TABLE_SIZE] = {
174 module_param_array(gpio_tab, ushort, NULL, 0444);
/linux-4.1.27/drivers/net/wireless/ath/wil6210/
H A Dmain.c36 module_param(rx_ring_overflow_thrsh, ushort, S_IRUGO);
/linux-4.1.27/kernel/
H A Dparams.c265 STANDARD_PARAM_DEF(ushort, unsigned short, "%hu", kstrtou16);
/linux-4.1.27/net/9p/
H A Dtrans_rdma.c628 cl.sin_port = htons((ushort)port); p9_rdma_bind_privport()
H A Dtrans_fd.c915 cl.sin_port = htons((ushort)port); p9_bind_privport()
/linux-4.1.27/drivers/usb/musb/
H A Dmusb_core.c1109 static ushort fifo_mode;
1112 module_param(fifo_mode, ushort, 0);
/linux-4.1.27/fs/nfs/
H A Dsuper.c2863 module_param(max_session_slots, ushort, 0644);
2866 module_param(send_implementation_id, ushort, 0644);
/linux-4.1.27/drivers/net/wireless/mwifiex/
H A Dmain.c32 module_param(driver_mode, ushort, 0);
/linux-4.1.27/drivers/atm/
H A Dhorizon.c2860 module_param(debug, ushort, 0644);
2861 module_param(vpi_bits, ushort, 0);
H A Dambassador.c2361 module_param(debug, ushort, 0644);
/linux-4.1.27/drivers/usb/misc/
H A Dusbtest.c2528 module_param(vendor, ushort, 0);
2532 module_param(product, ushort, 0);
/linux-4.1.27/fs/jbd2/
H A Djournal.c54 ushort jbd2_journal_enable_debug __read_mostly;
57 module_param_named(jbd2_debug, jbd2_journal_enable_debug, ushort, 0644);
/linux-4.1.27/drivers/char/ipmi/
H A Dipmi_ssif.c1125 module_param_array(addr, ushort, &num_addrs, 0);
/linux-4.1.27/fs/
H A Dexec.c1443 if (request_module("binfmt-%04x", *(ushort *)(bprm->buf + 2)) < 0) search_binary_handler()
/linux-4.1.27/drivers/net/can/
H A Dgrcan.c1518 GRCAN_MODULE_PARAM(name, ushort, GRCAN_NOT_BOOL, desc)
/linux-4.1.27/drivers/scsi/cxgbi/cxgb4i/
H A Dcxgb4i.c71 module_param(cxgb4i_sport_base, ushort, 0644);
/linux-4.1.27/drivers/scsi/sym53c8xx_2/
H A Dsym_glue.c61 module_param_named(cmd_per_lun, sym_driver_setup.max_tag, ushort, 0);
/linux-4.1.27/drivers/net/ethernet/emulex/benet/
H A Dbe_main.c40 static ushort rx_frag_size = 2048;
41 module_param(rx_frag_size, ushort, S_IRUGO);
/linux-4.1.27/drivers/scsi/lpfc/
H A Dlpfc_bsg.c1544 icmd->ulpContext = (ushort) tag; lpfc_issue_ct_rsp()
2816 bpl->tus.f.bdeSize = (ushort) cnt; diag_cmd_data_alloc()
H A Dlpfc_hbadisc.c4418 if (icmd->ulpContext == (volatile ushort)ndlp->nlp_rpi) { lpfc_check_sli_ndlp()
/linux-4.1.27/fs/xfs/
H A Dxfs_log_recover.c1628 ushort flags) xlog_peek_buffer_cancelled()
1668 ushort flags) xlog_check_buffer_cancelled()
/linux-4.1.27/sound/pci/ac97/
H A Dac97_patch.c3525 ushort usSM51, usMS; snd_ac97_vt1617a_smart51_get()
3545 ushort usSM51, usMS, usReg; snd_ac97_vt1617a_smart51_put()
/linux-4.1.27/drivers/isdn/i4l/
H A Disdn_net.c1986 ushort max_hlhdr_len = 0; isdn_net_init()
/linux-4.1.27/drivers/net/
H A Dvxlan.c69 module_param_named(udp_port, vxlan_port, ushort, 0444);
/linux-4.1.27/drivers/scsi/mpt3sas/
H A Dmpt3sas_scsih.c105 static ushort max_sectors = 0xFFFF;
106 module_param(max_sectors, ushort, 0);
/linux-4.1.27/drivers/scsi/mpt2sas/
H A Dmpt2sas_scsih.c103 static ushort max_sectors = 0xFFFF;
104 module_param(max_sectors, ushort, 0);

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