1/* 2 * Freescale CPM1/CPM2 I2C interface. 3 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net). 4 * 5 * moved into proper i2c interface; 6 * Brad Parker (brad@heeltoe.com) 7 * 8 * Parts from dbox2_i2c.c (cvs.tuxbox.org) 9 * (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net) 10 * 11 * (C) 2007 Montavista Software, Inc. 12 * Vitaly Bordug <vitb@kernel.crashing.org> 13 * 14 * Converted to of_platform_device. Renamed to i2c-cpm.c. 15 * (C) 2007,2008 Jochen Friedrich <jochen@scram.de> 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License as published by 19 * the Free Software Foundation; either version 2 of the License, or 20 * (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/delay.h> 31#include <linux/slab.h> 32#include <linux/interrupt.h> 33#include <linux/errno.h> 34#include <linux/stddef.h> 35#include <linux/i2c.h> 36#include <linux/io.h> 37#include <linux/dma-mapping.h> 38#include <linux/of_address.h> 39#include <linux/of_device.h> 40#include <linux/of_irq.h> 41#include <linux/of_platform.h> 42#include <sysdev/fsl_soc.h> 43#include <asm/cpm.h> 44 45/* Try to define this if you have an older CPU (earlier than rev D4) */ 46/* However, better use a GPIO based bitbang driver in this case :/ */ 47#undef I2C_CHIP_ERRATA 48 49#define CPM_MAX_READ 513 50#define CPM_MAXBD 4 51 52#define I2C_EB (0x10) /* Big endian mode */ 53#define I2C_EB_CPM2 (0x30) /* Big endian mode, memory snoop */ 54 55#define DPRAM_BASE ((u8 __iomem __force *)cpm_muram_addr(0)) 56 57/* I2C parameter RAM. */ 58struct i2c_ram { 59 ushort rbase; /* Rx Buffer descriptor base address */ 60 ushort tbase; /* Tx Buffer descriptor base address */ 61 u_char rfcr; /* Rx function code */ 62 u_char tfcr; /* Tx function code */ 63 ushort mrblr; /* Max receive buffer length */ 64 uint rstate; /* Internal */ 65 uint rdp; /* Internal */ 66 ushort rbptr; /* Rx Buffer descriptor pointer */ 67 ushort rbc; /* Internal */ 68 uint rxtmp; /* Internal */ 69 uint tstate; /* Internal */ 70 uint tdp; /* Internal */ 71 ushort tbptr; /* Tx Buffer descriptor pointer */ 72 ushort tbc; /* Internal */ 73 uint txtmp; /* Internal */ 74 char res1[4]; /* Reserved */ 75 ushort rpbase; /* Relocation pointer */ 76 char res2[2]; /* Reserved */ 77}; 78 79#define I2COM_START 0x80 80#define I2COM_MASTER 0x01 81#define I2CER_TXE 0x10 82#define I2CER_BUSY 0x04 83#define I2CER_TXB 0x02 84#define I2CER_RXB 0x01 85#define I2MOD_EN 0x01 86 87/* I2C Registers */ 88struct i2c_reg { 89 u8 i2mod; 90 u8 res1[3]; 91 u8 i2add; 92 u8 res2[3]; 93 u8 i2brg; 94 u8 res3[3]; 95 u8 i2com; 96 u8 res4[3]; 97 u8 i2cer; 98 u8 res5[3]; 99 u8 i2cmr; 100}; 101 102struct cpm_i2c { 103 char *base; 104 struct platform_device *ofdev; 105 struct i2c_adapter adap; 106 uint dp_addr; 107 int version; /* CPM1=1, CPM2=2 */ 108 int irq; 109 int cp_command; 110 int freq; 111 struct i2c_reg __iomem *i2c_reg; 112 struct i2c_ram __iomem *i2c_ram; 113 u16 i2c_addr; 114 wait_queue_head_t i2c_wait; 115 cbd_t __iomem *tbase; 116 cbd_t __iomem *rbase; 117 u_char *txbuf[CPM_MAXBD]; 118 u_char *rxbuf[CPM_MAXBD]; 119 u32 txdma[CPM_MAXBD]; 120 u32 rxdma[CPM_MAXBD]; 121}; 122 123static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id) 124{ 125 struct cpm_i2c *cpm; 126 struct i2c_reg __iomem *i2c_reg; 127 struct i2c_adapter *adap = dev_id; 128 int i; 129 130 cpm = i2c_get_adapdata(dev_id); 131 i2c_reg = cpm->i2c_reg; 132 133 /* Clear interrupt. */ 134 i = in_8(&i2c_reg->i2cer); 135 out_8(&i2c_reg->i2cer, i); 136 137 dev_dbg(&adap->dev, "Interrupt: %x\n", i); 138 139 wake_up(&cpm->i2c_wait); 140 141 return i ? IRQ_HANDLED : IRQ_NONE; 142} 143 144static void cpm_reset_i2c_params(struct cpm_i2c *cpm) 145{ 146 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram; 147 148 /* Set up the I2C parameters in the parameter ram. */ 149 out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE); 150 out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE); 151 152 if (cpm->version == 1) { 153 out_8(&i2c_ram->tfcr, I2C_EB); 154 out_8(&i2c_ram->rfcr, I2C_EB); 155 } else { 156 out_8(&i2c_ram->tfcr, I2C_EB_CPM2); 157 out_8(&i2c_ram->rfcr, I2C_EB_CPM2); 158 } 159 160 out_be16(&i2c_ram->mrblr, CPM_MAX_READ); 161 162 out_be32(&i2c_ram->rstate, 0); 163 out_be32(&i2c_ram->rdp, 0); 164 out_be16(&i2c_ram->rbptr, 0); 165 out_be16(&i2c_ram->rbc, 0); 166 out_be32(&i2c_ram->rxtmp, 0); 167 out_be32(&i2c_ram->tstate, 0); 168 out_be32(&i2c_ram->tdp, 0); 169 out_be16(&i2c_ram->tbptr, 0); 170 out_be16(&i2c_ram->tbc, 0); 171 out_be32(&i2c_ram->txtmp, 0); 172} 173 174static void cpm_i2c_force_close(struct i2c_adapter *adap) 175{ 176 struct cpm_i2c *cpm = i2c_get_adapdata(adap); 177 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg; 178 179 dev_dbg(&adap->dev, "cpm_i2c_force_close()\n"); 180 181 cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD); 182 183 out_8(&i2c_reg->i2cmr, 0x00); /* Disable all interrupts */ 184 out_8(&i2c_reg->i2cer, 0xff); 185} 186 187static void cpm_i2c_parse_message(struct i2c_adapter *adap, 188 struct i2c_msg *pmsg, int num, int tx, int rx) 189{ 190 cbd_t __iomem *tbdf; 191 cbd_t __iomem *rbdf; 192 u_char addr; 193 u_char *tb; 194 u_char *rb; 195 struct cpm_i2c *cpm = i2c_get_adapdata(adap); 196 197 tbdf = cpm->tbase + tx; 198 rbdf = cpm->rbase + rx; 199 200 addr = pmsg->addr << 1; 201 if (pmsg->flags & I2C_M_RD) 202 addr |= 1; 203 204 tb = cpm->txbuf[tx]; 205 rb = cpm->rxbuf[rx]; 206 207 /* Align read buffer */ 208 rb = (u_char *) (((ulong) rb + 1) & ~1); 209 210 tb[0] = addr; /* Device address byte w/rw flag */ 211 212 out_be16(&tbdf->cbd_datlen, pmsg->len + 1); 213 out_be16(&tbdf->cbd_sc, 0); 214 215 if (!(pmsg->flags & I2C_M_NOSTART)) 216 setbits16(&tbdf->cbd_sc, BD_I2C_START); 217 218 if (tx + 1 == num) 219 setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP); 220 221 if (pmsg->flags & I2C_M_RD) { 222 /* 223 * To read, we need an empty buffer of the proper length. 224 * All that is used is the first byte for address, the remainder 225 * is just used for timing (and doesn't really have to exist). 226 */ 227 228 dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr); 229 230 out_be16(&rbdf->cbd_datlen, 0); 231 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); 232 233 if (rx + 1 == CPM_MAXBD) 234 setbits16(&rbdf->cbd_sc, BD_SC_WRAP); 235 236 eieio(); 237 setbits16(&tbdf->cbd_sc, BD_SC_READY); 238 } else { 239 dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr); 240 241 memcpy(tb+1, pmsg->buf, pmsg->len); 242 243 eieio(); 244 setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT); 245 } 246} 247 248static int cpm_i2c_check_message(struct i2c_adapter *adap, 249 struct i2c_msg *pmsg, int tx, int rx) 250{ 251 cbd_t __iomem *tbdf; 252 cbd_t __iomem *rbdf; 253 u_char *tb; 254 u_char *rb; 255 struct cpm_i2c *cpm = i2c_get_adapdata(adap); 256 257 tbdf = cpm->tbase + tx; 258 rbdf = cpm->rbase + rx; 259 260 tb = cpm->txbuf[tx]; 261 rb = cpm->rxbuf[rx]; 262 263 /* Align read buffer */ 264 rb = (u_char *) (((uint) rb + 1) & ~1); 265 266 eieio(); 267 if (pmsg->flags & I2C_M_RD) { 268 dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n", 269 in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc)); 270 271 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) { 272 dev_dbg(&adap->dev, "I2C read; No ack\n"); 273 return -ENXIO; 274 } 275 if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) { 276 dev_err(&adap->dev, 277 "I2C read; complete but rbuf empty\n"); 278 return -EREMOTEIO; 279 } 280 if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) { 281 dev_err(&adap->dev, "I2C read; Overrun\n"); 282 return -EREMOTEIO; 283 } 284 memcpy(pmsg->buf, rb, pmsg->len); 285 } else { 286 dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx, 287 in_be16(&tbdf->cbd_sc)); 288 289 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) { 290 dev_dbg(&adap->dev, "I2C write; No ack\n"); 291 return -ENXIO; 292 } 293 if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) { 294 dev_err(&adap->dev, "I2C write; Underrun\n"); 295 return -EIO; 296 } 297 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) { 298 dev_err(&adap->dev, "I2C write; Collision\n"); 299 return -EIO; 300 } 301 } 302 return 0; 303} 304 305static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 306{ 307 struct cpm_i2c *cpm = i2c_get_adapdata(adap); 308 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg; 309 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram; 310 struct i2c_msg *pmsg; 311 int ret; 312 int tptr; 313 int rptr; 314 cbd_t __iomem *tbdf; 315 cbd_t __iomem *rbdf; 316 317 /* Reset to use first buffer */ 318 out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase)); 319 out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase)); 320 321 tbdf = cpm->tbase; 322 rbdf = cpm->rbase; 323 324 tptr = 0; 325 rptr = 0; 326 327 /* 328 * If there was a collision in the last i2c transaction, 329 * Set I2COM_MASTER as it was cleared during collision. 330 */ 331 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) { 332 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); 333 } 334 335 while (tptr < num) { 336 pmsg = &msgs[tptr]; 337 dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr); 338 339 cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr); 340 if (pmsg->flags & I2C_M_RD) 341 rptr++; 342 tptr++; 343 } 344 /* Start transfer now */ 345 /* Enable RX/TX/Error interupts */ 346 out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB); 347 out_8(&i2c_reg->i2cer, 0xff); /* Clear interrupt status */ 348 /* Chip bug, set enable here */ 349 setbits8(&i2c_reg->i2mod, I2MOD_EN); /* Enable */ 350 /* Begin transmission */ 351 setbits8(&i2c_reg->i2com, I2COM_START); 352 353 tptr = 0; 354 rptr = 0; 355 356 while (tptr < num) { 357 /* Check for outstanding messages */ 358 dev_dbg(&adap->dev, "test ready.\n"); 359 pmsg = &msgs[tptr]; 360 if (pmsg->flags & I2C_M_RD) 361 ret = wait_event_timeout(cpm->i2c_wait, 362 (in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) || 363 !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY), 364 1 * HZ); 365 else 366 ret = wait_event_timeout(cpm->i2c_wait, 367 !(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY), 368 1 * HZ); 369 if (ret == 0) { 370 ret = -EREMOTEIO; 371 dev_err(&adap->dev, "I2C transfer: timeout\n"); 372 goto out_err; 373 } 374 if (ret > 0) { 375 dev_dbg(&adap->dev, "ready.\n"); 376 ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr); 377 tptr++; 378 if (pmsg->flags & I2C_M_RD) 379 rptr++; 380 if (ret) 381 goto out_err; 382 } 383 } 384#ifdef I2C_CHIP_ERRATA 385 /* 386 * Chip errata, clear enable. This is not needed on rev D4 CPUs. 387 * Disabling I2C too early may cause too short stop condition 388 */ 389 udelay(4); 390 clrbits8(&i2c_reg->i2mod, I2MOD_EN); 391#endif 392 return (num); 393 394out_err: 395 cpm_i2c_force_close(adap); 396#ifdef I2C_CHIP_ERRATA 397 /* 398 * Chip errata, clear enable. This is not needed on rev D4 CPUs. 399 */ 400 clrbits8(&i2c_reg->i2mod, I2MOD_EN); 401#endif 402 return ret; 403} 404 405static u32 cpm_i2c_func(struct i2c_adapter *adap) 406{ 407 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 408} 409 410/* -----exported algorithm data: ------------------------------------- */ 411 412static const struct i2c_algorithm cpm_i2c_algo = { 413 .master_xfer = cpm_i2c_xfer, 414 .functionality = cpm_i2c_func, 415}; 416 417/* CPM_MAX_READ is also limiting writes according to the code! */ 418static struct i2c_adapter_quirks cpm_i2c_quirks = { 419 .max_num_msgs = CPM_MAXBD, 420 .max_read_len = CPM_MAX_READ, 421 .max_write_len = CPM_MAX_READ, 422}; 423 424static const struct i2c_adapter cpm_ops = { 425 .owner = THIS_MODULE, 426 .name = "i2c-cpm", 427 .algo = &cpm_i2c_algo, 428 .quirks = &cpm_i2c_quirks, 429}; 430 431static int cpm_i2c_setup(struct cpm_i2c *cpm) 432{ 433 struct platform_device *ofdev = cpm->ofdev; 434 const u32 *data; 435 int len, ret, i; 436 void __iomem *i2c_base; 437 cbd_t __iomem *tbdf; 438 cbd_t __iomem *rbdf; 439 unsigned char brg; 440 441 dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n"); 442 443 init_waitqueue_head(&cpm->i2c_wait); 444 445 cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 446 if (!cpm->irq) 447 return -EINVAL; 448 449 /* Install interrupt handler. */ 450 ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c", 451 &cpm->adap); 452 if (ret) 453 return ret; 454 455 /* I2C parameter RAM */ 456 i2c_base = of_iomap(ofdev->dev.of_node, 1); 457 if (i2c_base == NULL) { 458 ret = -EINVAL; 459 goto out_irq; 460 } 461 462 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) { 463 464 /* Check for and use a microcode relocation patch. */ 465 cpm->i2c_ram = i2c_base; 466 cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase); 467 468 /* 469 * Maybe should use cpm_muram_alloc instead of hardcoding 470 * this in micropatch.c 471 */ 472 if (cpm->i2c_addr) { 473 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr); 474 iounmap(i2c_base); 475 } 476 477 cpm->version = 1; 478 479 } else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) { 480 cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64); 481 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr); 482 out_be16(i2c_base, cpm->i2c_addr); 483 iounmap(i2c_base); 484 485 cpm->version = 2; 486 487 } else { 488 iounmap(i2c_base); 489 ret = -EINVAL; 490 goto out_irq; 491 } 492 493 /* I2C control/status registers */ 494 cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0); 495 if (cpm->i2c_reg == NULL) { 496 ret = -EINVAL; 497 goto out_ram; 498 } 499 500 data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len); 501 if (!data || len != 4) { 502 ret = -EINVAL; 503 goto out_reg; 504 } 505 cpm->cp_command = *data; 506 507 data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len); 508 if (data && len == 4) 509 cpm->adap.class = *data; 510 511 data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len); 512 if (data && len == 4) 513 cpm->freq = *data; 514 else 515 cpm->freq = 60000; /* use 60kHz i2c clock by default */ 516 517 /* 518 * Allocate space for CPM_MAXBD transmit and receive buffer 519 * descriptors in the DP ram. 520 */ 521 cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8); 522 if (!cpm->dp_addr) { 523 ret = -ENOMEM; 524 goto out_reg; 525 } 526 527 cpm->tbase = cpm_muram_addr(cpm->dp_addr); 528 cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD); 529 530 /* Allocate TX and RX buffers */ 531 532 tbdf = cpm->tbase; 533 rbdf = cpm->rbase; 534 535 for (i = 0; i < CPM_MAXBD; i++) { 536 cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev, 537 CPM_MAX_READ + 1, 538 &cpm->rxdma[i], GFP_KERNEL); 539 if (!cpm->rxbuf[i]) { 540 ret = -ENOMEM; 541 goto out_muram; 542 } 543 out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1)); 544 545 cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL); 546 if (!cpm->txbuf[i]) { 547 ret = -ENOMEM; 548 goto out_muram; 549 } 550 out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]); 551 } 552 553 /* Initialize Tx/Rx parameters. */ 554 555 cpm_reset_i2c_params(cpm); 556 557 dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n", 558 cpm->i2c_ram, cpm->i2c_addr, cpm->freq); 559 dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n", 560 (u8 __iomem *)cpm->tbase - DPRAM_BASE, 561 (u8 __iomem *)cpm->rbase - DPRAM_BASE); 562 563 cpm_command(cpm->cp_command, CPM_CR_INIT_TRX); 564 565 /* 566 * Select an invalid address. Just make sure we don't use loopback mode 567 */ 568 out_8(&cpm->i2c_reg->i2add, 0x7f << 1); 569 570 /* 571 * PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the 572 * i2c baud rate generator. This is divided by 2 x (DIV + 3) to get 573 * the actual i2c bus frequency. 574 */ 575 brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3; 576 out_8(&cpm->i2c_reg->i2brg, brg); 577 578 out_8(&cpm->i2c_reg->i2mod, 0x00); 579 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); /* Master mode */ 580 581 /* Disable interrupts. */ 582 out_8(&cpm->i2c_reg->i2cmr, 0); 583 out_8(&cpm->i2c_reg->i2cer, 0xff); 584 585 return 0; 586 587out_muram: 588 for (i = 0; i < CPM_MAXBD; i++) { 589 if (cpm->rxbuf[i]) 590 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, 591 cpm->rxbuf[i], cpm->rxdma[i]); 592 if (cpm->txbuf[i]) 593 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, 594 cpm->txbuf[i], cpm->txdma[i]); 595 } 596 cpm_muram_free(cpm->dp_addr); 597out_reg: 598 iounmap(cpm->i2c_reg); 599out_ram: 600 if ((cpm->version == 1) && (!cpm->i2c_addr)) 601 iounmap(cpm->i2c_ram); 602 if (cpm->version == 2) 603 cpm_muram_free(cpm->i2c_addr); 604out_irq: 605 free_irq(cpm->irq, &cpm->adap); 606 return ret; 607} 608 609static void cpm_i2c_shutdown(struct cpm_i2c *cpm) 610{ 611 int i; 612 613 /* Shut down I2C. */ 614 clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN); 615 616 /* Disable interrupts */ 617 out_8(&cpm->i2c_reg->i2cmr, 0); 618 out_8(&cpm->i2c_reg->i2cer, 0xff); 619 620 free_irq(cpm->irq, &cpm->adap); 621 622 /* Free all memory */ 623 for (i = 0; i < CPM_MAXBD; i++) { 624 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, 625 cpm->rxbuf[i], cpm->rxdma[i]); 626 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, 627 cpm->txbuf[i], cpm->txdma[i]); 628 } 629 630 cpm_muram_free(cpm->dp_addr); 631 iounmap(cpm->i2c_reg); 632 633 if ((cpm->version == 1) && (!cpm->i2c_addr)) 634 iounmap(cpm->i2c_ram); 635 if (cpm->version == 2) 636 cpm_muram_free(cpm->i2c_addr); 637} 638 639static int cpm_i2c_probe(struct platform_device *ofdev) 640{ 641 int result, len; 642 struct cpm_i2c *cpm; 643 const u32 *data; 644 645 cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL); 646 if (!cpm) 647 return -ENOMEM; 648 649 cpm->ofdev = ofdev; 650 651 platform_set_drvdata(ofdev, cpm); 652 653 cpm->adap = cpm_ops; 654 i2c_set_adapdata(&cpm->adap, cpm); 655 cpm->adap.dev.parent = &ofdev->dev; 656 cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node); 657 658 result = cpm_i2c_setup(cpm); 659 if (result) { 660 dev_err(&ofdev->dev, "Unable to init hardware\n"); 661 goto out_free; 662 } 663 664 /* register new adapter to i2c module... */ 665 666 data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len); 667 cpm->adap.nr = (data && len == 4) ? be32_to_cpup(data) : -1; 668 result = i2c_add_numbered_adapter(&cpm->adap); 669 670 if (result < 0) { 671 dev_err(&ofdev->dev, "Unable to register with I2C\n"); 672 goto out_shut; 673 } 674 675 dev_dbg(&ofdev->dev, "hw routines for %s registered.\n", 676 cpm->adap.name); 677 678 return 0; 679out_shut: 680 cpm_i2c_shutdown(cpm); 681out_free: 682 kfree(cpm); 683 684 return result; 685} 686 687static int cpm_i2c_remove(struct platform_device *ofdev) 688{ 689 struct cpm_i2c *cpm = platform_get_drvdata(ofdev); 690 691 i2c_del_adapter(&cpm->adap); 692 693 cpm_i2c_shutdown(cpm); 694 695 kfree(cpm); 696 697 return 0; 698} 699 700static const struct of_device_id cpm_i2c_match[] = { 701 { 702 .compatible = "fsl,cpm1-i2c", 703 }, 704 { 705 .compatible = "fsl,cpm2-i2c", 706 }, 707 {}, 708}; 709 710MODULE_DEVICE_TABLE(of, cpm_i2c_match); 711 712static struct platform_driver cpm_i2c_driver = { 713 .probe = cpm_i2c_probe, 714 .remove = cpm_i2c_remove, 715 .driver = { 716 .name = "fsl-i2c-cpm", 717 .of_match_table = cpm_i2c_match, 718 }, 719}; 720 721module_platform_driver(cpm_i2c_driver); 722 723MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>"); 724MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards"); 725MODULE_LICENSE("GPL"); 726