1/*
2 * Socket CAN driver for Aeroflex Gaisler GRCAN and GRHCAN.
3 *
4 * 2012 (c) Aeroflex Gaisler AB
5 *
6 * This driver supports GRCAN and GRHCAN CAN controllers available in the GRLIB
7 * VHDL IP core library.
8 *
9 * Full documentation of the GRCAN core can be found here:
10 * http://www.gaisler.com/products/grlib/grip.pdf
11 *
12 * See "Documentation/devicetree/bindings/net/can/grcan.txt" for information on
13 * open firmware properties.
14 *
15 * See "Documentation/ABI/testing/sysfs-class-net-grcan" for information on the
16 * sysfs interface.
17 *
18 * See "Documentation/kernel-parameters.txt" for information on the module
19 * parameters.
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2 of the License, or (at your
24 * option) any later version.
25 *
26 * Contributors: Andreas Larsson <andreas@gaisler.com>
27 */
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/interrupt.h>
32#include <linux/netdevice.h>
33#include <linux/delay.h>
34#include <linux/io.h>
35#include <linux/can/dev.h>
36#include <linux/spinlock.h>
37#include <linux/of_platform.h>
38#include <linux/of_irq.h>
39
40#include <linux/dma-mapping.h>
41
42#define DRV_NAME	"grcan"
43
44#define GRCAN_NAPI_WEIGHT	32
45
46#define GRCAN_RESERVE_SIZE(slot1, slot2) (((slot2) - (slot1)) / 4 - 1)
47
48struct grcan_registers {
49	u32 conf;	/* 0x00 */
50	u32 stat;	/* 0x04 */
51	u32 ctrl;	/* 0x08 */
52	u32 __reserved1[GRCAN_RESERVE_SIZE(0x08, 0x18)];
53	u32 smask;	/* 0x18 - CanMASK */
54	u32 scode;	/* 0x1c - CanCODE */
55	u32 __reserved2[GRCAN_RESERVE_SIZE(0x1c, 0x100)];
56	u32 pimsr;	/* 0x100 */
57	u32 pimr;	/* 0x104 */
58	u32 pisr;	/* 0x108 */
59	u32 pir;	/* 0x10C */
60	u32 imr;	/* 0x110 */
61	u32 picr;	/* 0x114 */
62	u32 __reserved3[GRCAN_RESERVE_SIZE(0x114, 0x200)];
63	u32 txctrl;	/* 0x200 */
64	u32 txaddr;	/* 0x204 */
65	u32 txsize;	/* 0x208 */
66	u32 txwr;	/* 0x20C */
67	u32 txrd;	/* 0x210 */
68	u32 txirq;	/* 0x214 */
69	u32 __reserved4[GRCAN_RESERVE_SIZE(0x214, 0x300)];
70	u32 rxctrl;	/* 0x300 */
71	u32 rxaddr;	/* 0x304 */
72	u32 rxsize;	/* 0x308 */
73	u32 rxwr;	/* 0x30C */
74	u32 rxrd;	/* 0x310 */
75	u32 rxirq;	/* 0x314 */
76	u32 rxmask;	/* 0x318 */
77	u32 rxcode;	/* 0x31C */
78};
79
80#define GRCAN_CONF_ABORT	0x00000001
81#define GRCAN_CONF_ENABLE0	0x00000002
82#define GRCAN_CONF_ENABLE1	0x00000004
83#define GRCAN_CONF_SELECT	0x00000008
84#define GRCAN_CONF_SILENT	0x00000010
85#define GRCAN_CONF_SAM		0x00000020 /* Available in some hardware */
86#define GRCAN_CONF_BPR		0x00000300 /* Note: not BRP */
87#define GRCAN_CONF_RSJ		0x00007000
88#define GRCAN_CONF_PS1		0x00f00000
89#define GRCAN_CONF_PS2		0x000f0000
90#define GRCAN_CONF_SCALER	0xff000000
91#define GRCAN_CONF_OPERATION						\
92	(GRCAN_CONF_ABORT | GRCAN_CONF_ENABLE0 | GRCAN_CONF_ENABLE1	\
93	 | GRCAN_CONF_SELECT | GRCAN_CONF_SILENT | GRCAN_CONF_SAM)
94#define GRCAN_CONF_TIMING						\
95	(GRCAN_CONF_BPR | GRCAN_CONF_RSJ | GRCAN_CONF_PS1		\
96	 | GRCAN_CONF_PS2 | GRCAN_CONF_SCALER)
97
98#define GRCAN_CONF_RSJ_MIN	1
99#define GRCAN_CONF_RSJ_MAX	4
100#define GRCAN_CONF_PS1_MIN	1
101#define GRCAN_CONF_PS1_MAX	15
102#define GRCAN_CONF_PS2_MIN	2
103#define GRCAN_CONF_PS2_MAX	8
104#define GRCAN_CONF_SCALER_MIN	0
105#define GRCAN_CONF_SCALER_MAX	255
106#define GRCAN_CONF_SCALER_INC	1
107
108#define GRCAN_CONF_BPR_BIT	8
109#define GRCAN_CONF_RSJ_BIT	12
110#define GRCAN_CONF_PS1_BIT	20
111#define GRCAN_CONF_PS2_BIT	16
112#define GRCAN_CONF_SCALER_BIT	24
113
114#define GRCAN_STAT_PASS		0x000001
115#define GRCAN_STAT_OFF		0x000002
116#define GRCAN_STAT_OR		0x000004
117#define GRCAN_STAT_AHBERR	0x000008
118#define GRCAN_STAT_ACTIVE	0x000010
119#define GRCAN_STAT_RXERRCNT	0x00ff00
120#define GRCAN_STAT_TXERRCNT	0xff0000
121
122#define GRCAN_STAT_ERRCTR_RELATED	(GRCAN_STAT_PASS | GRCAN_STAT_OFF)
123
124#define GRCAN_STAT_RXERRCNT_BIT	8
125#define GRCAN_STAT_TXERRCNT_BIT	16
126
127#define GRCAN_STAT_ERRCNT_WARNING_LIMIT	96
128#define GRCAN_STAT_ERRCNT_PASSIVE_LIMIT	127
129
130#define GRCAN_CTRL_RESET	0x2
131#define GRCAN_CTRL_ENABLE	0x1
132
133#define GRCAN_TXCTRL_ENABLE	0x1
134#define GRCAN_TXCTRL_ONGOING	0x2
135#define GRCAN_TXCTRL_SINGLE	0x4
136
137#define GRCAN_RXCTRL_ENABLE	0x1
138#define GRCAN_RXCTRL_ONGOING	0x2
139
140/* Relative offset of IRQ sources to AMBA Plug&Play */
141#define GRCAN_IRQIX_IRQ		0
142#define GRCAN_IRQIX_TXSYNC	1
143#define GRCAN_IRQIX_RXSYNC	2
144
145#define GRCAN_IRQ_PASS		0x00001
146#define GRCAN_IRQ_OFF		0x00002
147#define GRCAN_IRQ_OR		0x00004
148#define GRCAN_IRQ_RXAHBERR	0x00008
149#define GRCAN_IRQ_TXAHBERR	0x00010
150#define GRCAN_IRQ_RXIRQ		0x00020
151#define GRCAN_IRQ_TXIRQ		0x00040
152#define GRCAN_IRQ_RXFULL	0x00080
153#define GRCAN_IRQ_TXEMPTY	0x00100
154#define GRCAN_IRQ_RX		0x00200
155#define GRCAN_IRQ_TX		0x00400
156#define GRCAN_IRQ_RXSYNC	0x00800
157#define GRCAN_IRQ_TXSYNC	0x01000
158#define GRCAN_IRQ_RXERRCTR	0x02000
159#define GRCAN_IRQ_TXERRCTR	0x04000
160#define GRCAN_IRQ_RXMISS	0x08000
161#define GRCAN_IRQ_TXLOSS	0x10000
162
163#define GRCAN_IRQ_NONE	0
164#define GRCAN_IRQ_ALL							\
165	(GRCAN_IRQ_PASS | GRCAN_IRQ_OFF | GRCAN_IRQ_OR			\
166	 | GRCAN_IRQ_RXAHBERR | GRCAN_IRQ_TXAHBERR			\
167	 | GRCAN_IRQ_RXIRQ | GRCAN_IRQ_TXIRQ				\
168	 | GRCAN_IRQ_RXFULL | GRCAN_IRQ_TXEMPTY				\
169	 | GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_RXSYNC		\
170	 | GRCAN_IRQ_TXSYNC | GRCAN_IRQ_RXERRCTR			\
171	 | GRCAN_IRQ_TXERRCTR | GRCAN_IRQ_RXMISS			\
172	 | GRCAN_IRQ_TXLOSS)
173
174#define GRCAN_IRQ_ERRCTR_RELATED (GRCAN_IRQ_RXERRCTR | GRCAN_IRQ_TXERRCTR \
175				  | GRCAN_IRQ_PASS | GRCAN_IRQ_OFF)
176#define GRCAN_IRQ_ERRORS (GRCAN_IRQ_ERRCTR_RELATED | GRCAN_IRQ_OR	\
177			  | GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR	\
178			  | GRCAN_IRQ_TXLOSS)
179#define GRCAN_IRQ_DEFAULT (GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_ERRORS)
180
181#define GRCAN_MSG_SIZE		16
182
183#define GRCAN_MSG_IDE		0x80000000
184#define GRCAN_MSG_RTR		0x40000000
185#define GRCAN_MSG_BID		0x1ffc0000
186#define GRCAN_MSG_EID		0x1fffffff
187#define GRCAN_MSG_IDE_BIT	31
188#define GRCAN_MSG_RTR_BIT	30
189#define GRCAN_MSG_BID_BIT	18
190#define GRCAN_MSG_EID_BIT	0
191
192#define GRCAN_MSG_DLC		0xf0000000
193#define GRCAN_MSG_TXERRC	0x00ff0000
194#define GRCAN_MSG_RXERRC	0x0000ff00
195#define GRCAN_MSG_DLC_BIT	28
196#define GRCAN_MSG_TXERRC_BIT	16
197#define GRCAN_MSG_RXERRC_BIT	8
198#define GRCAN_MSG_AHBERR	0x00000008
199#define GRCAN_MSG_OR		0x00000004
200#define GRCAN_MSG_OFF		0x00000002
201#define GRCAN_MSG_PASS		0x00000001
202
203#define GRCAN_MSG_DATA_SLOT_INDEX(i) (2 + (i) / 4)
204#define GRCAN_MSG_DATA_SHIFT(i) ((3 - (i) % 4) * 8)
205
206#define GRCAN_BUFFER_ALIGNMENT		1024
207#define GRCAN_DEFAULT_BUFFER_SIZE	1024
208#define GRCAN_VALID_TR_SIZE_MASK	0x001fffc0
209
210#define GRCAN_INVALID_BUFFER_SIZE(s)			\
211	((s) == 0 || ((s) & ~GRCAN_VALID_TR_SIZE_MASK))
212
213#if GRCAN_INVALID_BUFFER_SIZE(GRCAN_DEFAULT_BUFFER_SIZE)
214#error "Invalid default buffer size"
215#endif
216
217struct grcan_dma_buffer {
218	size_t size;
219	void *buf;
220	dma_addr_t handle;
221};
222
223struct grcan_dma {
224	size_t base_size;
225	void *base_buf;
226	dma_addr_t base_handle;
227	struct grcan_dma_buffer tx;
228	struct grcan_dma_buffer rx;
229};
230
231/* GRCAN configuration parameters */
232struct grcan_device_config {
233	unsigned short enable0;
234	unsigned short enable1;
235	unsigned short select;
236	unsigned int txsize;
237	unsigned int rxsize;
238};
239
240#define GRCAN_DEFAULT_DEVICE_CONFIG {				\
241		.enable0	= 0,				\
242		.enable1	= 0,				\
243		.select		= 0,				\
244		.txsize		= GRCAN_DEFAULT_BUFFER_SIZE,	\
245		.rxsize		= GRCAN_DEFAULT_BUFFER_SIZE,	\
246		}
247
248#define GRCAN_TXBUG_SAFE_GRLIB_VERSION	0x4100
249#define GRLIB_VERSION_MASK		0xffff
250
251/* GRCAN private data structure */
252struct grcan_priv {
253	struct can_priv can;	/* must be the first member */
254	struct net_device *dev;
255	struct napi_struct napi;
256
257	struct grcan_registers __iomem *regs;	/* ioremap'ed registers */
258	struct grcan_device_config config;
259	struct grcan_dma dma;
260
261	struct sk_buff **echo_skb;	/* We allocate this on our own */
262	u8 *txdlc;			/* Length of queued frames */
263
264	/* The echo skb pointer, pointing into echo_skb and indicating which
265	 * frames can be echoed back. See the "Notes on the tx cyclic buffer
266	 * handling"-comment for grcan_start_xmit for more details.
267	 */
268	u32 eskbp;
269
270	/* Lock for controlling changes to the netif tx queue state, accesses to
271	 * the echo_skb pointer eskbp and for making sure that a running reset
272	 * and/or a close of the interface is done without interference from
273	 * other parts of the code.
274	 *
275	 * The echo_skb pointer, eskbp, should only be accessed under this lock
276	 * as it can be changed in several places and together with decisions on
277	 * whether to wake up the tx queue.
278	 *
279	 * The tx queue must never be woken up if there is a running reset or
280	 * close in progress.
281	 *
282	 * A running reset (see below on need_txbug_workaround) should never be
283	 * done if the interface is closing down and several running resets
284	 * should never be scheduled simultaneously.
285	 */
286	spinlock_t lock;
287
288	/* Whether a workaround is needed due to a bug in older hardware. In
289	 * this case, the driver both tries to prevent the bug from being
290	 * triggered and recovers, if the bug nevertheless happens, by doing a
291	 * running reset. A running reset, resets the device and continues from
292	 * where it were without being noticeable from outside the driver (apart
293	 * from slight delays).
294	 */
295	bool need_txbug_workaround;
296
297	/* To trigger initization of running reset and to trigger running reset
298	 * respectively in the case of a hanged device due to a txbug.
299	 */
300	struct timer_list hang_timer;
301	struct timer_list rr_timer;
302
303	/* To avoid waking up the netif queue and restarting timers
304	 * when a reset is scheduled or when closing of the device is
305	 * undergoing
306	 */
307	bool resetting;
308	bool closing;
309};
310
311/* Wait time for a short wait for ongoing to clear */
312#define GRCAN_SHORTWAIT_USECS	10
313
314/* Limit on the number of transmitted bits of an eff frame according to the CAN
315 * specification: 1 bit start of frame, 32 bits arbitration field, 6 bits
316 * control field, 8 bytes data field, 16 bits crc field, 2 bits ACK field and 7
317 * bits end of frame
318 */
319#define GRCAN_EFF_FRAME_MAX_BITS	(1+32+6+8*8+16+2+7)
320
321#if defined(__BIG_ENDIAN)
322static inline u32 grcan_read_reg(u32 __iomem *reg)
323{
324	return ioread32be(reg);
325}
326
327static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
328{
329	iowrite32be(val, reg);
330}
331#else
332static inline u32 grcan_read_reg(u32 __iomem *reg)
333{
334	return ioread32(reg);
335}
336
337static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
338{
339	iowrite32(val, reg);
340}
341#endif
342
343static inline void grcan_clear_bits(u32 __iomem *reg, u32 mask)
344{
345	grcan_write_reg(reg, grcan_read_reg(reg) & ~mask);
346}
347
348static inline void grcan_set_bits(u32 __iomem *reg, u32 mask)
349{
350	grcan_write_reg(reg, grcan_read_reg(reg) | mask);
351}
352
353static inline u32 grcan_read_bits(u32 __iomem *reg, u32 mask)
354{
355	return grcan_read_reg(reg) & mask;
356}
357
358static inline void grcan_write_bits(u32 __iomem *reg, u32 value, u32 mask)
359{
360	u32 old = grcan_read_reg(reg);
361
362	grcan_write_reg(reg, (old & ~mask) | (value & mask));
363}
364
365/* a and b should both be in [0,size] and a == b == size should not hold */
366static inline u32 grcan_ring_add(u32 a, u32 b, u32 size)
367{
368	u32 sum = a + b;
369
370	if (sum < size)
371		return sum;
372	else
373		return sum - size;
374}
375
376/* a and b should both be in [0,size) */
377static inline u32 grcan_ring_sub(u32 a, u32 b, u32 size)
378{
379	return grcan_ring_add(a, size - b, size);
380}
381
382/* Available slots for new transmissions */
383static inline u32 grcan_txspace(size_t txsize, u32 txwr, u32 eskbp)
384{
385	u32 slots = txsize / GRCAN_MSG_SIZE - 1;
386	u32 used = grcan_ring_sub(txwr, eskbp, txsize) / GRCAN_MSG_SIZE;
387
388	return slots - used;
389}
390
391/* Configuration parameters that can be set via module parameters */
392static struct grcan_device_config grcan_module_config =
393	GRCAN_DEFAULT_DEVICE_CONFIG;
394
395static const struct can_bittiming_const grcan_bittiming_const = {
396	.name		= DRV_NAME,
397	.tseg1_min	= GRCAN_CONF_PS1_MIN + 1,
398	.tseg1_max	= GRCAN_CONF_PS1_MAX + 1,
399	.tseg2_min	= GRCAN_CONF_PS2_MIN,
400	.tseg2_max	= GRCAN_CONF_PS2_MAX,
401	.sjw_max	= GRCAN_CONF_RSJ_MAX,
402	.brp_min	= GRCAN_CONF_SCALER_MIN + 1,
403	.brp_max	= GRCAN_CONF_SCALER_MAX + 1,
404	.brp_inc	= GRCAN_CONF_SCALER_INC,
405};
406
407static int grcan_set_bittiming(struct net_device *dev)
408{
409	struct grcan_priv *priv = netdev_priv(dev);
410	struct grcan_registers __iomem *regs = priv->regs;
411	struct can_bittiming *bt = &priv->can.bittiming;
412	u32 timing = 0;
413	int bpr, rsj, ps1, ps2, scaler;
414
415	/* Should never happen - function will not be called when
416	 * device is up
417	 */
418	if (grcan_read_bits(&regs->ctrl, GRCAN_CTRL_ENABLE))
419		return -EBUSY;
420
421	bpr = 0; /* Note bpr and brp are different concepts */
422	rsj = bt->sjw;
423	ps1 = (bt->prop_seg + bt->phase_seg1) - 1; /* tseg1 - 1 */
424	ps2 = bt->phase_seg2;
425	scaler = (bt->brp - 1);
426	netdev_dbg(dev, "Request for BPR=%d, RSJ=%d, PS1=%d, PS2=%d, SCALER=%d",
427		   bpr, rsj, ps1, ps2, scaler);
428	if (!(ps1 > ps2)) {
429		netdev_err(dev, "PS1 > PS2 must hold: PS1=%d, PS2=%d\n",
430			   ps1, ps2);
431		return -EINVAL;
432	}
433	if (!(ps2 >= rsj)) {
434		netdev_err(dev, "PS2 >= RSJ must hold: PS2=%d, RSJ=%d\n",
435			   ps2, rsj);
436		return -EINVAL;
437	}
438
439	timing |= (bpr << GRCAN_CONF_BPR_BIT) & GRCAN_CONF_BPR;
440	timing |= (rsj << GRCAN_CONF_RSJ_BIT) & GRCAN_CONF_RSJ;
441	timing |= (ps1 << GRCAN_CONF_PS1_BIT) & GRCAN_CONF_PS1;
442	timing |= (ps2 << GRCAN_CONF_PS2_BIT) & GRCAN_CONF_PS2;
443	timing |= (scaler << GRCAN_CONF_SCALER_BIT) & GRCAN_CONF_SCALER;
444	netdev_info(dev, "setting timing=0x%x\n", timing);
445	grcan_write_bits(&regs->conf, timing, GRCAN_CONF_TIMING);
446
447	return 0;
448}
449
450static int grcan_get_berr_counter(const struct net_device *dev,
451				  struct can_berr_counter *bec)
452{
453	struct grcan_priv *priv = netdev_priv(dev);
454	struct grcan_registers __iomem *regs = priv->regs;
455	u32 status = grcan_read_reg(&regs->stat);
456
457	bec->txerr = (status & GRCAN_STAT_TXERRCNT) >> GRCAN_STAT_TXERRCNT_BIT;
458	bec->rxerr = (status & GRCAN_STAT_RXERRCNT) >> GRCAN_STAT_RXERRCNT_BIT;
459	return 0;
460}
461
462static int grcan_poll(struct napi_struct *napi, int budget);
463
464/* Reset device, but keep configuration information */
465static void grcan_reset(struct net_device *dev)
466{
467	struct grcan_priv *priv = netdev_priv(dev);
468	struct grcan_registers __iomem *regs = priv->regs;
469	u32 config = grcan_read_reg(&regs->conf);
470
471	grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
472	grcan_write_reg(&regs->conf, config);
473
474	priv->eskbp = grcan_read_reg(&regs->txrd);
475	priv->can.state = CAN_STATE_STOPPED;
476
477	/* Turn off hardware filtering - regs->rxcode set to 0 by reset */
478	grcan_write_reg(&regs->rxmask, 0);
479}
480
481/* stop device without changing any configurations */
482static void grcan_stop_hardware(struct net_device *dev)
483{
484	struct grcan_priv *priv = netdev_priv(dev);
485	struct grcan_registers __iomem *regs = priv->regs;
486
487	grcan_write_reg(&regs->imr, GRCAN_IRQ_NONE);
488	grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
489	grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
490	grcan_clear_bits(&regs->ctrl, GRCAN_CTRL_ENABLE);
491}
492
493/* Let priv->eskbp catch up to regs->txrd and echo back the skbs if echo
494 * is true and free them otherwise.
495 *
496 * If budget is >= 0, stop after handling at most budget skbs. Otherwise,
497 * continue until priv->eskbp catches up to regs->txrd.
498 *
499 * priv->lock *must* be held when calling this function
500 */
501static int catch_up_echo_skb(struct net_device *dev, int budget, bool echo)
502{
503	struct grcan_priv *priv = netdev_priv(dev);
504	struct grcan_registers __iomem *regs = priv->regs;
505	struct grcan_dma *dma = &priv->dma;
506	struct net_device_stats *stats = &dev->stats;
507	int i, work_done;
508
509	/* Updates to priv->eskbp and wake-ups of the queue needs to
510	 * be atomic towards the reads of priv->eskbp and shut-downs
511	 * of the queue in grcan_start_xmit.
512	 */
513	u32 txrd = grcan_read_reg(&regs->txrd);
514
515	for (work_done = 0; work_done < budget || budget < 0; work_done++) {
516		if (priv->eskbp == txrd)
517			break;
518		i = priv->eskbp / GRCAN_MSG_SIZE;
519		if (echo) {
520			/* Normal echo of messages */
521			stats->tx_packets++;
522			stats->tx_bytes += priv->txdlc[i];
523			priv->txdlc[i] = 0;
524			can_get_echo_skb(dev, i);
525		} else {
526			/* For cleanup of untransmitted messages */
527			can_free_echo_skb(dev, i);
528		}
529
530		priv->eskbp = grcan_ring_add(priv->eskbp, GRCAN_MSG_SIZE,
531					     dma->tx.size);
532		txrd = grcan_read_reg(&regs->txrd);
533	}
534	return work_done;
535}
536
537static void grcan_lost_one_shot_frame(struct net_device *dev)
538{
539	struct grcan_priv *priv = netdev_priv(dev);
540	struct grcan_registers __iomem *regs = priv->regs;
541	struct grcan_dma *dma = &priv->dma;
542	u32 txrd;
543	unsigned long flags;
544
545	spin_lock_irqsave(&priv->lock, flags);
546
547	catch_up_echo_skb(dev, -1, true);
548
549	if (unlikely(grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE))) {
550		/* Should never happen */
551		netdev_err(dev, "TXCTRL enabled at TXLOSS in one shot mode\n");
552	} else {
553		/* By the time an GRCAN_IRQ_TXLOSS is generated in
554		 * one-shot mode there is no problem in writing
555		 * to TXRD even in versions of the hardware in
556		 * which GRCAN_TXCTRL_ONGOING is not cleared properly
557		 * in one-shot mode.
558		 */
559
560		/* Skip message and discard echo-skb */
561		txrd = grcan_read_reg(&regs->txrd);
562		txrd = grcan_ring_add(txrd, GRCAN_MSG_SIZE, dma->tx.size);
563		grcan_write_reg(&regs->txrd, txrd);
564		catch_up_echo_skb(dev, -1, false);
565
566		if (!priv->resetting && !priv->closing &&
567		    !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) {
568			netif_wake_queue(dev);
569			grcan_set_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
570		}
571	}
572
573	spin_unlock_irqrestore(&priv->lock, flags);
574}
575
576static void grcan_err(struct net_device *dev, u32 sources, u32 status)
577{
578	struct grcan_priv *priv = netdev_priv(dev);
579	struct grcan_registers __iomem *regs = priv->regs;
580	struct grcan_dma *dma = &priv->dma;
581	struct net_device_stats *stats = &dev->stats;
582	struct can_frame cf;
583
584	/* Zero potential error_frame */
585	memset(&cf, 0, sizeof(cf));
586
587	/* Message lost interrupt. This might be due to arbitration error, but
588	 * is also triggered when there is no one else on the can bus or when
589	 * there is a problem with the hardware interface or the bus itself. As
590	 * arbitration errors can not be singled out, no error frames are
591	 * generated reporting this event as an arbitration error.
592	 */
593	if (sources & GRCAN_IRQ_TXLOSS) {
594		/* Take care of failed one-shot transmit */
595		if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
596			grcan_lost_one_shot_frame(dev);
597
598		/* Stop printing as soon as error passive or bus off is in
599		 * effect to limit the amount of txloss debug printouts.
600		 */
601		if (!(status & GRCAN_STAT_ERRCTR_RELATED)) {
602			netdev_dbg(dev, "tx message lost\n");
603			stats->tx_errors++;
604		}
605	}
606
607	/* Conditions dealing with the error counters. There is no interrupt for
608	 * error warning, but there are interrupts for increases of the error
609	 * counters.
610	 */
611	if ((sources & GRCAN_IRQ_ERRCTR_RELATED) ||
612	    (status & GRCAN_STAT_ERRCTR_RELATED)) {
613		enum can_state state = priv->can.state;
614		enum can_state oldstate = state;
615		u32 txerr = (status & GRCAN_STAT_TXERRCNT)
616			>> GRCAN_STAT_TXERRCNT_BIT;
617		u32 rxerr = (status & GRCAN_STAT_RXERRCNT)
618			>> GRCAN_STAT_RXERRCNT_BIT;
619
620		/* Figure out current state */
621		if (status & GRCAN_STAT_OFF) {
622			state = CAN_STATE_BUS_OFF;
623		} else if (status & GRCAN_STAT_PASS) {
624			state = CAN_STATE_ERROR_PASSIVE;
625		} else if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT ||
626			   rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT) {
627			state = CAN_STATE_ERROR_WARNING;
628		} else {
629			state = CAN_STATE_ERROR_ACTIVE;
630		}
631
632		/* Handle and report state changes */
633		if (state != oldstate) {
634			switch (state) {
635			case CAN_STATE_BUS_OFF:
636				netdev_dbg(dev, "bus-off\n");
637				netif_carrier_off(dev);
638				priv->can.can_stats.bus_off++;
639
640				/* Prevent the hardware from recovering from bus
641				 * off on its own if restart is disabled.
642				 */
643				if (!priv->can.restart_ms)
644					grcan_stop_hardware(dev);
645
646				cf.can_id |= CAN_ERR_BUSOFF;
647				break;
648
649			case CAN_STATE_ERROR_PASSIVE:
650				netdev_dbg(dev, "Error passive condition\n");
651				priv->can.can_stats.error_passive++;
652
653				cf.can_id |= CAN_ERR_CRTL;
654				if (txerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
655					cf.data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
656				if (rxerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
657					cf.data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
658				break;
659
660			case CAN_STATE_ERROR_WARNING:
661				netdev_dbg(dev, "Error warning condition\n");
662				priv->can.can_stats.error_warning++;
663
664				cf.can_id |= CAN_ERR_CRTL;
665				if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
666					cf.data[1] |= CAN_ERR_CRTL_TX_WARNING;
667				if (rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
668					cf.data[1] |= CAN_ERR_CRTL_RX_WARNING;
669				break;
670
671			case CAN_STATE_ERROR_ACTIVE:
672				netdev_dbg(dev, "Error active condition\n");
673				cf.can_id |= CAN_ERR_CRTL;
674				break;
675
676			default:
677				/* There are no others at this point */
678				break;
679			}
680			cf.data[6] = txerr;
681			cf.data[7] = rxerr;
682			priv->can.state = state;
683		}
684
685		/* Report automatic restarts */
686		if (priv->can.restart_ms && oldstate == CAN_STATE_BUS_OFF) {
687			unsigned long flags;
688
689			cf.can_id |= CAN_ERR_RESTARTED;
690			netdev_dbg(dev, "restarted\n");
691			priv->can.can_stats.restarts++;
692			netif_carrier_on(dev);
693
694			spin_lock_irqsave(&priv->lock, flags);
695
696			if (!priv->resetting && !priv->closing) {
697				u32 txwr = grcan_read_reg(&regs->txwr);
698
699				if (grcan_txspace(dma->tx.size, txwr,
700						  priv->eskbp))
701					netif_wake_queue(dev);
702			}
703
704			spin_unlock_irqrestore(&priv->lock, flags);
705		}
706	}
707
708	/* Data overrun interrupt */
709	if ((sources & GRCAN_IRQ_OR) || (status & GRCAN_STAT_OR)) {
710		netdev_dbg(dev, "got data overrun interrupt\n");
711		stats->rx_over_errors++;
712		stats->rx_errors++;
713
714		cf.can_id |= CAN_ERR_CRTL;
715		cf.data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
716	}
717
718	/* AHB bus error interrupts (not CAN bus errors) - shut down the
719	 * device.
720	 */
721	if (sources & (GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR) ||
722	    (status & GRCAN_STAT_AHBERR)) {
723		char *txrx = "";
724		unsigned long flags;
725
726		if (sources & GRCAN_IRQ_TXAHBERR) {
727			txrx = "on tx ";
728			stats->tx_errors++;
729		} else if (sources & GRCAN_IRQ_RXAHBERR) {
730			txrx = "on rx ";
731			stats->rx_errors++;
732		}
733		netdev_err(dev, "Fatal AHB buss error %s- halting device\n",
734			   txrx);
735
736		spin_lock_irqsave(&priv->lock, flags);
737
738		/* Prevent anything to be enabled again and halt device */
739		priv->closing = true;
740		netif_stop_queue(dev);
741		grcan_stop_hardware(dev);
742		priv->can.state = CAN_STATE_STOPPED;
743
744		spin_unlock_irqrestore(&priv->lock, flags);
745	}
746
747	/* Pass on error frame if something to report,
748	 * i.e. id contains some information
749	 */
750	if (cf.can_id) {
751		struct can_frame *skb_cf;
752		struct sk_buff *skb = alloc_can_err_skb(dev, &skb_cf);
753
754		if (skb == NULL) {
755			netdev_dbg(dev, "could not allocate error frame\n");
756			return;
757		}
758		skb_cf->can_id |= cf.can_id;
759		memcpy(skb_cf->data, cf.data, sizeof(cf.data));
760
761		netif_rx(skb);
762	}
763}
764
765static irqreturn_t grcan_interrupt(int irq, void *dev_id)
766{
767	struct net_device *dev = dev_id;
768	struct grcan_priv *priv = netdev_priv(dev);
769	struct grcan_registers __iomem *regs = priv->regs;
770	u32 sources, status;
771
772	/* Find out the source */
773	sources = grcan_read_reg(&regs->pimsr);
774	if (!sources)
775		return IRQ_NONE;
776	grcan_write_reg(&regs->picr, sources);
777	status = grcan_read_reg(&regs->stat);
778
779	/* If we got TX progress, the device has not hanged,
780	 * so disable the hang timer
781	 */
782	if (priv->need_txbug_workaround &&
783	    (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_TXLOSS))) {
784		del_timer(&priv->hang_timer);
785	}
786
787	/* Frame(s) received or transmitted */
788	if (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_RX)) {
789		/* Disable tx/rx interrupts and schedule poll(). No need for
790		 * locking as interference from a running reset at worst leads
791		 * to an extra interrupt.
792		 */
793		grcan_clear_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
794		napi_schedule(&priv->napi);
795	}
796
797	/* (Potential) error conditions to take care of */
798	if (sources & GRCAN_IRQ_ERRORS)
799		grcan_err(dev, sources, status);
800
801	return IRQ_HANDLED;
802}
803
804/* Reset device and restart operations from where they were.
805 *
806 * This assumes that RXCTRL & RXCTRL is properly disabled and that RX
807 * is not ONGOING (TX might be stuck in ONGOING due to a harwrware bug
808 * for single shot)
809 */
810static void grcan_running_reset(unsigned long data)
811{
812	struct net_device *dev = (struct net_device *)data;
813	struct grcan_priv *priv = netdev_priv(dev);
814	struct grcan_registers __iomem *regs = priv->regs;
815	unsigned long flags;
816
817	/* This temporarily messes with eskbp, so we need to lock
818	 * priv->lock
819	 */
820	spin_lock_irqsave(&priv->lock, flags);
821
822	priv->resetting = false;
823	del_timer(&priv->hang_timer);
824	del_timer(&priv->rr_timer);
825
826	if (!priv->closing) {
827		/* Save and reset - config register preserved by grcan_reset */
828		u32 imr = grcan_read_reg(&regs->imr);
829
830		u32 txaddr = grcan_read_reg(&regs->txaddr);
831		u32 txsize = grcan_read_reg(&regs->txsize);
832		u32 txwr = grcan_read_reg(&regs->txwr);
833		u32 txrd = grcan_read_reg(&regs->txrd);
834		u32 eskbp = priv->eskbp;
835
836		u32 rxaddr = grcan_read_reg(&regs->rxaddr);
837		u32 rxsize = grcan_read_reg(&regs->rxsize);
838		u32 rxwr = grcan_read_reg(&regs->rxwr);
839		u32 rxrd = grcan_read_reg(&regs->rxrd);
840
841		grcan_reset(dev);
842
843		/* Restore */
844		grcan_write_reg(&regs->txaddr, txaddr);
845		grcan_write_reg(&regs->txsize, txsize);
846		grcan_write_reg(&regs->txwr, txwr);
847		grcan_write_reg(&regs->txrd, txrd);
848		priv->eskbp = eskbp;
849
850		grcan_write_reg(&regs->rxaddr, rxaddr);
851		grcan_write_reg(&regs->rxsize, rxsize);
852		grcan_write_reg(&regs->rxwr, rxwr);
853		grcan_write_reg(&regs->rxrd, rxrd);
854
855		/* Turn on device again */
856		grcan_write_reg(&regs->imr, imr);
857		priv->can.state = CAN_STATE_ERROR_ACTIVE;
858		grcan_write_reg(&regs->txctrl, GRCAN_TXCTRL_ENABLE
859				| (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
860				   ? GRCAN_TXCTRL_SINGLE : 0));
861		grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
862		grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
863
864		/* Start queue if there is size and listen-onle mode is not
865		 * enabled
866		 */
867		if (grcan_txspace(priv->dma.tx.size, txwr, priv->eskbp) &&
868		    !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
869			netif_wake_queue(dev);
870	}
871
872	spin_unlock_irqrestore(&priv->lock, flags);
873
874	netdev_err(dev, "Device reset and restored\n");
875}
876
877/* Waiting time in usecs corresponding to the transmission of three maximum
878 * sized can frames in the given bitrate (in bits/sec). Waiting for this amount
879 * of time makes sure that the can controller have time to finish sending or
880 * receiving a frame with a good margin.
881 *
882 * usecs/sec * number of frames * bits/frame / bits/sec
883 */
884static inline u32 grcan_ongoing_wait_usecs(__u32 bitrate)
885{
886	return 1000000 * 3 * GRCAN_EFF_FRAME_MAX_BITS / bitrate;
887}
888
889/* Set timer so that it will not fire until after a period in which the can
890 * controller have a good margin to finish transmitting a frame unless it has
891 * hanged
892 */
893static inline void grcan_reset_timer(struct timer_list *timer, __u32 bitrate)
894{
895	u32 wait_jiffies = usecs_to_jiffies(grcan_ongoing_wait_usecs(bitrate));
896
897	mod_timer(timer, jiffies + wait_jiffies);
898}
899
900/* Disable channels and schedule a running reset */
901static void grcan_initiate_running_reset(unsigned long data)
902{
903	struct net_device *dev = (struct net_device *)data;
904	struct grcan_priv *priv = netdev_priv(dev);
905	struct grcan_registers __iomem *regs = priv->regs;
906	unsigned long flags;
907
908	netdev_err(dev, "Device seems hanged - reset scheduled\n");
909
910	spin_lock_irqsave(&priv->lock, flags);
911
912	/* The main body of this function must never be executed again
913	 * until after an execution of grcan_running_reset
914	 */
915	if (!priv->resetting && !priv->closing) {
916		priv->resetting = true;
917		netif_stop_queue(dev);
918		grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
919		grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
920		grcan_reset_timer(&priv->rr_timer, priv->can.bittiming.bitrate);
921	}
922
923	spin_unlock_irqrestore(&priv->lock, flags);
924}
925
926static void grcan_free_dma_buffers(struct net_device *dev)
927{
928	struct grcan_priv *priv = netdev_priv(dev);
929	struct grcan_dma *dma = &priv->dma;
930
931	dma_free_coherent(&dev->dev, dma->base_size, dma->base_buf,
932			  dma->base_handle);
933	memset(dma, 0, sizeof(*dma));
934}
935
936static int grcan_allocate_dma_buffers(struct net_device *dev,
937				      size_t tsize, size_t rsize)
938{
939	struct grcan_priv *priv = netdev_priv(dev);
940	struct grcan_dma *dma = &priv->dma;
941	struct grcan_dma_buffer *large = rsize > tsize ? &dma->rx : &dma->tx;
942	struct grcan_dma_buffer *small = rsize > tsize ? &dma->tx : &dma->rx;
943	size_t shift;
944
945	/* Need a whole number of GRCAN_BUFFER_ALIGNMENT for the large,
946	 * i.e. first buffer
947	 */
948	size_t maxs = max(tsize, rsize);
949	size_t lsize = ALIGN(maxs, GRCAN_BUFFER_ALIGNMENT);
950
951	/* Put the small buffer after that */
952	size_t ssize = min(tsize, rsize);
953
954	/* Extra GRCAN_BUFFER_ALIGNMENT to allow for alignment */
955	dma->base_size = lsize + ssize + GRCAN_BUFFER_ALIGNMENT;
956	dma->base_buf = dma_alloc_coherent(&dev->dev,
957					   dma->base_size,
958					   &dma->base_handle,
959					   GFP_KERNEL);
960
961	if (!dma->base_buf)
962		return -ENOMEM;
963
964	dma->tx.size = tsize;
965	dma->rx.size = rsize;
966
967	large->handle = ALIGN(dma->base_handle, GRCAN_BUFFER_ALIGNMENT);
968	small->handle = large->handle + lsize;
969	shift = large->handle - dma->base_handle;
970
971	large->buf = dma->base_buf + shift;
972	small->buf = large->buf + lsize;
973
974	return 0;
975}
976
977/* priv->lock *must* be held when calling this function */
978static int grcan_start(struct net_device *dev)
979{
980	struct grcan_priv *priv = netdev_priv(dev);
981	struct grcan_registers __iomem *regs = priv->regs;
982	u32 confop, txctrl;
983
984	grcan_reset(dev);
985
986	grcan_write_reg(&regs->txaddr, priv->dma.tx.handle);
987	grcan_write_reg(&regs->txsize, priv->dma.tx.size);
988	/* regs->txwr, regs->txrd and priv->eskbp already set to 0 by reset */
989
990	grcan_write_reg(&regs->rxaddr, priv->dma.rx.handle);
991	grcan_write_reg(&regs->rxsize, priv->dma.rx.size);
992	/* regs->rxwr and regs->rxrd already set to 0 by reset */
993
994	/* Enable interrupts */
995	grcan_read_reg(&regs->pir);
996	grcan_write_reg(&regs->imr, GRCAN_IRQ_DEFAULT);
997
998	/* Enable interfaces, channels and device */
999	confop = GRCAN_CONF_ABORT
1000		| (priv->config.enable0 ? GRCAN_CONF_ENABLE0 : 0)
1001		| (priv->config.enable1 ? GRCAN_CONF_ENABLE1 : 0)
1002		| (priv->config.select ? GRCAN_CONF_SELECT : 0)
1003		| (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY ?
1004		   GRCAN_CONF_SILENT : 0)
1005		| (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
1006		   GRCAN_CONF_SAM : 0);
1007	grcan_write_bits(&regs->conf, confop, GRCAN_CONF_OPERATION);
1008	txctrl = GRCAN_TXCTRL_ENABLE
1009		| (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
1010		   ? GRCAN_TXCTRL_SINGLE : 0);
1011	grcan_write_reg(&regs->txctrl, txctrl);
1012	grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
1013	grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
1014
1015	priv->can.state = CAN_STATE_ERROR_ACTIVE;
1016
1017	return 0;
1018}
1019
1020static int grcan_set_mode(struct net_device *dev, enum can_mode mode)
1021{
1022	struct grcan_priv *priv = netdev_priv(dev);
1023	unsigned long flags;
1024	int err = 0;
1025
1026	if (mode == CAN_MODE_START) {
1027		/* This might be called to restart the device to recover from
1028		 * bus off errors
1029		 */
1030		spin_lock_irqsave(&priv->lock, flags);
1031		if (priv->closing || priv->resetting) {
1032			err = -EBUSY;
1033		} else {
1034			netdev_info(dev, "Restarting device\n");
1035			grcan_start(dev);
1036			if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1037				netif_wake_queue(dev);
1038		}
1039		spin_unlock_irqrestore(&priv->lock, flags);
1040		return err;
1041	}
1042	return -EOPNOTSUPP;
1043}
1044
1045static int grcan_open(struct net_device *dev)
1046{
1047	struct grcan_priv *priv = netdev_priv(dev);
1048	struct grcan_dma *dma = &priv->dma;
1049	unsigned long flags;
1050	int err;
1051
1052	/* Allocate memory */
1053	err = grcan_allocate_dma_buffers(dev, priv->config.txsize,
1054					 priv->config.rxsize);
1055	if (err) {
1056		netdev_err(dev, "could not allocate DMA buffers\n");
1057		return err;
1058	}
1059
1060	priv->echo_skb = kzalloc(dma->tx.size * sizeof(*priv->echo_skb),
1061				 GFP_KERNEL);
1062	if (!priv->echo_skb) {
1063		err = -ENOMEM;
1064		goto exit_free_dma_buffers;
1065	}
1066	priv->can.echo_skb_max = dma->tx.size;
1067	priv->can.echo_skb = priv->echo_skb;
1068
1069	priv->txdlc = kzalloc(dma->tx.size * sizeof(*priv->txdlc), GFP_KERNEL);
1070	if (!priv->txdlc) {
1071		err = -ENOMEM;
1072		goto exit_free_echo_skb;
1073	}
1074
1075	/* Get can device up */
1076	err = open_candev(dev);
1077	if (err)
1078		goto exit_free_txdlc;
1079
1080	err = request_irq(dev->irq, grcan_interrupt, IRQF_SHARED,
1081			  dev->name, dev);
1082	if (err)
1083		goto exit_close_candev;
1084
1085	spin_lock_irqsave(&priv->lock, flags);
1086
1087	napi_enable(&priv->napi);
1088	grcan_start(dev);
1089	if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1090		netif_start_queue(dev);
1091	priv->resetting = false;
1092	priv->closing = false;
1093
1094	spin_unlock_irqrestore(&priv->lock, flags);
1095
1096	return 0;
1097
1098exit_close_candev:
1099	close_candev(dev);
1100exit_free_txdlc:
1101	kfree(priv->txdlc);
1102exit_free_echo_skb:
1103	kfree(priv->echo_skb);
1104exit_free_dma_buffers:
1105	grcan_free_dma_buffers(dev);
1106	return err;
1107}
1108
1109static int grcan_close(struct net_device *dev)
1110{
1111	struct grcan_priv *priv = netdev_priv(dev);
1112	unsigned long flags;
1113
1114	napi_disable(&priv->napi);
1115
1116	spin_lock_irqsave(&priv->lock, flags);
1117
1118	priv->closing = true;
1119	if (priv->need_txbug_workaround) {
1120		del_timer_sync(&priv->hang_timer);
1121		del_timer_sync(&priv->rr_timer);
1122	}
1123	netif_stop_queue(dev);
1124	grcan_stop_hardware(dev);
1125	priv->can.state = CAN_STATE_STOPPED;
1126
1127	spin_unlock_irqrestore(&priv->lock, flags);
1128
1129	free_irq(dev->irq, dev);
1130	close_candev(dev);
1131
1132	grcan_free_dma_buffers(dev);
1133	priv->can.echo_skb_max = 0;
1134	priv->can.echo_skb = NULL;
1135	kfree(priv->echo_skb);
1136	kfree(priv->txdlc);
1137
1138	return 0;
1139}
1140
1141static int grcan_transmit_catch_up(struct net_device *dev, int budget)
1142{
1143	struct grcan_priv *priv = netdev_priv(dev);
1144	unsigned long flags;
1145	int work_done;
1146
1147	spin_lock_irqsave(&priv->lock, flags);
1148
1149	work_done = catch_up_echo_skb(dev, budget, true);
1150	if (work_done) {
1151		if (!priv->resetting && !priv->closing &&
1152		    !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1153			netif_wake_queue(dev);
1154
1155		/* With napi we don't get TX interrupts for a while,
1156		 * so prevent a running reset while catching up
1157		 */
1158		if (priv->need_txbug_workaround)
1159			del_timer(&priv->hang_timer);
1160	}
1161
1162	spin_unlock_irqrestore(&priv->lock, flags);
1163
1164	return work_done;
1165}
1166
1167static int grcan_receive(struct net_device *dev, int budget)
1168{
1169	struct grcan_priv *priv = netdev_priv(dev);
1170	struct grcan_registers __iomem *regs = priv->regs;
1171	struct grcan_dma *dma = &priv->dma;
1172	struct net_device_stats *stats = &dev->stats;
1173	struct can_frame *cf;
1174	struct sk_buff *skb;
1175	u32 wr, rd, startrd;
1176	u32 *slot;
1177	u32 i, rtr, eff, j, shift;
1178	int work_done = 0;
1179
1180	rd = grcan_read_reg(&regs->rxrd);
1181	startrd = rd;
1182	for (work_done = 0; work_done < budget; work_done++) {
1183		/* Check for packet to receive */
1184		wr = grcan_read_reg(&regs->rxwr);
1185		if (rd == wr)
1186			break;
1187
1188		/* Take care of packet */
1189		skb = alloc_can_skb(dev, &cf);
1190		if (skb == NULL) {
1191			netdev_err(dev,
1192				   "dropping frame: skb allocation failed\n");
1193			stats->rx_dropped++;
1194			continue;
1195		}
1196
1197		slot = dma->rx.buf + rd;
1198		eff = slot[0] & GRCAN_MSG_IDE;
1199		rtr = slot[0] & GRCAN_MSG_RTR;
1200		if (eff) {
1201			cf->can_id = ((slot[0] & GRCAN_MSG_EID)
1202				      >> GRCAN_MSG_EID_BIT);
1203			cf->can_id |= CAN_EFF_FLAG;
1204		} else {
1205			cf->can_id = ((slot[0] & GRCAN_MSG_BID)
1206				      >> GRCAN_MSG_BID_BIT);
1207		}
1208		cf->can_dlc = get_can_dlc((slot[1] & GRCAN_MSG_DLC)
1209					  >> GRCAN_MSG_DLC_BIT);
1210		if (rtr) {
1211			cf->can_id |= CAN_RTR_FLAG;
1212		} else {
1213			for (i = 0; i < cf->can_dlc; i++) {
1214				j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1215				shift = GRCAN_MSG_DATA_SHIFT(i);
1216				cf->data[i] = (u8)(slot[j] >> shift);
1217			}
1218		}
1219		netif_receive_skb(skb);
1220
1221		/* Update statistics and read pointer */
1222		stats->rx_packets++;
1223		stats->rx_bytes += cf->can_dlc;
1224		rd = grcan_ring_add(rd, GRCAN_MSG_SIZE, dma->rx.size);
1225	}
1226
1227	/* Make sure everything is read before allowing hardware to
1228	 * use the memory
1229	 */
1230	mb();
1231
1232	/* Update read pointer - no need to check for ongoing */
1233	if (likely(rd != startrd))
1234		grcan_write_reg(&regs->rxrd, rd);
1235
1236	return work_done;
1237}
1238
1239static int grcan_poll(struct napi_struct *napi, int budget)
1240{
1241	struct grcan_priv *priv = container_of(napi, struct grcan_priv, napi);
1242	struct net_device *dev = priv->dev;
1243	struct grcan_registers __iomem *regs = priv->regs;
1244	unsigned long flags;
1245	int tx_work_done, rx_work_done;
1246	int rx_budget = budget / 2;
1247	int tx_budget = budget - rx_budget;
1248
1249	/* Half of the budget for receiveing messages */
1250	rx_work_done = grcan_receive(dev, rx_budget);
1251
1252	/* Half of the budget for transmitting messages as that can trigger echo
1253	 * frames being received
1254	 */
1255	tx_work_done = grcan_transmit_catch_up(dev, tx_budget);
1256
1257	if (rx_work_done < rx_budget && tx_work_done < tx_budget) {
1258		napi_complete(napi);
1259
1260		/* Guarantee no interference with a running reset that otherwise
1261		 * could turn off interrupts.
1262		 */
1263		spin_lock_irqsave(&priv->lock, flags);
1264
1265		/* Enable tx and rx interrupts again. No need to check
1266		 * priv->closing as napi_disable in grcan_close is waiting for
1267		 * scheduled napi calls to finish.
1268		 */
1269		grcan_set_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
1270
1271		spin_unlock_irqrestore(&priv->lock, flags);
1272	}
1273
1274	return rx_work_done + tx_work_done;
1275}
1276
1277/* Work tx bug by waiting while for the risky situation to clear. If that fails,
1278 * drop a frame in one-shot mode or indicate a busy device otherwise.
1279 *
1280 * Returns 0 on successful wait. Otherwise it sets *netdev_tx_status to the
1281 * value that should be returned by grcan_start_xmit when aborting the xmit.
1282 */
1283static int grcan_txbug_workaround(struct net_device *dev, struct sk_buff *skb,
1284				  u32 txwr, u32 oneshotmode,
1285				  netdev_tx_t *netdev_tx_status)
1286{
1287	struct grcan_priv *priv = netdev_priv(dev);
1288	struct grcan_registers __iomem *regs = priv->regs;
1289	struct grcan_dma *dma = &priv->dma;
1290	int i;
1291	unsigned long flags;
1292
1293	/* Wait a while for ongoing to be cleared or read pointer to catch up to
1294	 * write pointer. The latter is needed due to a bug in older versions of
1295	 * GRCAN in which ONGOING is not cleared properly one-shot mode when a
1296	 * transmission fails.
1297	 */
1298	for (i = 0; i < GRCAN_SHORTWAIT_USECS; i++) {
1299		udelay(1);
1300		if (!grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ONGOING) ||
1301		    grcan_read_reg(&regs->txrd) == txwr) {
1302			return 0;
1303		}
1304	}
1305
1306	/* Clean up, in case the situation was not resolved */
1307	spin_lock_irqsave(&priv->lock, flags);
1308	if (!priv->resetting && !priv->closing) {
1309		/* Queue might have been stopped earlier in grcan_start_xmit */
1310		if (grcan_txspace(dma->tx.size, txwr, priv->eskbp))
1311			netif_wake_queue(dev);
1312		/* Set a timer to resolve a hanged tx controller */
1313		if (!timer_pending(&priv->hang_timer))
1314			grcan_reset_timer(&priv->hang_timer,
1315					  priv->can.bittiming.bitrate);
1316	}
1317	spin_unlock_irqrestore(&priv->lock, flags);
1318
1319	if (oneshotmode) {
1320		/* In one-shot mode we should never end up here because
1321		 * then the interrupt handler increases txrd on TXLOSS,
1322		 * but it is consistent with one-shot mode to drop the
1323		 * frame in this case.
1324		 */
1325		kfree_skb(skb);
1326		*netdev_tx_status = NETDEV_TX_OK;
1327	} else {
1328		/* In normal mode the socket-can transmission queue get
1329		 * to keep the frame so that it can be retransmitted
1330		 * later
1331		 */
1332		*netdev_tx_status = NETDEV_TX_BUSY;
1333	}
1334	return -EBUSY;
1335}
1336
1337/* Notes on the tx cyclic buffer handling:
1338 *
1339 * regs->txwr	- the next slot for the driver to put data to be sent
1340 * regs->txrd	- the next slot for the device to read data
1341 * priv->eskbp	- the next slot for the driver to call can_put_echo_skb for
1342 *
1343 * grcan_start_xmit can enter more messages as long as regs->txwr does
1344 * not reach priv->eskbp (within 1 message gap)
1345 *
1346 * The device sends messages until regs->txrd reaches regs->txwr
1347 *
1348 * The interrupt calls handler calls can_put_echo_skb until
1349 * priv->eskbp reaches regs->txrd
1350 */
1351static netdev_tx_t grcan_start_xmit(struct sk_buff *skb,
1352				    struct net_device *dev)
1353{
1354	struct grcan_priv *priv = netdev_priv(dev);
1355	struct grcan_registers __iomem *regs = priv->regs;
1356	struct grcan_dma *dma = &priv->dma;
1357	struct can_frame *cf = (struct can_frame *)skb->data;
1358	u32 id, txwr, txrd, space, txctrl;
1359	int slotindex;
1360	u32 *slot;
1361	u32 i, rtr, eff, dlc, tmp, err;
1362	int j, shift;
1363	unsigned long flags;
1364	u32 oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT;
1365
1366	if (can_dropped_invalid_skb(dev, skb))
1367		return NETDEV_TX_OK;
1368
1369	/* Trying to transmit in silent mode will generate error interrupts, but
1370	 * this should never happen - the queue should not have been started.
1371	 */
1372	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1373		return NETDEV_TX_BUSY;
1374
1375	/* Reads of priv->eskbp and shut-downs of the queue needs to
1376	 * be atomic towards the updates to priv->eskbp and wake-ups
1377	 * of the queue in the interrupt handler.
1378	 */
1379	spin_lock_irqsave(&priv->lock, flags);
1380
1381	txwr = grcan_read_reg(&regs->txwr);
1382	space = grcan_txspace(dma->tx.size, txwr, priv->eskbp);
1383
1384	slotindex = txwr / GRCAN_MSG_SIZE;
1385	slot = dma->tx.buf + txwr;
1386
1387	if (unlikely(space == 1))
1388		netif_stop_queue(dev);
1389
1390	spin_unlock_irqrestore(&priv->lock, flags);
1391	/* End of critical section*/
1392
1393	/* This should never happen. If circular buffer is full, the
1394	 * netif_stop_queue should have been stopped already.
1395	 */
1396	if (unlikely(!space)) {
1397		netdev_err(dev, "No buffer space, but queue is non-stopped.\n");
1398		return NETDEV_TX_BUSY;
1399	}
1400
1401	/* Convert and write CAN message to DMA buffer */
1402	eff = cf->can_id & CAN_EFF_FLAG;
1403	rtr = cf->can_id & CAN_RTR_FLAG;
1404	id = cf->can_id & (eff ? CAN_EFF_MASK : CAN_SFF_MASK);
1405	dlc = cf->can_dlc;
1406	if (eff)
1407		tmp = (id << GRCAN_MSG_EID_BIT) & GRCAN_MSG_EID;
1408	else
1409		tmp = (id << GRCAN_MSG_BID_BIT) & GRCAN_MSG_BID;
1410	slot[0] = (eff ? GRCAN_MSG_IDE : 0) | (rtr ? GRCAN_MSG_RTR : 0) | tmp;
1411
1412	slot[1] = ((dlc << GRCAN_MSG_DLC_BIT) & GRCAN_MSG_DLC);
1413	slot[2] = 0;
1414	slot[3] = 0;
1415	for (i = 0; i < dlc; i++) {
1416		j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1417		shift = GRCAN_MSG_DATA_SHIFT(i);
1418		slot[j] |= cf->data[i] << shift;
1419	}
1420
1421	/* Checking that channel has not been disabled. These cases
1422	 * should never happen
1423	 */
1424	txctrl = grcan_read_reg(&regs->txctrl);
1425	if (!(txctrl & GRCAN_TXCTRL_ENABLE))
1426		netdev_err(dev, "tx channel spuriously disabled\n");
1427
1428	if (oneshotmode && !(txctrl & GRCAN_TXCTRL_SINGLE))
1429		netdev_err(dev, "one-shot mode spuriously disabled\n");
1430
1431	/* Bug workaround for old version of grcan where updating txwr
1432	 * in the same clock cycle as the controller updates txrd to
1433	 * the current txwr could hang the can controller
1434	 */
1435	if (priv->need_txbug_workaround) {
1436		txrd = grcan_read_reg(&regs->txrd);
1437		if (unlikely(grcan_ring_sub(txwr, txrd, dma->tx.size) == 1)) {
1438			netdev_tx_t txstatus;
1439
1440			err = grcan_txbug_workaround(dev, skb, txwr,
1441						     oneshotmode, &txstatus);
1442			if (err)
1443				return txstatus;
1444		}
1445	}
1446
1447	/* Prepare skb for echoing. This must be after the bug workaround above
1448	 * as ownership of the skb is passed on by calling can_put_echo_skb.
1449	 * Returning NETDEV_TX_BUSY or accessing skb or cf after a call to
1450	 * can_put_echo_skb would be an error unless other measures are
1451	 * taken.
1452	 */
1453	priv->txdlc[slotindex] = cf->can_dlc; /* Store dlc for statistics */
1454	can_put_echo_skb(skb, dev, slotindex);
1455
1456	/* Make sure everything is written before allowing hardware to
1457	 * read from the memory
1458	 */
1459	wmb();
1460
1461	/* Update write pointer to start transmission */
1462	grcan_write_reg(&regs->txwr,
1463			grcan_ring_add(txwr, GRCAN_MSG_SIZE, dma->tx.size));
1464
1465	return NETDEV_TX_OK;
1466}
1467
1468/* ========== Setting up sysfs interface and module parameters ========== */
1469
1470#define GRCAN_NOT_BOOL(unsigned_val) ((unsigned_val) > 1)
1471
1472#define GRCAN_MODULE_PARAM(name, mtype, valcheckf, desc)		\
1473	static void grcan_sanitize_##name(struct platform_device *pd)	\
1474	{								\
1475		struct grcan_device_config grcan_default_config		\
1476			= GRCAN_DEFAULT_DEVICE_CONFIG;			\
1477		if (valcheckf(grcan_module_config.name)) {		\
1478			dev_err(&pd->dev,				\
1479				"Invalid module parameter value for "	\
1480				#name " - setting default\n");		\
1481			grcan_module_config.name =			\
1482				grcan_default_config.name;		\
1483		}							\
1484	}								\
1485	module_param_named(name, grcan_module_config.name,		\
1486			   mtype, S_IRUGO);				\
1487	MODULE_PARM_DESC(name, desc)
1488
1489#define GRCAN_CONFIG_ATTR(name, desc)					\
1490	static ssize_t grcan_store_##name(struct device *sdev,		\
1491					  struct device_attribute *att,	\
1492					  const char *buf,		\
1493					  size_t count)			\
1494	{								\
1495		struct net_device *dev = to_net_dev(sdev);		\
1496		struct grcan_priv *priv = netdev_priv(dev);		\
1497		u8 val;							\
1498		int ret;						\
1499		if (dev->flags & IFF_UP)				\
1500			return -EBUSY;					\
1501		ret = kstrtou8(buf, 0, &val);				\
1502		if (ret < 0 || val > 1)					\
1503			return -EINVAL;					\
1504		priv->config.name = val;				\
1505		return count;						\
1506	}								\
1507	static ssize_t grcan_show_##name(struct device *sdev,		\
1508					 struct device_attribute *att,	\
1509					 char *buf)			\
1510	{								\
1511		struct net_device *dev = to_net_dev(sdev);		\
1512		struct grcan_priv *priv = netdev_priv(dev);		\
1513		return sprintf(buf, "%d\n", priv->config.name);		\
1514	}								\
1515	static DEVICE_ATTR(name, S_IRUGO | S_IWUSR,			\
1516			   grcan_show_##name,				\
1517			   grcan_store_##name);				\
1518	GRCAN_MODULE_PARAM(name, ushort, GRCAN_NOT_BOOL, desc)
1519
1520/* The following configuration options are made available both via module
1521 * parameters and writable sysfs files. See the chapter about GRCAN in the
1522 * documentation for the GRLIB VHDL library for further details.
1523 */
1524GRCAN_CONFIG_ATTR(enable0,
1525		  "Configuration of physical interface 0. Determines\n"	\
1526		  "the \"Enable 0\" bit of the configuration register.\n" \
1527		  "Format: 0 | 1\nDefault: 0\n");
1528
1529GRCAN_CONFIG_ATTR(enable1,
1530		  "Configuration of physical interface 1. Determines\n"	\
1531		  "the \"Enable 1\" bit of the configuration register.\n" \
1532		  "Format: 0 | 1\nDefault: 0\n");
1533
1534GRCAN_CONFIG_ATTR(select,
1535		  "Select which physical interface to use.\n"	\
1536		  "Format: 0 | 1\nDefault: 0\n");
1537
1538/* The tx and rx buffer size configuration options are only available via module
1539 * parameters.
1540 */
1541GRCAN_MODULE_PARAM(txsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1542		   "Sets the size of the tx buffer.\n"			\
1543		   "Format: <unsigned int> where (txsize & ~0x1fffc0) == 0\n" \
1544		   "Default: 1024\n");
1545GRCAN_MODULE_PARAM(rxsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1546		   "Sets the size of the rx buffer.\n"			\
1547		   "Format: <unsigned int> where (size & ~0x1fffc0) == 0\n" \
1548		   "Default: 1024\n");
1549
1550/* Function that makes sure that configuration done using
1551 * module parameters are set to valid values
1552 */
1553static void grcan_sanitize_module_config(struct platform_device *ofdev)
1554{
1555	grcan_sanitize_enable0(ofdev);
1556	grcan_sanitize_enable1(ofdev);
1557	grcan_sanitize_select(ofdev);
1558	grcan_sanitize_txsize(ofdev);
1559	grcan_sanitize_rxsize(ofdev);
1560}
1561
1562static const struct attribute *const sysfs_grcan_attrs[] = {
1563	/* Config attrs */
1564	&dev_attr_enable0.attr,
1565	&dev_attr_enable1.attr,
1566	&dev_attr_select.attr,
1567	NULL,
1568};
1569
1570static const struct attribute_group sysfs_grcan_group = {
1571	.name	= "grcan",
1572	.attrs	= (struct attribute **)sysfs_grcan_attrs,
1573};
1574
1575/* ========== Setting up the driver ========== */
1576
1577static const struct net_device_ops grcan_netdev_ops = {
1578	.ndo_open	= grcan_open,
1579	.ndo_stop	= grcan_close,
1580	.ndo_start_xmit	= grcan_start_xmit,
1581	.ndo_change_mtu = can_change_mtu,
1582};
1583
1584static int grcan_setup_netdev(struct platform_device *ofdev,
1585			      void __iomem *base,
1586			      int irq, u32 ambafreq, bool txbug)
1587{
1588	struct net_device *dev;
1589	struct grcan_priv *priv;
1590	struct grcan_registers __iomem *regs;
1591	int err;
1592
1593	dev = alloc_candev(sizeof(struct grcan_priv), 0);
1594	if (!dev)
1595		return -ENOMEM;
1596
1597	dev->irq = irq;
1598	dev->flags |= IFF_ECHO;
1599	dev->netdev_ops = &grcan_netdev_ops;
1600	dev->sysfs_groups[0] = &sysfs_grcan_group;
1601
1602	priv = netdev_priv(dev);
1603	memcpy(&priv->config, &grcan_module_config,
1604	       sizeof(struct grcan_device_config));
1605	priv->dev = dev;
1606	priv->regs = base;
1607	priv->can.bittiming_const = &grcan_bittiming_const;
1608	priv->can.do_set_bittiming = grcan_set_bittiming;
1609	priv->can.do_set_mode = grcan_set_mode;
1610	priv->can.do_get_berr_counter = grcan_get_berr_counter;
1611	priv->can.clock.freq = ambafreq;
1612	priv->can.ctrlmode_supported =
1613		CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_ONE_SHOT;
1614	priv->need_txbug_workaround = txbug;
1615
1616	/* Discover if triple sampling is supported by hardware */
1617	regs = priv->regs;
1618	grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
1619	grcan_set_bits(&regs->conf, GRCAN_CONF_SAM);
1620	if (grcan_read_bits(&regs->conf, GRCAN_CONF_SAM)) {
1621		priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
1622		dev_dbg(&ofdev->dev, "Hardware supports triple-sampling\n");
1623	}
1624
1625	spin_lock_init(&priv->lock);
1626
1627	if (priv->need_txbug_workaround) {
1628		init_timer(&priv->rr_timer);
1629		priv->rr_timer.function = grcan_running_reset;
1630		priv->rr_timer.data = (unsigned long)dev;
1631
1632		init_timer(&priv->hang_timer);
1633		priv->hang_timer.function = grcan_initiate_running_reset;
1634		priv->hang_timer.data = (unsigned long)dev;
1635	}
1636
1637	netif_napi_add(dev, &priv->napi, grcan_poll, GRCAN_NAPI_WEIGHT);
1638
1639	SET_NETDEV_DEV(dev, &ofdev->dev);
1640	dev_info(&ofdev->dev, "regs=0x%p, irq=%d, clock=%d\n",
1641		 priv->regs, dev->irq, priv->can.clock.freq);
1642
1643	err = register_candev(dev);
1644	if (err)
1645		goto exit_free_candev;
1646
1647	platform_set_drvdata(ofdev, dev);
1648
1649	/* Reset device to allow bit-timing to be set. No need to call
1650	 * grcan_reset at this stage. That is done in grcan_open.
1651	 */
1652	grcan_write_reg(&regs->ctrl, GRCAN_CTRL_RESET);
1653
1654	return 0;
1655exit_free_candev:
1656	free_candev(dev);
1657	return err;
1658}
1659
1660static int grcan_probe(struct platform_device *ofdev)
1661{
1662	struct device_node *np = ofdev->dev.of_node;
1663	struct resource *res;
1664	u32 sysid, ambafreq;
1665	int irq, err;
1666	void __iomem *base;
1667	bool txbug = true;
1668
1669	/* Compare GRLIB version number with the first that does not
1670	 * have the tx bug (see start_xmit)
1671	 */
1672	err = of_property_read_u32(np, "systemid", &sysid);
1673	if (!err && ((sysid & GRLIB_VERSION_MASK)
1674		     >= GRCAN_TXBUG_SAFE_GRLIB_VERSION))
1675		txbug = false;
1676
1677	err = of_property_read_u32(np, "freq", &ambafreq);
1678	if (err) {
1679		dev_err(&ofdev->dev, "unable to fetch \"freq\" property\n");
1680		goto exit_error;
1681	}
1682
1683	res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
1684	base = devm_ioremap_resource(&ofdev->dev, res);
1685	if (IS_ERR(base)) {
1686		err = PTR_ERR(base);
1687		goto exit_error;
1688	}
1689
1690	irq = irq_of_parse_and_map(np, GRCAN_IRQIX_IRQ);
1691	if (!irq) {
1692		dev_err(&ofdev->dev, "no irq found\n");
1693		err = -ENODEV;
1694		goto exit_error;
1695	}
1696
1697	grcan_sanitize_module_config(ofdev);
1698
1699	err = grcan_setup_netdev(ofdev, base, irq, ambafreq, txbug);
1700	if (err)
1701		goto exit_dispose_irq;
1702
1703	return 0;
1704
1705exit_dispose_irq:
1706	irq_dispose_mapping(irq);
1707exit_error:
1708	dev_err(&ofdev->dev,
1709		"%s socket CAN driver initialization failed with error %d\n",
1710		DRV_NAME, err);
1711	return err;
1712}
1713
1714static int grcan_remove(struct platform_device *ofdev)
1715{
1716	struct net_device *dev = platform_get_drvdata(ofdev);
1717	struct grcan_priv *priv = netdev_priv(dev);
1718
1719	unregister_candev(dev); /* Will in turn call grcan_close */
1720
1721	irq_dispose_mapping(dev->irq);
1722	netif_napi_del(&priv->napi);
1723	free_candev(dev);
1724
1725	return 0;
1726}
1727
1728static const struct of_device_id grcan_match[] = {
1729	{.name = "GAISLER_GRCAN"},
1730	{.name = "01_03d"},
1731	{.name = "GAISLER_GRHCAN"},
1732	{.name = "01_034"},
1733	{},
1734};
1735
1736MODULE_DEVICE_TABLE(of, grcan_match);
1737
1738static struct platform_driver grcan_driver = {
1739	.driver = {
1740		.name = DRV_NAME,
1741		.of_match_table = grcan_match,
1742	},
1743	.probe = grcan_probe,
1744	.remove = grcan_remove,
1745};
1746
1747module_platform_driver(grcan_driver);
1748
1749MODULE_AUTHOR("Aeroflex Gaisler AB.");
1750MODULE_DESCRIPTION("Socket CAN driver for Aeroflex Gaisler GRCAN");
1751MODULE_LICENSE("GPL");
1752