1/* 2 Madge Horizon ATM Adapter driver. 3 Copyright (C) 1995-1999 Madge Networks Ltd. 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian 20 system and in the file COPYING in the Linux kernel source. 21*/ 22 23/* 24 IMPORTANT NOTE: Madge Networks no longer makes the adapters 25 supported by this driver and makes no commitment to maintain it. 26*/ 27 28#include <linux/module.h> 29#include <linux/kernel.h> 30#include <linux/mm.h> 31#include <linux/pci.h> 32#include <linux/errno.h> 33#include <linux/atm.h> 34#include <linux/atmdev.h> 35#include <linux/sonet.h> 36#include <linux/skbuff.h> 37#include <linux/time.h> 38#include <linux/delay.h> 39#include <linux/uio.h> 40#include <linux/init.h> 41#include <linux/interrupt.h> 42#include <linux/ioport.h> 43#include <linux/wait.h> 44#include <linux/slab.h> 45 46#include <asm/io.h> 47#include <linux/atomic.h> 48#include <asm/uaccess.h> 49#include <asm/string.h> 50#include <asm/byteorder.h> 51 52#include "horizon.h" 53 54#define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>" 55#define description_string "Madge ATM Horizon [Ultra] driver" 56#define version_string "1.2.1" 57 58static inline void __init show_version (void) { 59 printk ("%s version %s\n", description_string, version_string); 60} 61 62/* 63 64 CREDITS 65 66 Driver and documentation by: 67 68 Chris Aston Madge Networks 69 Giuliano Procida Madge Networks 70 Simon Benham Madge Networks 71 Simon Johnson Madge Networks 72 Various Others Madge Networks 73 74 Some inspiration taken from other drivers by: 75 76 Alexandru Cucos UTBv 77 Kari Mettinen University of Helsinki 78 Werner Almesberger EPFL LRC 79 80 Theory of Operation 81 82 I Hardware, detection, initialisation and shutdown. 83 84 1. Supported Hardware 85 86 This driver should handle all variants of the PCI Madge ATM adapters 87 with the Horizon chipset. These are all PCI cards supporting PIO, BM 88 DMA and a form of MMIO (registers only, not internal RAM). 89 90 The driver is only known to work with SONET and UTP Horizon Ultra 91 cards at 155Mb/s. However, code is in place to deal with both the 92 original Horizon and 25Mb/s operation. 93 94 There are two revisions of the Horizon ASIC: the original and the 95 Ultra. Details of hardware bugs are in section III. 96 97 The ASIC version can be distinguished by chip markings but is NOT 98 indicated by the PCI revision (all adapters seem to have PCI rev 1). 99 100 I believe that: 101 102 Horizon => Collage 25 PCI Adapter (UTP and STP) 103 Horizon Ultra => Collage 155 PCI Client (UTP or SONET) 104 Ambassador x => Collage 155 PCI Server (completely different) 105 106 Horizon (25Mb/s) is fitted with UTP and STP connectors. It seems to 107 have a Madge B154 plus glue logic serializer. I have also found a 108 really ancient version of this with slightly different glue. It 109 comes with the revision 0 (140-025-01) ASIC. 110 111 Horizon Ultra (155Mb/s) is fitted with either a Pulse Medialink 112 output (UTP) or an HP HFBR 5205 output (SONET). It has either 113 Madge's SAMBA framer or a SUNI-lite device (early versions). It 114 comes with the revision 1 (140-027-01) ASIC. 115 116 2. Detection 117 118 All Horizon-based cards present with the same PCI Vendor and Device 119 IDs. The standard Linux 2.2 PCI API is used to locate any cards and 120 to enable bus-mastering (with appropriate latency). 121 122 ATM_LAYER_STATUS in the control register distinguishes between the 123 two possible physical layers (25 and 155). It is not clear whether 124 the 155 cards can also operate at 25Mbps. We rely on the fact that a 125 card operates at 155 if and only if it has the newer Horizon Ultra 126 ASIC. 127 128 For 155 cards the two possible framers are probed for and then set 129 up for loop-timing. 130 131 3. Initialisation 132 133 The card is reset and then put into a known state. The physical 134 layer is configured for normal operation at the appropriate speed; 135 in the case of the 155 cards, the framer is initialised with 136 line-based timing; the internal RAM is zeroed and the allocation of 137 buffers for RX and TX is made; the Burnt In Address is read and 138 copied to the ATM ESI; various policy settings for RX (VPI bits, 139 unknown VCs, oam cells) are made. Ideally all policy items should be 140 configurable at module load (if not actually on-demand), however, 141 only the vpi vs vci bit allocation can be specified at insmod. 142 143 4. Shutdown 144 145 This is in response to module_cleaup. No VCs are in use and the card 146 should be idle; it is reset. 147 148 II Driver software (as it should be) 149 150 0. Traffic Parameters 151 152 The traffic classes (not an enumeration) are currently: ATM_NONE (no 153 traffic), ATM_UBR, ATM_CBR, ATM_VBR and ATM_ABR, ATM_ANYCLASS 154 (compatible with everything). Together with (perhaps only some of) 155 the following items they make up the traffic specification. 156 157 struct atm_trafprm { 158 unsigned char traffic_class; traffic class (ATM_UBR, ...) 159 int max_pcr; maximum PCR in cells per second 160 int pcr; desired PCR in cells per second 161 int min_pcr; minimum PCR in cells per second 162 int max_cdv; maximum CDV in microseconds 163 int max_sdu; maximum SDU in bytes 164 }; 165 166 Note that these denote bandwidth available not bandwidth used; the 167 possibilities according to ATMF are: 168 169 Real Time (cdv and max CDT given) 170 171 CBR(pcr) pcr bandwidth always available 172 rtVBR(pcr,scr,mbs) scr bandwidth always available, up to pcr at mbs too 173 174 Non Real Time 175 176 nrtVBR(pcr,scr,mbs) scr bandwidth always available, up to pcr at mbs too 177 UBR() 178 ABR(mcr,pcr) mcr bandwidth always available, up to pcr (depending) too 179 180 mbs is max burst size (bucket) 181 pcr and scr have associated cdvt values 182 mcr is like scr but has no cdtv 183 cdtv may differ at each hop 184 185 Some of the above items are qos items (as opposed to traffic 186 parameters). We have nothing to do with qos. All except ABR can have 187 their traffic parameters converted to GCRA parameters. The GCRA may 188 be implemented as a (real-number) leaky bucket. The GCRA can be used 189 in complicated ways by switches and in simpler ways by end-stations. 190 It can be used both to filter incoming cells and shape out-going 191 cells. 192 193 ATM Linux actually supports: 194 195 ATM_NONE() (no traffic in this direction) 196 ATM_UBR(max_frame_size) 197 ATM_CBR(max/min_pcr, max_cdv, max_frame_size) 198 199 0 or ATM_MAX_PCR are used to indicate maximum available PCR 200 201 A traffic specification consists of the AAL type and separate 202 traffic specifications for either direction. In ATM Linux it is: 203 204 struct atm_qos { 205 struct atm_trafprm txtp; 206 struct atm_trafprm rxtp; 207 unsigned char aal; 208 }; 209 210 AAL types are: 211 212 ATM_NO_AAL AAL not specified 213 ATM_AAL0 "raw" ATM cells 214 ATM_AAL1 AAL1 (CBR) 215 ATM_AAL2 AAL2 (VBR) 216 ATM_AAL34 AAL3/4 (data) 217 ATM_AAL5 AAL5 (data) 218 ATM_SAAL signaling AAL 219 220 The Horizon has support for AAL frame types: 0, 3/4 and 5. However, 221 it does not implement AAL 3/4 SAR and it has a different notion of 222 "raw cell" to ATM Linux's (48 bytes vs. 52 bytes) so neither are 223 supported by this driver. 224 225 The Horizon has limited support for ABR (including UBR), VBR and 226 CBR. Each TX channel has a bucket (containing up to 31 cell units) 227 and two timers (PCR and SCR) associated with it that can be used to 228 govern cell emissions and host notification (in the case of ABR this 229 is presumably so that RM cells may be emitted at appropriate times). 230 The timers may either be disabled or may be set to any of 240 values 231 (determined by the clock crystal, a fixed (?) per-device divider, a 232 configurable divider and a configurable timer preload value). 233 234 At the moment only UBR and CBR are supported by the driver. VBR will 235 be supported as soon as ATM for Linux supports it. ABR support is 236 very unlikely as RM cell handling is completely up to the driver. 237 238 1. TX (TX channel setup and TX transfer) 239 240 The TX half of the driver owns the TX Horizon registers. The TX 241 component in the IRQ handler is the BM completion handler. This can 242 only be entered when tx_busy is true (enforced by hardware). The 243 other TX component can only be entered when tx_busy is false 244 (enforced by driver). So TX is single-threaded. 245 246 Apart from a minor optimisation to not re-select the last channel, 247 the TX send component works as follows: 248 249 Atomic test and set tx_busy until we succeed; we should implement 250 some sort of timeout so that tx_busy will never be stuck at true. 251 252 If no TX channel is set up for this VC we wait for an idle one (if 253 necessary) and set it up. 254 255 At this point we have a TX channel ready for use. We wait for enough 256 buffers to become available then start a TX transmit (set the TX 257 descriptor, schedule transfer, exit). 258 259 The IRQ component handles TX completion (stats, free buffer, tx_busy 260 unset, exit). We also re-schedule further transfers for the same 261 frame if needed. 262 263 TX setup in more detail: 264 265 TX open is a nop, the relevant information is held in the hrz_vcc 266 (vcc->dev_data) structure and is "cached" on the card. 267 268 TX close gets the TX lock and clears the channel from the "cache". 269 270 2. RX (Data Available and RX transfer) 271 272 The RX half of the driver owns the RX registers. There are two RX 273 components in the IRQ handler: the data available handler deals with 274 fresh data that has arrived on the card, the BM completion handler 275 is very similar to the TX completion handler. The data available 276 handler grabs the rx_lock and it is only released once the data has 277 been discarded or completely transferred to the host. The BM 278 completion handler only runs when the lock is held; the data 279 available handler is locked out over the same period. 280 281 Data available on the card triggers an interrupt. If the data is not 282 suitable for our existing RX channels or we cannot allocate a buffer 283 it is flushed. Otherwise an RX receive is scheduled. Multiple RX 284 transfers may be scheduled for the same frame. 285 286 RX setup in more detail: 287 288 RX open... 289 RX close... 290 291 III Hardware Bugs 292 293 0. Byte vs Word addressing of adapter RAM. 294 295 A design feature; see the .h file (especially the memory map). 296 297 1. Bus Master Data Transfers (original Horizon only, fixed in Ultra) 298 299 The host must not start a transmit direction transfer at a 300 non-four-byte boundary in host memory. Instead the host should 301 perform a byte, or a two byte, or one byte followed by two byte 302 transfer in order to start the rest of the transfer on a four byte 303 boundary. RX is OK. 304 305 Simultaneous transmit and receive direction bus master transfers are 306 not allowed. 307 308 The simplest solution to these two is to always do PIO (never DMA) 309 in the TX direction on the original Horizon. More complicated 310 solutions are likely to hurt my brain. 311 312 2. Loss of buffer on close VC 313 314 When a VC is being closed, the buffer associated with it is not 315 returned to the pool. The host must store the reference to this 316 buffer and when opening a new VC then give it to that new VC. 317 318 The host intervention currently consists of stacking such a buffer 319 pointer at VC close and checking the stack at VC open. 320 321 3. Failure to close a VC 322 323 If a VC is currently receiving a frame then closing the VC may fail 324 and the frame continues to be received. 325 326 The solution is to make sure any received frames are flushed when 327 ready. This is currently done just before the solution to 2. 328 329 4. PCI bus (original Horizon only, fixed in Ultra) 330 331 Reading from the data port prior to initialisation will hang the PCI 332 bus. Just don't do that then! We don't. 333 334 IV To Do List 335 336 . Timer code may be broken. 337 338 . Allow users to specify buffer allocation split for TX and RX. 339 340 . Deal once and for all with buggy VC close. 341 342 . Handle interrupted and/or non-blocking operations. 343 344 . Change some macros to functions and move from .h to .c. 345 346 . Try to limit the number of TX frames each VC may have queued, in 347 order to reduce the chances of TX buffer exhaustion. 348 349 . Implement VBR (bucket and timers not understood) and ABR (need to 350 do RM cells manually); also no Linux support for either. 351 352 . Implement QoS changes on open VCs (involves extracting parts of VC open 353 and close into separate functions and using them to make changes). 354 355*/ 356 357/********** globals **********/ 358 359static void do_housekeeping (unsigned long arg); 360 361static unsigned short debug = 0; 362static unsigned short vpi_bits = 0; 363static int max_tx_size = 9000; 364static int max_rx_size = 9000; 365static unsigned char pci_lat = 0; 366 367/********** access functions **********/ 368 369/* Read / Write Horizon registers */ 370static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) { 371 outl (cpu_to_le32 (data), dev->iobase + reg); 372} 373 374static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) { 375 return le32_to_cpu (inl (dev->iobase + reg)); 376} 377 378static inline void wr_regw (const hrz_dev * dev, unsigned char reg, u16 data) { 379 outw (cpu_to_le16 (data), dev->iobase + reg); 380} 381 382static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) { 383 return le16_to_cpu (inw (dev->iobase + reg)); 384} 385 386static inline void wrs_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) { 387 outsb (dev->iobase + reg, addr, len); 388} 389 390static inline void rds_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) { 391 insb (dev->iobase + reg, addr, len); 392} 393 394/* Read / Write to a given address in Horizon buffer memory. 395 Interrupts must be disabled between the address register and data 396 port accesses as these must form an atomic operation. */ 397static inline void wr_mem (const hrz_dev * dev, HDW * addr, u32 data) { 398 // wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr); 399 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW)); 400 wr_regl (dev, MEMORY_PORT_OFF, data); 401} 402 403static inline u32 rd_mem (const hrz_dev * dev, HDW * addr) { 404 // wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr); 405 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW)); 406 return rd_regl (dev, MEMORY_PORT_OFF); 407} 408 409static inline void wr_framer (const hrz_dev * dev, u32 addr, u32 data) { 410 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000); 411 wr_regl (dev, MEMORY_PORT_OFF, data); 412} 413 414static inline u32 rd_framer (const hrz_dev * dev, u32 addr) { 415 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000); 416 return rd_regl (dev, MEMORY_PORT_OFF); 417} 418 419/********** specialised access functions **********/ 420 421/* RX */ 422 423static inline void FLUSH_RX_CHANNEL (hrz_dev * dev, u16 channel) { 424 wr_regw (dev, RX_CHANNEL_PORT_OFF, FLUSH_CHANNEL | channel); 425 return; 426} 427 428static void WAIT_FLUSH_RX_COMPLETE (hrz_dev * dev) { 429 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & FLUSH_CHANNEL) 430 ; 431 return; 432} 433 434static inline void SELECT_RX_CHANNEL (hrz_dev * dev, u16 channel) { 435 wr_regw (dev, RX_CHANNEL_PORT_OFF, channel); 436 return; 437} 438 439static void WAIT_UPDATE_COMPLETE (hrz_dev * dev) { 440 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & RX_CHANNEL_UPDATE_IN_PROGRESS) 441 ; 442 return; 443} 444 445/* TX */ 446 447static inline void SELECT_TX_CHANNEL (hrz_dev * dev, u16 tx_channel) { 448 wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel); 449 return; 450} 451 452/* Update or query one configuration parameter of a particular channel. */ 453 454static inline void update_tx_channel_config (hrz_dev * dev, short chan, u8 mode, u16 value) { 455 wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF, 456 chan * TX_CHANNEL_CONFIG_MULT | mode); 457 wr_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF, value); 458 return; 459} 460 461/********** dump functions **********/ 462 463static inline void dump_skb (char * prefix, unsigned int vc, struct sk_buff * skb) { 464#ifdef DEBUG_HORIZON 465 unsigned int i; 466 unsigned char * data = skb->data; 467 PRINTDB (DBG_DATA, "%s(%u) ", prefix, vc); 468 for (i=0; i<skb->len && i < 256;i++) 469 PRINTDM (DBG_DATA, "%02x ", data[i]); 470 PRINTDE (DBG_DATA,""); 471#else 472 (void) prefix; 473 (void) vc; 474 (void) skb; 475#endif 476 return; 477} 478 479static inline void dump_regs (hrz_dev * dev) { 480#ifdef DEBUG_HORIZON 481 PRINTD (DBG_REGS, "CONTROL 0: %#x", rd_regl (dev, CONTROL_0_REG)); 482 PRINTD (DBG_REGS, "RX CONFIG: %#x", rd_regw (dev, RX_CONFIG_OFF)); 483 PRINTD (DBG_REGS, "TX CONFIG: %#x", rd_regw (dev, TX_CONFIG_OFF)); 484 PRINTD (DBG_REGS, "TX STATUS: %#x", rd_regw (dev, TX_STATUS_OFF)); 485 PRINTD (DBG_REGS, "IRQ ENBLE: %#x", rd_regl (dev, INT_ENABLE_REG_OFF)); 486 PRINTD (DBG_REGS, "IRQ SORCE: %#x", rd_regl (dev, INT_SOURCE_REG_OFF)); 487#else 488 (void) dev; 489#endif 490 return; 491} 492 493static inline void dump_framer (hrz_dev * dev) { 494#ifdef DEBUG_HORIZON 495 unsigned int i; 496 PRINTDB (DBG_REGS, "framer registers:"); 497 for (i = 0; i < 0x10; ++i) 498 PRINTDM (DBG_REGS, " %02x", rd_framer (dev, i)); 499 PRINTDE (DBG_REGS,""); 500#else 501 (void) dev; 502#endif 503 return; 504} 505 506/********** VPI/VCI <-> (RX) channel conversions **********/ 507 508/* RX channels are 10 bit integers, these fns are quite paranoid */ 509 510static inline int vpivci_to_channel (u16 * channel, const short vpi, const int vci) { 511 unsigned short vci_bits = 10 - vpi_bits; 512 if (0 <= vpi && vpi < 1<<vpi_bits && 0 <= vci && vci < 1<<vci_bits) { 513 *channel = vpi<<vci_bits | vci; 514 return *channel ? 0 : -EINVAL; 515 } 516 return -EINVAL; 517} 518 519/********** decode RX queue entries **********/ 520 521static inline u16 rx_q_entry_to_length (u32 x) { 522 return x & RX_Q_ENTRY_LENGTH_MASK; 523} 524 525static inline u16 rx_q_entry_to_rx_channel (u32 x) { 526 return (x>>RX_Q_ENTRY_CHANNEL_SHIFT) & RX_CHANNEL_MASK; 527} 528 529/* Cell Transmit Rate Values 530 * 531 * the cell transmit rate (cells per sec) can be set to a variety of 532 * different values by specifying two parameters: a timer preload from 533 * 1 to 16 (stored as 0 to 15) and a clock divider (2 to the power of 534 * an exponent from 0 to 14; the special value 15 disables the timer). 535 * 536 * cellrate = baserate / (preload * 2^divider) 537 * 538 * The maximum cell rate that can be specified is therefore just the 539 * base rate. Halving the preload is equivalent to adding 1 to the 540 * divider and so values 1 to 8 of the preload are redundant except 541 * in the case of a maximal divider (14). 542 * 543 * Given a desired cell rate, an algorithm to determine the preload 544 * and divider is: 545 * 546 * a) x = baserate / cellrate, want p * 2^d = x (as far as possible) 547 * b) if x > 16 * 2^14 then set p = 16, d = 14 (min rate), done 548 * if x <= 16 then set p = x, d = 0 (high rates), done 549 * c) now have 16 < x <= 2^18, or 1 < x/16 <= 2^14 and we want to 550 * know n such that 2^(n-1) < x/16 <= 2^n, so slide a bit until 551 * we find the range (n will be between 1 and 14), set d = n 552 * d) Also have 8 < x/2^n <= 16, so set p nearest x/2^n 553 * 554 * The algorithm used below is a minor variant of the above. 555 * 556 * The base rate is derived from the oscillator frequency (Hz) using a 557 * fixed divider: 558 * 559 * baserate = freq / 32 in the case of some Unknown Card 560 * baserate = freq / 8 in the case of the Horizon 25 561 * baserate = freq / 8 in the case of the Horizon Ultra 155 562 * 563 * The Horizon cards have oscillators and base rates as follows: 564 * 565 * Card Oscillator Base Rate 566 * Unknown Card 33 MHz 1.03125 MHz (33 MHz = PCI freq) 567 * Horizon 25 32 MHz 4 MHz 568 * Horizon Ultra 155 40 MHz 5 MHz 569 * 570 * The following defines give the base rates in Hz. These were 571 * previously a factor of 100 larger, no doubt someone was using 572 * cps*100. 573 */ 574 575#define BR_UKN 1031250l 576#define BR_HRZ 4000000l 577#define BR_ULT 5000000l 578 579// d is an exponent 580#define CR_MIND 0 581#define CR_MAXD 14 582 583// p ranges from 1 to a power of 2 584#define CR_MAXPEXP 4 585 586static int make_rate (const hrz_dev * dev, u32 c, rounding r, 587 u16 * bits, unsigned int * actual) 588{ 589 // note: rounding the rate down means rounding 'p' up 590 const unsigned long br = test_bit(ultra, &dev->flags) ? BR_ULT : BR_HRZ; 591 592 u32 div = CR_MIND; 593 u32 pre; 594 595 // br_exp and br_man are used to avoid overflowing (c*maxp*2^d) in 596 // the tests below. We could think harder about exact possibilities 597 // of failure... 598 599 unsigned long br_man = br; 600 unsigned int br_exp = 0; 601 602 PRINTD (DBG_QOS|DBG_FLOW, "make_rate b=%lu, c=%u, %s", br, c, 603 r == round_up ? "up" : r == round_down ? "down" : "nearest"); 604 605 // avoid div by zero 606 if (!c) { 607 PRINTD (DBG_QOS|DBG_ERR, "zero rate is not allowed!"); 608 return -EINVAL; 609 } 610 611 while (br_exp < CR_MAXPEXP + CR_MIND && (br_man % 2 == 0)) { 612 br_man = br_man >> 1; 613 ++br_exp; 614 } 615 // (br >>br_exp) <<br_exp == br and 616 // br_exp <= CR_MAXPEXP+CR_MIND 617 618 if (br_man <= (c << (CR_MAXPEXP+CR_MIND-br_exp))) { 619 // Equivalent to: B <= (c << (MAXPEXP+MIND)) 620 // take care of rounding 621 switch (r) { 622 case round_down: 623 pre = DIV_ROUND_UP(br, c<<div); 624 // but p must be non-zero 625 if (!pre) 626 pre = 1; 627 break; 628 case round_nearest: 629 pre = DIV_ROUND_CLOSEST(br, c<<div); 630 // but p must be non-zero 631 if (!pre) 632 pre = 1; 633 break; 634 default: /* round_up */ 635 pre = br/(c<<div); 636 // but p must be non-zero 637 if (!pre) 638 return -EINVAL; 639 } 640 PRINTD (DBG_QOS, "A: p=%u, d=%u", pre, div); 641 goto got_it; 642 } 643 644 // at this point we have 645 // d == MIND and (c << (MAXPEXP+MIND)) < B 646 while (div < CR_MAXD) { 647 div++; 648 if (br_man <= (c << (CR_MAXPEXP+div-br_exp))) { 649 // Equivalent to: B <= (c << (MAXPEXP+d)) 650 // c << (MAXPEXP+d-1) < B <= c << (MAXPEXP+d) 651 // 1 << (MAXPEXP-1) < B/2^d/c <= 1 << MAXPEXP 652 // MAXP/2 < B/c2^d <= MAXP 653 // take care of rounding 654 switch (r) { 655 case round_down: 656 pre = DIV_ROUND_UP(br, c<<div); 657 break; 658 case round_nearest: 659 pre = DIV_ROUND_CLOSEST(br, c<<div); 660 break; 661 default: /* round_up */ 662 pre = br/(c<<div); 663 } 664 PRINTD (DBG_QOS, "B: p=%u, d=%u", pre, div); 665 goto got_it; 666 } 667 } 668 // at this point we have 669 // d == MAXD and (c << (MAXPEXP+MAXD)) < B 670 // but we cannot go any higher 671 // take care of rounding 672 if (r == round_down) 673 return -EINVAL; 674 pre = 1 << CR_MAXPEXP; 675 PRINTD (DBG_QOS, "C: p=%u, d=%u", pre, div); 676got_it: 677 // paranoia 678 if (div > CR_MAXD || (!pre) || pre > 1<<CR_MAXPEXP) { 679 PRINTD (DBG_QOS, "set_cr internal failure: d=%u p=%u", 680 div, pre); 681 return -EINVAL; 682 } else { 683 if (bits) 684 *bits = (div<<CLOCK_SELECT_SHIFT) | (pre-1); 685 if (actual) { 686 *actual = DIV_ROUND_UP(br, pre<<div); 687 PRINTD (DBG_QOS, "actual rate: %u", *actual); 688 } 689 return 0; 690 } 691} 692 693static int make_rate_with_tolerance (const hrz_dev * dev, u32 c, rounding r, unsigned int tol, 694 u16 * bit_pattern, unsigned int * actual) { 695 unsigned int my_actual; 696 697 PRINTD (DBG_QOS|DBG_FLOW, "make_rate_with_tolerance c=%u, %s, tol=%u", 698 c, (r == round_up) ? "up" : (r == round_down) ? "down" : "nearest", tol); 699 700 if (!actual) 701 // actual rate is not returned 702 actual = &my_actual; 703 704 if (make_rate (dev, c, round_nearest, bit_pattern, actual)) 705 // should never happen as round_nearest always succeeds 706 return -1; 707 708 if (c - tol <= *actual && *actual <= c + tol) 709 // within tolerance 710 return 0; 711 else 712 // intolerant, try rounding instead 713 return make_rate (dev, c, r, bit_pattern, actual); 714} 715 716/********** Listen on a VC **********/ 717 718static int hrz_open_rx (hrz_dev * dev, u16 channel) { 719 // is there any guarantee that we don't get two simulataneous 720 // identical calls of this function from different processes? yes 721 // rate_lock 722 unsigned long flags; 723 u32 channel_type; // u16? 724 725 u16 buf_ptr = RX_CHANNEL_IDLE; 726 727 rx_ch_desc * rx_desc = &memmap->rx_descs[channel]; 728 729 PRINTD (DBG_FLOW, "hrz_open_rx %x", channel); 730 731 spin_lock_irqsave (&dev->mem_lock, flags); 732 channel_type = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK; 733 spin_unlock_irqrestore (&dev->mem_lock, flags); 734 735 // very serious error, should never occur 736 if (channel_type != RX_CHANNEL_DISABLED) { 737 PRINTD (DBG_ERR|DBG_VCC, "RX channel for VC already open"); 738 return -EBUSY; // clean up? 739 } 740 741 // Give back spare buffer 742 if (dev->noof_spare_buffers) { 743 buf_ptr = dev->spare_buffers[--dev->noof_spare_buffers]; 744 PRINTD (DBG_VCC, "using a spare buffer: %u", buf_ptr); 745 // should never occur 746 if (buf_ptr == RX_CHANNEL_DISABLED || buf_ptr == RX_CHANNEL_IDLE) { 747 // but easy to recover from 748 PRINTD (DBG_ERR|DBG_VCC, "bad spare buffer pointer, using IDLE"); 749 buf_ptr = RX_CHANNEL_IDLE; 750 } 751 } else { 752 PRINTD (DBG_VCC, "using IDLE buffer pointer"); 753 } 754 755 // Channel is currently disabled so change its status to idle 756 757 // do we really need to save the flags again? 758 spin_lock_irqsave (&dev->mem_lock, flags); 759 760 wr_mem (dev, &rx_desc->wr_buf_type, 761 buf_ptr | CHANNEL_TYPE_AAL5 | FIRST_CELL_OF_AAL5_FRAME); 762 if (buf_ptr != RX_CHANNEL_IDLE) 763 wr_mem (dev, &rx_desc->rd_buf_type, buf_ptr); 764 765 spin_unlock_irqrestore (&dev->mem_lock, flags); 766 767 // rxer->rate = make_rate (qos->peak_cells); 768 769 PRINTD (DBG_FLOW, "hrz_open_rx ok"); 770 771 return 0; 772} 773 774#if 0 775/********** change vc rate for a given vc **********/ 776 777static void hrz_change_vc_qos (ATM_RXER * rxer, MAAL_QOS * qos) { 778 rxer->rate = make_rate (qos->peak_cells); 779} 780#endif 781 782/********** free an skb (as per ATM device driver documentation) **********/ 783 784static void hrz_kfree_skb (struct sk_buff * skb) { 785 if (ATM_SKB(skb)->vcc->pop) { 786 ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb); 787 } else { 788 dev_kfree_skb_any (skb); 789 } 790} 791 792/********** cancel listen on a VC **********/ 793 794static void hrz_close_rx (hrz_dev * dev, u16 vc) { 795 unsigned long flags; 796 797 u32 value; 798 799 u32 r1, r2; 800 801 rx_ch_desc * rx_desc = &memmap->rx_descs[vc]; 802 803 int was_idle = 0; 804 805 spin_lock_irqsave (&dev->mem_lock, flags); 806 value = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK; 807 spin_unlock_irqrestore (&dev->mem_lock, flags); 808 809 if (value == RX_CHANNEL_DISABLED) { 810 // I suppose this could happen once we deal with _NONE traffic properly 811 PRINTD (DBG_VCC, "closing VC: RX channel %u already disabled", vc); 812 return; 813 } 814 if (value == RX_CHANNEL_IDLE) 815 was_idle = 1; 816 817 spin_lock_irqsave (&dev->mem_lock, flags); 818 819 for (;;) { 820 wr_mem (dev, &rx_desc->wr_buf_type, RX_CHANNEL_DISABLED); 821 822 if ((rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK) == RX_CHANNEL_DISABLED) 823 break; 824 825 was_idle = 0; 826 } 827 828 if (was_idle) { 829 spin_unlock_irqrestore (&dev->mem_lock, flags); 830 return; 831 } 832 833 WAIT_FLUSH_RX_COMPLETE(dev); 834 835 // XXX Is this all really necessary? We can rely on the rx_data_av 836 // handler to discard frames that remain queued for delivery. If the 837 // worry is that immediately reopening the channel (perhaps by a 838 // different process) may cause some data to be mis-delivered then 839 // there may still be a simpler solution (such as busy-waiting on 840 // rx_busy once the channel is disabled or before a new one is 841 // opened - does this leave any holes?). Arguably setting up and 842 // tearing down the TX and RX halves of each virtual circuit could 843 // most safely be done within ?x_busy protected regions. 844 845 // OK, current changes are that Simon's marker is disabled and we DO 846 // look for NULL rxer elsewhere. The code here seems flush frames 847 // and then remember the last dead cell belonging to the channel 848 // just disabled - the cell gets relinked at the next vc_open. 849 // However, when all VCs are closed or only a few opened there are a 850 // handful of buffers that are unusable. 851 852 // Does anyone feel like documenting spare_buffers properly? 853 // Does anyone feel like fixing this in a nicer way? 854 855 // Flush any data which is left in the channel 856 for (;;) { 857 // Change the rx channel port to something different to the RX 858 // channel we are trying to close to force Horizon to flush the rx 859 // channel read and write pointers. 860 861 u16 other = vc^(RX_CHANS/2); 862 863 SELECT_RX_CHANNEL (dev, other); 864 WAIT_UPDATE_COMPLETE (dev); 865 866 r1 = rd_mem (dev, &rx_desc->rd_buf_type); 867 868 // Select this RX channel. Flush doesn't seem to work unless we 869 // select an RX channel before hand 870 871 SELECT_RX_CHANNEL (dev, vc); 872 WAIT_UPDATE_COMPLETE (dev); 873 874 // Attempt to flush a frame on this RX channel 875 876 FLUSH_RX_CHANNEL (dev, vc); 877 WAIT_FLUSH_RX_COMPLETE (dev); 878 879 // Force Horizon to flush rx channel read and write pointers as before 880 881 SELECT_RX_CHANNEL (dev, other); 882 WAIT_UPDATE_COMPLETE (dev); 883 884 r2 = rd_mem (dev, &rx_desc->rd_buf_type); 885 886 PRINTD (DBG_VCC|DBG_RX, "r1 = %u, r2 = %u", r1, r2); 887 888 if (r1 == r2) { 889 dev->spare_buffers[dev->noof_spare_buffers++] = (u16)r1; 890 break; 891 } 892 } 893 894#if 0 895 { 896 rx_q_entry * wr_ptr = &memmap->rx_q_entries[rd_regw (dev, RX_QUEUE_WR_PTR_OFF)]; 897 rx_q_entry * rd_ptr = dev->rx_q_entry; 898 899 PRINTD (DBG_VCC|DBG_RX, "rd_ptr = %u, wr_ptr = %u", rd_ptr, wr_ptr); 900 901 while (rd_ptr != wr_ptr) { 902 u32 x = rd_mem (dev, (HDW *) rd_ptr); 903 904 if (vc == rx_q_entry_to_rx_channel (x)) { 905 x |= SIMONS_DODGEY_MARKER; 906 907 PRINTD (DBG_RX|DBG_VCC|DBG_WARN, "marking a frame as dodgey"); 908 909 wr_mem (dev, (HDW *) rd_ptr, x); 910 } 911 912 if (rd_ptr == dev->rx_q_wrap) 913 rd_ptr = dev->rx_q_reset; 914 else 915 rd_ptr++; 916 } 917 } 918#endif 919 920 spin_unlock_irqrestore (&dev->mem_lock, flags); 921 922 return; 923} 924 925/********** schedule RX transfers **********/ 926 927// Note on tail recursion: a GCC developer said that it is not likely 928// to be fixed soon, so do not define TAILRECUSRIONWORKS unless you 929// are sure it does as you may otherwise overflow the kernel stack. 930 931// giving this fn a return value would help GCC, allegedly 932 933static void rx_schedule (hrz_dev * dev, int irq) { 934 unsigned int rx_bytes; 935 936 int pio_instead = 0; 937#ifndef TAILRECURSIONWORKS 938 pio_instead = 1; 939 while (pio_instead) { 940#endif 941 // bytes waiting for RX transfer 942 rx_bytes = dev->rx_bytes; 943 944#if 0 945 spin_count = 0; 946 while (rd_regl (dev, MASTER_RX_COUNT_REG_OFF)) { 947 PRINTD (DBG_RX|DBG_WARN, "RX error: other PCI Bus Master RX still in progress!"); 948 if (++spin_count > 10) { 949 PRINTD (DBG_RX|DBG_ERR, "spun out waiting PCI Bus Master RX completion"); 950 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); 951 clear_bit (rx_busy, &dev->flags); 952 hrz_kfree_skb (dev->rx_skb); 953 return; 954 } 955 } 956#endif 957 958 // this code follows the TX code but (at the moment) there is only 959 // one region - the skb itself. I don't know if this will change, 960 // but it doesn't hurt to have the code here, disabled. 961 962 if (rx_bytes) { 963 // start next transfer within same region 964 if (rx_bytes <= MAX_PIO_COUNT) { 965 PRINTD (DBG_RX|DBG_BUS, "(pio)"); 966 pio_instead = 1; 967 } 968 if (rx_bytes <= MAX_TRANSFER_COUNT) { 969 PRINTD (DBG_RX|DBG_BUS, "(simple or last multi)"); 970 dev->rx_bytes = 0; 971 } else { 972 PRINTD (DBG_RX|DBG_BUS, "(continuing multi)"); 973 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT; 974 rx_bytes = MAX_TRANSFER_COUNT; 975 } 976 } else { 977 // rx_bytes == 0 -- we're between regions 978 // regions remaining to transfer 979#if 0 980 unsigned int rx_regions = dev->rx_regions; 981#else 982 unsigned int rx_regions = 0; 983#endif 984 985 if (rx_regions) { 986#if 0 987 // start a new region 988 dev->rx_addr = dev->rx_iovec->iov_base; 989 rx_bytes = dev->rx_iovec->iov_len; 990 ++dev->rx_iovec; 991 dev->rx_regions = rx_regions - 1; 992 993 if (rx_bytes <= MAX_PIO_COUNT) { 994 PRINTD (DBG_RX|DBG_BUS, "(pio)"); 995 pio_instead = 1; 996 } 997 if (rx_bytes <= MAX_TRANSFER_COUNT) { 998 PRINTD (DBG_RX|DBG_BUS, "(full region)"); 999 dev->rx_bytes = 0; 1000 } else { 1001 PRINTD (DBG_RX|DBG_BUS, "(start multi region)"); 1002 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT; 1003 rx_bytes = MAX_TRANSFER_COUNT; 1004 } 1005#endif 1006 } else { 1007 // rx_regions == 0 1008 // that's all folks - end of frame 1009 struct sk_buff * skb = dev->rx_skb; 1010 // dev->rx_iovec = 0; 1011 1012 FLUSH_RX_CHANNEL (dev, dev->rx_channel); 1013 1014 dump_skb ("<<<", dev->rx_channel, skb); 1015 1016 PRINTD (DBG_RX|DBG_SKB, "push %p %u", skb->data, skb->len); 1017 1018 { 1019 struct atm_vcc * vcc = ATM_SKB(skb)->vcc; 1020 // VC layer stats 1021 atomic_inc(&vcc->stats->rx); 1022 __net_timestamp(skb); 1023 // end of our responsibility 1024 vcc->push (vcc, skb); 1025 } 1026 } 1027 } 1028 1029 // note: writing RX_COUNT clears any interrupt condition 1030 if (rx_bytes) { 1031 if (pio_instead) { 1032 if (irq) 1033 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); 1034 rds_regb (dev, DATA_PORT_OFF, dev->rx_addr, rx_bytes); 1035 } else { 1036 wr_regl (dev, MASTER_RX_ADDR_REG_OFF, virt_to_bus (dev->rx_addr)); 1037 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, rx_bytes); 1038 } 1039 dev->rx_addr += rx_bytes; 1040 } else { 1041 if (irq) 1042 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); 1043 // allow another RX thread to start 1044 YELLOW_LED_ON(dev); 1045 clear_bit (rx_busy, &dev->flags); 1046 PRINTD (DBG_RX, "cleared rx_busy for dev %p", dev); 1047 } 1048 1049#ifdef TAILRECURSIONWORKS 1050 // and we all bless optimised tail calls 1051 if (pio_instead) 1052 return rx_schedule (dev, 0); 1053 return; 1054#else 1055 // grrrrrrr! 1056 irq = 0; 1057 } 1058 return; 1059#endif 1060} 1061 1062/********** handle RX bus master complete events **********/ 1063 1064static void rx_bus_master_complete_handler (hrz_dev * dev) { 1065 if (test_bit (rx_busy, &dev->flags)) { 1066 rx_schedule (dev, 1); 1067 } else { 1068 PRINTD (DBG_RX|DBG_ERR, "unexpected RX bus master completion"); 1069 // clear interrupt condition on adapter 1070 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); 1071 } 1072 return; 1073} 1074 1075/********** (queue to) become the next TX thread **********/ 1076 1077static int tx_hold (hrz_dev * dev) { 1078 PRINTD (DBG_TX, "sleeping at tx lock %p %lu", dev, dev->flags); 1079 wait_event_interruptible(dev->tx_queue, (!test_and_set_bit(tx_busy, &dev->flags))); 1080 PRINTD (DBG_TX, "woken at tx lock %p %lu", dev, dev->flags); 1081 if (signal_pending (current)) 1082 return -1; 1083 PRINTD (DBG_TX, "set tx_busy for dev %p", dev); 1084 return 0; 1085} 1086 1087/********** allow another TX thread to start **********/ 1088 1089static inline void tx_release (hrz_dev * dev) { 1090 clear_bit (tx_busy, &dev->flags); 1091 PRINTD (DBG_TX, "cleared tx_busy for dev %p", dev); 1092 wake_up_interruptible (&dev->tx_queue); 1093} 1094 1095/********** schedule TX transfers **********/ 1096 1097static void tx_schedule (hrz_dev * const dev, int irq) { 1098 unsigned int tx_bytes; 1099 1100 int append_desc = 0; 1101 1102 int pio_instead = 0; 1103#ifndef TAILRECURSIONWORKS 1104 pio_instead = 1; 1105 while (pio_instead) { 1106#endif 1107 // bytes in current region waiting for TX transfer 1108 tx_bytes = dev->tx_bytes; 1109 1110#if 0 1111 spin_count = 0; 1112 while (rd_regl (dev, MASTER_TX_COUNT_REG_OFF)) { 1113 PRINTD (DBG_TX|DBG_WARN, "TX error: other PCI Bus Master TX still in progress!"); 1114 if (++spin_count > 10) { 1115 PRINTD (DBG_TX|DBG_ERR, "spun out waiting PCI Bus Master TX completion"); 1116 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0); 1117 tx_release (dev); 1118 hrz_kfree_skb (dev->tx_skb); 1119 return; 1120 } 1121 } 1122#endif 1123 1124 if (tx_bytes) { 1125 // start next transfer within same region 1126 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) { 1127 PRINTD (DBG_TX|DBG_BUS, "(pio)"); 1128 pio_instead = 1; 1129 } 1130 if (tx_bytes <= MAX_TRANSFER_COUNT) { 1131 PRINTD (DBG_TX|DBG_BUS, "(simple or last multi)"); 1132 if (!dev->tx_iovec) { 1133 // end of last region 1134 append_desc = 1; 1135 } 1136 dev->tx_bytes = 0; 1137 } else { 1138 PRINTD (DBG_TX|DBG_BUS, "(continuing multi)"); 1139 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT; 1140 tx_bytes = MAX_TRANSFER_COUNT; 1141 } 1142 } else { 1143 // tx_bytes == 0 -- we're between regions 1144 // regions remaining to transfer 1145 unsigned int tx_regions = dev->tx_regions; 1146 1147 if (tx_regions) { 1148 // start a new region 1149 dev->tx_addr = dev->tx_iovec->iov_base; 1150 tx_bytes = dev->tx_iovec->iov_len; 1151 ++dev->tx_iovec; 1152 dev->tx_regions = tx_regions - 1; 1153 1154 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) { 1155 PRINTD (DBG_TX|DBG_BUS, "(pio)"); 1156 pio_instead = 1; 1157 } 1158 if (tx_bytes <= MAX_TRANSFER_COUNT) { 1159 PRINTD (DBG_TX|DBG_BUS, "(full region)"); 1160 dev->tx_bytes = 0; 1161 } else { 1162 PRINTD (DBG_TX|DBG_BUS, "(start multi region)"); 1163 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT; 1164 tx_bytes = MAX_TRANSFER_COUNT; 1165 } 1166 } else { 1167 // tx_regions == 0 1168 // that's all folks - end of frame 1169 struct sk_buff * skb = dev->tx_skb; 1170 dev->tx_iovec = NULL; 1171 1172 // VC layer stats 1173 atomic_inc(&ATM_SKB(skb)->vcc->stats->tx); 1174 1175 // free the skb 1176 hrz_kfree_skb (skb); 1177 } 1178 } 1179 1180 // note: writing TX_COUNT clears any interrupt condition 1181 if (tx_bytes) { 1182 if (pio_instead) { 1183 if (irq) 1184 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0); 1185 wrs_regb (dev, DATA_PORT_OFF, dev->tx_addr, tx_bytes); 1186 if (append_desc) 1187 wr_regl (dev, TX_DESCRIPTOR_PORT_OFF, cpu_to_be32 (dev->tx_skb->len)); 1188 } else { 1189 wr_regl (dev, MASTER_TX_ADDR_REG_OFF, virt_to_bus (dev->tx_addr)); 1190 if (append_desc) 1191 wr_regl (dev, TX_DESCRIPTOR_REG_OFF, cpu_to_be32 (dev->tx_skb->len)); 1192 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 1193 append_desc 1194 ? tx_bytes | MASTER_TX_AUTO_APPEND_DESC 1195 : tx_bytes); 1196 } 1197 dev->tx_addr += tx_bytes; 1198 } else { 1199 if (irq) 1200 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0); 1201 YELLOW_LED_ON(dev); 1202 tx_release (dev); 1203 } 1204 1205#ifdef TAILRECURSIONWORKS 1206 // and we all bless optimised tail calls 1207 if (pio_instead) 1208 return tx_schedule (dev, 0); 1209 return; 1210#else 1211 // grrrrrrr! 1212 irq = 0; 1213 } 1214 return; 1215#endif 1216} 1217 1218/********** handle TX bus master complete events **********/ 1219 1220static void tx_bus_master_complete_handler (hrz_dev * dev) { 1221 if (test_bit (tx_busy, &dev->flags)) { 1222 tx_schedule (dev, 1); 1223 } else { 1224 PRINTD (DBG_TX|DBG_ERR, "unexpected TX bus master completion"); 1225 // clear interrupt condition on adapter 1226 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0); 1227 } 1228 return; 1229} 1230 1231/********** move RX Q pointer to next item in circular buffer **********/ 1232 1233// called only from IRQ sub-handler 1234static u32 rx_queue_entry_next (hrz_dev * dev) { 1235 u32 rx_queue_entry; 1236 spin_lock (&dev->mem_lock); 1237 rx_queue_entry = rd_mem (dev, &dev->rx_q_entry->entry); 1238 if (dev->rx_q_entry == dev->rx_q_wrap) 1239 dev->rx_q_entry = dev->rx_q_reset; 1240 else 1241 dev->rx_q_entry++; 1242 wr_regw (dev, RX_QUEUE_RD_PTR_OFF, dev->rx_q_entry - dev->rx_q_reset); 1243 spin_unlock (&dev->mem_lock); 1244 return rx_queue_entry; 1245} 1246 1247/********** handle RX data received by device **********/ 1248 1249// called from IRQ handler 1250static void rx_data_av_handler (hrz_dev * dev) { 1251 u32 rx_queue_entry; 1252 u32 rx_queue_entry_flags; 1253 u16 rx_len; 1254 u16 rx_channel; 1255 1256 PRINTD (DBG_FLOW, "hrz_data_av_handler"); 1257 1258 // try to grab rx lock (not possible during RX bus mastering) 1259 if (test_and_set_bit (rx_busy, &dev->flags)) { 1260 PRINTD (DBG_RX, "locked out of rx lock"); 1261 return; 1262 } 1263 PRINTD (DBG_RX, "set rx_busy for dev %p", dev); 1264 // lock is cleared if we fail now, o/w after bus master completion 1265 1266 YELLOW_LED_OFF(dev); 1267 1268 rx_queue_entry = rx_queue_entry_next (dev); 1269 1270 rx_len = rx_q_entry_to_length (rx_queue_entry); 1271 rx_channel = rx_q_entry_to_rx_channel (rx_queue_entry); 1272 1273 WAIT_FLUSH_RX_COMPLETE (dev); 1274 1275 SELECT_RX_CHANNEL (dev, rx_channel); 1276 1277 PRINTD (DBG_RX, "rx_queue_entry is: %#x", rx_queue_entry); 1278 rx_queue_entry_flags = rx_queue_entry & (RX_CRC_32_OK|RX_COMPLETE_FRAME|SIMONS_DODGEY_MARKER); 1279 1280 if (!rx_len) { 1281 // (at least) bus-mastering breaks if we try to handle a 1282 // zero-length frame, besides AAL5 does not support them 1283 PRINTK (KERN_ERR, "zero-length frame!"); 1284 rx_queue_entry_flags &= ~RX_COMPLETE_FRAME; 1285 } 1286 1287 if (rx_queue_entry_flags & SIMONS_DODGEY_MARKER) { 1288 PRINTD (DBG_RX|DBG_ERR, "Simon's marker detected!"); 1289 } 1290 if (rx_queue_entry_flags == (RX_CRC_32_OK | RX_COMPLETE_FRAME)) { 1291 struct atm_vcc * atm_vcc; 1292 1293 PRINTD (DBG_RX, "got a frame on rx_channel %x len %u", rx_channel, rx_len); 1294 1295 atm_vcc = dev->rxer[rx_channel]; 1296 // if no vcc is assigned to this channel, we should drop the frame 1297 // (is this what SIMONS etc. was trying to achieve?) 1298 1299 if (atm_vcc) { 1300 1301 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) { 1302 1303 if (rx_len <= atm_vcc->qos.rxtp.max_sdu) { 1304 1305 struct sk_buff * skb = atm_alloc_charge (atm_vcc, rx_len, GFP_ATOMIC); 1306 if (skb) { 1307 // remember this so we can push it later 1308 dev->rx_skb = skb; 1309 // remember this so we can flush it later 1310 dev->rx_channel = rx_channel; 1311 1312 // prepare socket buffer 1313 skb_put (skb, rx_len); 1314 ATM_SKB(skb)->vcc = atm_vcc; 1315 1316 // simple transfer 1317 // dev->rx_regions = 0; 1318 // dev->rx_iovec = 0; 1319 dev->rx_bytes = rx_len; 1320 dev->rx_addr = skb->data; 1321 PRINTD (DBG_RX, "RX start simple transfer (addr %p, len %d)", 1322 skb->data, rx_len); 1323 1324 // do the business 1325 rx_schedule (dev, 0); 1326 return; 1327 1328 } else { 1329 PRINTD (DBG_SKB|DBG_WARN, "failed to get skb"); 1330 } 1331 1332 } else { 1333 PRINTK (KERN_INFO, "frame received on TX-only VC %x", rx_channel); 1334 // do we count this? 1335 } 1336 1337 } else { 1338 PRINTK (KERN_WARNING, "dropped over-size frame"); 1339 // do we count this? 1340 } 1341 1342 } else { 1343 PRINTD (DBG_WARN|DBG_VCC|DBG_RX, "no VCC for this frame (VC closed)"); 1344 // do we count this? 1345 } 1346 1347 } else { 1348 // Wait update complete ? SPONG 1349 } 1350 1351 // RX was aborted 1352 YELLOW_LED_ON(dev); 1353 1354 FLUSH_RX_CHANNEL (dev,rx_channel); 1355 clear_bit (rx_busy, &dev->flags); 1356 1357 return; 1358} 1359 1360/********** interrupt handler **********/ 1361 1362static irqreturn_t interrupt_handler(int irq, void *dev_id) 1363{ 1364 hrz_dev *dev = dev_id; 1365 u32 int_source; 1366 unsigned int irq_ok; 1367 1368 PRINTD (DBG_FLOW, "interrupt_handler: %p", dev_id); 1369 1370 // definitely for us 1371 irq_ok = 0; 1372 while ((int_source = rd_regl (dev, INT_SOURCE_REG_OFF) 1373 & INTERESTING_INTERRUPTS)) { 1374 // In the interests of fairness, the handlers below are 1375 // called in sequence and without immediate return to the head of 1376 // the while loop. This is only of issue for slow hosts (or when 1377 // debugging messages are on). Really slow hosts may find a fast 1378 // sender keeps them permanently in the IRQ handler. :( 1379 1380 // (only an issue for slow hosts) RX completion goes before 1381 // rx_data_av as the former implies rx_busy and so the latter 1382 // would just abort. If it reschedules another transfer 1383 // (continuing the same frame) then it will not clear rx_busy. 1384 1385 // (only an issue for slow hosts) TX completion goes before RX 1386 // data available as it is a much shorter routine - there is the 1387 // chance that any further transfers it schedules will be complete 1388 // by the time of the return to the head of the while loop 1389 1390 if (int_source & RX_BUS_MASTER_COMPLETE) { 1391 ++irq_ok; 1392 PRINTD (DBG_IRQ|DBG_BUS|DBG_RX, "rx_bus_master_complete asserted"); 1393 rx_bus_master_complete_handler (dev); 1394 } 1395 if (int_source & TX_BUS_MASTER_COMPLETE) { 1396 ++irq_ok; 1397 PRINTD (DBG_IRQ|DBG_BUS|DBG_TX, "tx_bus_master_complete asserted"); 1398 tx_bus_master_complete_handler (dev); 1399 } 1400 if (int_source & RX_DATA_AV) { 1401 ++irq_ok; 1402 PRINTD (DBG_IRQ|DBG_RX, "rx_data_av asserted"); 1403 rx_data_av_handler (dev); 1404 } 1405 } 1406 if (irq_ok) { 1407 PRINTD (DBG_IRQ, "work done: %u", irq_ok); 1408 } else { 1409 PRINTD (DBG_IRQ|DBG_WARN, "spurious interrupt source: %#x", int_source); 1410 } 1411 1412 PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler done: %p", dev_id); 1413 if (irq_ok) 1414 return IRQ_HANDLED; 1415 return IRQ_NONE; 1416} 1417 1418/********** housekeeping **********/ 1419 1420static void do_housekeeping (unsigned long arg) { 1421 // just stats at the moment 1422 hrz_dev * dev = (hrz_dev *) arg; 1423 1424 // collect device-specific (not driver/atm-linux) stats here 1425 dev->tx_cell_count += rd_regw (dev, TX_CELL_COUNT_OFF); 1426 dev->rx_cell_count += rd_regw (dev, RX_CELL_COUNT_OFF); 1427 dev->hec_error_count += rd_regw (dev, HEC_ERROR_COUNT_OFF); 1428 dev->unassigned_cell_count += rd_regw (dev, UNASSIGNED_CELL_COUNT_OFF); 1429 1430 mod_timer (&dev->housekeeping, jiffies + HZ/10); 1431 1432 return; 1433} 1434 1435/********** find an idle channel for TX and set it up **********/ 1436 1437// called with tx_busy set 1438static short setup_idle_tx_channel (hrz_dev * dev, hrz_vcc * vcc) { 1439 unsigned short idle_channels; 1440 short tx_channel = -1; 1441 unsigned int spin_count; 1442 PRINTD (DBG_FLOW|DBG_TX, "setup_idle_tx_channel %p", dev); 1443 1444 // better would be to fail immediately, the caller can then decide whether 1445 // to wait or drop (depending on whether this is UBR etc.) 1446 spin_count = 0; 1447 while (!(idle_channels = rd_regw (dev, TX_STATUS_OFF) & IDLE_CHANNELS_MASK)) { 1448 PRINTD (DBG_TX|DBG_WARN, "waiting for idle TX channel"); 1449 // delay a bit here 1450 if (++spin_count > 100) { 1451 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for idle TX channel"); 1452 return -EBUSY; 1453 } 1454 } 1455 1456 // got an idle channel 1457 { 1458 // tx_idle ensures we look for idle channels in RR order 1459 int chan = dev->tx_idle; 1460 1461 int keep_going = 1; 1462 while (keep_going) { 1463 if (idle_channels & (1<<chan)) { 1464 tx_channel = chan; 1465 keep_going = 0; 1466 } 1467 ++chan; 1468 if (chan == TX_CHANS) 1469 chan = 0; 1470 } 1471 1472 dev->tx_idle = chan; 1473 } 1474 1475 // set up the channel we found 1476 { 1477 // Initialise the cell header in the transmit channel descriptor 1478 // a.k.a. prepare the channel and remember that we have done so. 1479 1480 tx_ch_desc * tx_desc = &memmap->tx_descs[tx_channel]; 1481 u32 rd_ptr; 1482 u32 wr_ptr; 1483 u16 channel = vcc->channel; 1484 1485 unsigned long flags; 1486 spin_lock_irqsave (&dev->mem_lock, flags); 1487 1488 // Update the transmit channel record. 1489 dev->tx_channel_record[tx_channel] = channel; 1490 1491 // xBR channel 1492 update_tx_channel_config (dev, tx_channel, RATE_TYPE_ACCESS, 1493 vcc->tx_xbr_bits); 1494 1495 // Update the PCR counter preload value etc. 1496 update_tx_channel_config (dev, tx_channel, PCR_TIMER_ACCESS, 1497 vcc->tx_pcr_bits); 1498 1499#if 0 1500 if (vcc->tx_xbr_bits == VBR_RATE_TYPE) { 1501 // SCR timer 1502 update_tx_channel_config (dev, tx_channel, SCR_TIMER_ACCESS, 1503 vcc->tx_scr_bits); 1504 1505 // Bucket size... 1506 update_tx_channel_config (dev, tx_channel, BUCKET_CAPACITY_ACCESS, 1507 vcc->tx_bucket_bits); 1508 1509 // ... and fullness 1510 update_tx_channel_config (dev, tx_channel, BUCKET_FULLNESS_ACCESS, 1511 vcc->tx_bucket_bits); 1512 } 1513#endif 1514 1515 // Initialise the read and write buffer pointers 1516 rd_ptr = rd_mem (dev, &tx_desc->rd_buf_type) & BUFFER_PTR_MASK; 1517 wr_ptr = rd_mem (dev, &tx_desc->wr_buf_type) & BUFFER_PTR_MASK; 1518 1519 // idle TX channels should have identical pointers 1520 if (rd_ptr != wr_ptr) { 1521 PRINTD (DBG_TX|DBG_ERR, "TX buffer pointers are broken!"); 1522 // spin_unlock... return -E... 1523 // I wonder if gcc would get rid of one of the pointer aliases 1524 } 1525 PRINTD (DBG_TX, "TX buffer pointers are: rd %x, wr %x.", 1526 rd_ptr, wr_ptr); 1527 1528 switch (vcc->aal) { 1529 case aal0: 1530 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal0"); 1531 rd_ptr |= CHANNEL_TYPE_RAW_CELLS; 1532 wr_ptr |= CHANNEL_TYPE_RAW_CELLS; 1533 break; 1534 case aal34: 1535 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal34"); 1536 rd_ptr |= CHANNEL_TYPE_AAL3_4; 1537 wr_ptr |= CHANNEL_TYPE_AAL3_4; 1538 break; 1539 case aal5: 1540 rd_ptr |= CHANNEL_TYPE_AAL5; 1541 wr_ptr |= CHANNEL_TYPE_AAL5; 1542 // Initialise the CRC 1543 wr_mem (dev, &tx_desc->partial_crc, INITIAL_CRC); 1544 break; 1545 } 1546 1547 wr_mem (dev, &tx_desc->rd_buf_type, rd_ptr); 1548 wr_mem (dev, &tx_desc->wr_buf_type, wr_ptr); 1549 1550 // Write the Cell Header 1551 // Payload Type, CLP and GFC would go here if non-zero 1552 wr_mem (dev, &tx_desc->cell_header, channel); 1553 1554 spin_unlock_irqrestore (&dev->mem_lock, flags); 1555 } 1556 1557 return tx_channel; 1558} 1559 1560/********** send a frame **********/ 1561 1562static int hrz_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) { 1563 unsigned int spin_count; 1564 int free_buffers; 1565 hrz_dev * dev = HRZ_DEV(atm_vcc->dev); 1566 hrz_vcc * vcc = HRZ_VCC(atm_vcc); 1567 u16 channel = vcc->channel; 1568 1569 u32 buffers_required; 1570 1571 /* signed for error return */ 1572 short tx_channel; 1573 1574 PRINTD (DBG_FLOW|DBG_TX, "hrz_send vc %x data %p len %u", 1575 channel, skb->data, skb->len); 1576 1577 dump_skb (">>>", channel, skb); 1578 1579 if (atm_vcc->qos.txtp.traffic_class == ATM_NONE) { 1580 PRINTK (KERN_ERR, "attempt to send on RX-only VC %x", channel); 1581 hrz_kfree_skb (skb); 1582 return -EIO; 1583 } 1584 1585 // don't understand this 1586 ATM_SKB(skb)->vcc = atm_vcc; 1587 1588 if (skb->len > atm_vcc->qos.txtp.max_sdu) { 1589 PRINTK (KERN_ERR, "sk_buff length greater than agreed max_sdu, dropping..."); 1590 hrz_kfree_skb (skb); 1591 return -EIO; 1592 } 1593 1594 if (!channel) { 1595 PRINTD (DBG_ERR|DBG_TX, "attempt to transmit on zero (rx_)channel"); 1596 hrz_kfree_skb (skb); 1597 return -EIO; 1598 } 1599 1600#if 0 1601 { 1602 // where would be a better place for this? housekeeping? 1603 u16 status; 1604 pci_read_config_word (dev->pci_dev, PCI_STATUS, &status); 1605 if (status & PCI_STATUS_REC_MASTER_ABORT) { 1606 PRINTD (DBG_BUS|DBG_ERR, "Clearing PCI Master Abort (and cleaning up)"); 1607 status &= ~PCI_STATUS_REC_MASTER_ABORT; 1608 pci_write_config_word (dev->pci_dev, PCI_STATUS, status); 1609 if (test_bit (tx_busy, &dev->flags)) { 1610 hrz_kfree_skb (dev->tx_skb); 1611 tx_release (dev); 1612 } 1613 } 1614 } 1615#endif 1616 1617#ifdef DEBUG_HORIZON 1618 /* wey-hey! */ 1619 if (channel == 1023) { 1620 unsigned int i; 1621 unsigned short d = 0; 1622 char * s = skb->data; 1623 if (*s++ == 'D') { 1624 for (i = 0; i < 4; ++i) 1625 d = (d << 4) | hex_to_bin(*s++); 1626 PRINTK (KERN_INFO, "debug bitmap is now %hx", debug = d); 1627 } 1628 } 1629#endif 1630 1631 // wait until TX is free and grab lock 1632 if (tx_hold (dev)) { 1633 hrz_kfree_skb (skb); 1634 return -ERESTARTSYS; 1635 } 1636 1637 // Wait for enough space to be available in transmit buffer memory. 1638 1639 // should be number of cells needed + 2 (according to hardware docs) 1640 // = ((framelen+8)+47) / 48 + 2 1641 // = (framelen+7) / 48 + 3, hmm... faster to put addition inside XXX 1642 buffers_required = (skb->len+(ATM_AAL5_TRAILER-1)) / ATM_CELL_PAYLOAD + 3; 1643 1644 // replace with timer and sleep, add dev->tx_buffers_queue (max 1 entry) 1645 spin_count = 0; 1646 while ((free_buffers = rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF)) < buffers_required) { 1647 PRINTD (DBG_TX, "waiting for free TX buffers, got %d of %d", 1648 free_buffers, buffers_required); 1649 // what is the appropriate delay? implement a timeout? (depending on line speed?) 1650 // mdelay (1); 1651 // what happens if we kill (current_pid, SIGKILL) ? 1652 schedule(); 1653 if (++spin_count > 1000) { 1654 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for tx buffers, got %d of %d", 1655 free_buffers, buffers_required); 1656 tx_release (dev); 1657 hrz_kfree_skb (skb); 1658 return -ERESTARTSYS; 1659 } 1660 } 1661 1662 // Select a channel to transmit the frame on. 1663 if (channel == dev->last_vc) { 1664 PRINTD (DBG_TX, "last vc hack: hit"); 1665 tx_channel = dev->tx_last; 1666 } else { 1667 PRINTD (DBG_TX, "last vc hack: miss"); 1668 // Are we currently transmitting this VC on one of the channels? 1669 for (tx_channel = 0; tx_channel < TX_CHANS; ++tx_channel) 1670 if (dev->tx_channel_record[tx_channel] == channel) { 1671 PRINTD (DBG_TX, "vc already on channel: hit"); 1672 break; 1673 } 1674 if (tx_channel == TX_CHANS) { 1675 PRINTD (DBG_TX, "vc already on channel: miss"); 1676 // Find and set up an idle channel. 1677 tx_channel = setup_idle_tx_channel (dev, vcc); 1678 if (tx_channel < 0) { 1679 PRINTD (DBG_TX|DBG_ERR, "failed to get channel"); 1680 tx_release (dev); 1681 return tx_channel; 1682 } 1683 } 1684 1685 PRINTD (DBG_TX, "got channel"); 1686 SELECT_TX_CHANNEL(dev, tx_channel); 1687 1688 dev->last_vc = channel; 1689 dev->tx_last = tx_channel; 1690 } 1691 1692 PRINTD (DBG_TX, "using channel %u", tx_channel); 1693 1694 YELLOW_LED_OFF(dev); 1695 1696 // TX start transfer 1697 1698 { 1699 unsigned int tx_len = skb->len; 1700 unsigned int tx_iovcnt = skb_shinfo(skb)->nr_frags; 1701 // remember this so we can free it later 1702 dev->tx_skb = skb; 1703 1704 if (tx_iovcnt) { 1705 // scatter gather transfer 1706 dev->tx_regions = tx_iovcnt; 1707 dev->tx_iovec = NULL; /* @@@ needs rewritten */ 1708 dev->tx_bytes = 0; 1709 PRINTD (DBG_TX|DBG_BUS, "TX start scatter-gather transfer (iovec %p, len %d)", 1710 skb->data, tx_len); 1711 tx_release (dev); 1712 hrz_kfree_skb (skb); 1713 return -EIO; 1714 } else { 1715 // simple transfer 1716 dev->tx_regions = 0; 1717 dev->tx_iovec = NULL; 1718 dev->tx_bytes = tx_len; 1719 dev->tx_addr = skb->data; 1720 PRINTD (DBG_TX|DBG_BUS, "TX start simple transfer (addr %p, len %d)", 1721 skb->data, tx_len); 1722 } 1723 1724 // and do the business 1725 tx_schedule (dev, 0); 1726 1727 } 1728 1729 return 0; 1730} 1731 1732/********** reset a card **********/ 1733 1734static void hrz_reset (const hrz_dev * dev) { 1735 u32 control_0_reg = rd_regl (dev, CONTROL_0_REG); 1736 1737 // why not set RESET_HORIZON to one and wait for the card to 1738 // reassert that bit as zero? Like so: 1739 control_0_reg = control_0_reg & RESET_HORIZON; 1740 wr_regl (dev, CONTROL_0_REG, control_0_reg); 1741 while (control_0_reg & RESET_HORIZON) 1742 control_0_reg = rd_regl (dev, CONTROL_0_REG); 1743 1744 // old reset code retained: 1745 wr_regl (dev, CONTROL_0_REG, control_0_reg | 1746 RESET_ATM | RESET_RX | RESET_TX | RESET_HOST); 1747 // just guessing here 1748 udelay (1000); 1749 1750 wr_regl (dev, CONTROL_0_REG, control_0_reg); 1751} 1752 1753/********** read the burnt in address **********/ 1754 1755static void WRITE_IT_WAIT (const hrz_dev *dev, u32 ctrl) 1756{ 1757 wr_regl (dev, CONTROL_0_REG, ctrl); 1758 udelay (5); 1759} 1760 1761static void CLOCK_IT (const hrz_dev *dev, u32 ctrl) 1762{ 1763 // DI must be valid around rising SK edge 1764 WRITE_IT_WAIT(dev, ctrl & ~SEEPROM_SK); 1765 WRITE_IT_WAIT(dev, ctrl | SEEPROM_SK); 1766} 1767 1768static u16 read_bia(const hrz_dev *dev, u16 addr) 1769{ 1770 u32 ctrl = rd_regl (dev, CONTROL_0_REG); 1771 1772 const unsigned int addr_bits = 6; 1773 const unsigned int data_bits = 16; 1774 1775 unsigned int i; 1776 1777 u16 res; 1778 1779 ctrl &= ~(SEEPROM_CS | SEEPROM_SK | SEEPROM_DI); 1780 WRITE_IT_WAIT(dev, ctrl); 1781 1782 // wake Serial EEPROM and send 110 (READ) command 1783 ctrl |= (SEEPROM_CS | SEEPROM_DI); 1784 CLOCK_IT(dev, ctrl); 1785 1786 ctrl |= SEEPROM_DI; 1787 CLOCK_IT(dev, ctrl); 1788 1789 ctrl &= ~SEEPROM_DI; 1790 CLOCK_IT(dev, ctrl); 1791 1792 for (i=0; i<addr_bits; i++) { 1793 if (addr & (1 << (addr_bits-1))) 1794 ctrl |= SEEPROM_DI; 1795 else 1796 ctrl &= ~SEEPROM_DI; 1797 1798 CLOCK_IT(dev, ctrl); 1799 1800 addr = addr << 1; 1801 } 1802 1803 // we could check that we have DO = 0 here 1804 ctrl &= ~SEEPROM_DI; 1805 1806 res = 0; 1807 for (i=0;i<data_bits;i++) { 1808 res = res >> 1; 1809 1810 CLOCK_IT(dev, ctrl); 1811 1812 if (rd_regl (dev, CONTROL_0_REG) & SEEPROM_DO) 1813 res |= (1 << (data_bits-1)); 1814 } 1815 1816 ctrl &= ~(SEEPROM_SK | SEEPROM_CS); 1817 WRITE_IT_WAIT(dev, ctrl); 1818 1819 return res; 1820} 1821 1822/********** initialise a card **********/ 1823 1824static int hrz_init(hrz_dev *dev) 1825{ 1826 int onefivefive; 1827 1828 u16 chan; 1829 1830 int buff_count; 1831 1832 HDW * mem; 1833 1834 cell_buf * tx_desc; 1835 cell_buf * rx_desc; 1836 1837 u32 ctrl; 1838 1839 ctrl = rd_regl (dev, CONTROL_0_REG); 1840 PRINTD (DBG_INFO, "ctrl0reg is %#x", ctrl); 1841 onefivefive = ctrl & ATM_LAYER_STATUS; 1842 1843 if (onefivefive) 1844 printk (DEV_LABEL ": Horizon Ultra (at 155.52 MBps)"); 1845 else 1846 printk (DEV_LABEL ": Horizon (at 25 MBps)"); 1847 1848 printk (":"); 1849 // Reset the card to get everything in a known state 1850 1851 printk (" reset"); 1852 hrz_reset (dev); 1853 1854 // Clear all the buffer memory 1855 1856 printk (" clearing memory"); 1857 1858 for (mem = (HDW *) memmap; mem < (HDW *) (memmap + 1); ++mem) 1859 wr_mem (dev, mem, 0); 1860 1861 printk (" tx channels"); 1862 1863 // All transmit eight channels are set up as AAL5 ABR channels with 1864 // a 16us cell spacing. Why? 1865 1866 // Channel 0 gets the free buffer at 100h, channel 1 gets the free 1867 // buffer at 110h etc. 1868 1869 for (chan = 0; chan < TX_CHANS; ++chan) { 1870 tx_ch_desc * tx_desc = &memmap->tx_descs[chan]; 1871 cell_buf * buf = &memmap->inittxbufs[chan]; 1872 1873 // initialise the read and write buffer pointers 1874 wr_mem (dev, &tx_desc->rd_buf_type, BUF_PTR(buf)); 1875 wr_mem (dev, &tx_desc->wr_buf_type, BUF_PTR(buf)); 1876 1877 // set the status of the initial buffers to empty 1878 wr_mem (dev, &buf->next, BUFF_STATUS_EMPTY); 1879 } 1880 1881 // Use space bufn3 at the moment for tx buffers 1882 1883 printk (" tx buffers"); 1884 1885 tx_desc = memmap->bufn3; 1886 1887 wr_mem (dev, &memmap->txfreebufstart.next, BUF_PTR(tx_desc) | BUFF_STATUS_EMPTY); 1888 1889 for (buff_count = 0; buff_count < BUFN3_SIZE-1; buff_count++) { 1890 wr_mem (dev, &tx_desc->next, BUF_PTR(tx_desc+1) | BUFF_STATUS_EMPTY); 1891 tx_desc++; 1892 } 1893 1894 wr_mem (dev, &tx_desc->next, BUF_PTR(&memmap->txfreebufend) | BUFF_STATUS_EMPTY); 1895 1896 // Initialise the transmit free buffer count 1897 wr_regw (dev, TX_FREE_BUFFER_COUNT_OFF, BUFN3_SIZE); 1898 1899 printk (" rx channels"); 1900 1901 // Initialise all of the receive channels to be AAL5 disabled with 1902 // an interrupt threshold of 0 1903 1904 for (chan = 0; chan < RX_CHANS; ++chan) { 1905 rx_ch_desc * rx_desc = &memmap->rx_descs[chan]; 1906 1907 wr_mem (dev, &rx_desc->wr_buf_type, CHANNEL_TYPE_AAL5 | RX_CHANNEL_DISABLED); 1908 } 1909 1910 printk (" rx buffers"); 1911 1912 // Use space bufn4 at the moment for rx buffers 1913 1914 rx_desc = memmap->bufn4; 1915 1916 wr_mem (dev, &memmap->rxfreebufstart.next, BUF_PTR(rx_desc) | BUFF_STATUS_EMPTY); 1917 1918 for (buff_count = 0; buff_count < BUFN4_SIZE-1; buff_count++) { 1919 wr_mem (dev, &rx_desc->next, BUF_PTR(rx_desc+1) | BUFF_STATUS_EMPTY); 1920 1921 rx_desc++; 1922 } 1923 1924 wr_mem (dev, &rx_desc->next, BUF_PTR(&memmap->rxfreebufend) | BUFF_STATUS_EMPTY); 1925 1926 // Initialise the receive free buffer count 1927 wr_regw (dev, RX_FREE_BUFFER_COUNT_OFF, BUFN4_SIZE); 1928 1929 // Initialize Horizons registers 1930 1931 // TX config 1932 wr_regw (dev, TX_CONFIG_OFF, 1933 ABR_ROUND_ROBIN | TX_NORMAL_OPERATION | DRVR_DRVRBAR_ENABLE); 1934 1935 // RX config. Use 10-x VC bits, x VP bits, non user cells in channel 0. 1936 wr_regw (dev, RX_CONFIG_OFF, 1937 DISCARD_UNUSED_VPI_VCI_BITS_SET | NON_USER_CELLS_IN_ONE_CHANNEL | vpi_bits); 1938 1939 // RX line config 1940 wr_regw (dev, RX_LINE_CONFIG_OFF, 1941 LOCK_DETECT_ENABLE | FREQUENCY_DETECT_ENABLE | GXTALOUT_SELECT_DIV4); 1942 1943 // Set the max AAL5 cell count to be just enough to contain the 1944 // largest AAL5 frame that the user wants to receive 1945 wr_regw (dev, MAX_AAL5_CELL_COUNT_OFF, 1946 DIV_ROUND_UP(max_rx_size + ATM_AAL5_TRAILER, ATM_CELL_PAYLOAD)); 1947 1948 // Enable receive 1949 wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE); 1950 1951 printk (" control"); 1952 1953 // Drive the OE of the LEDs then turn the green LED on 1954 ctrl |= GREEN_LED_OE | YELLOW_LED_OE | GREEN_LED | YELLOW_LED; 1955 wr_regl (dev, CONTROL_0_REG, ctrl); 1956 1957 // Test for a 155-capable card 1958 1959 if (onefivefive) { 1960 // Select 155 mode... make this a choice (or: how do we detect 1961 // external line speed and switch?) 1962 ctrl |= ATM_LAYER_SELECT; 1963 wr_regl (dev, CONTROL_0_REG, ctrl); 1964 1965 // test SUNI-lite vs SAMBA 1966 1967 // Register 0x00 in the SUNI will have some of bits 3-7 set, and 1968 // they will always be zero for the SAMBA. Ha! Bloody hardware 1969 // engineers. It'll never work. 1970 1971 if (rd_framer (dev, 0) & 0x00f0) { 1972 // SUNI 1973 printk (" SUNI"); 1974 1975 // Reset, just in case 1976 wr_framer (dev, 0x00, 0x0080); 1977 wr_framer (dev, 0x00, 0x0000); 1978 1979 // Configure transmit FIFO 1980 wr_framer (dev, 0x63, rd_framer (dev, 0x63) | 0x0002); 1981 1982 // Set line timed mode 1983 wr_framer (dev, 0x05, rd_framer (dev, 0x05) | 0x0001); 1984 } else { 1985 // SAMBA 1986 printk (" SAMBA"); 1987 1988 // Reset, just in case 1989 wr_framer (dev, 0, rd_framer (dev, 0) | 0x0001); 1990 wr_framer (dev, 0, rd_framer (dev, 0) &~ 0x0001); 1991 1992 // Turn off diagnostic loopback and enable line-timed mode 1993 wr_framer (dev, 0, 0x0002); 1994 1995 // Turn on transmit outputs 1996 wr_framer (dev, 2, 0x0B80); 1997 } 1998 } else { 1999 // Select 25 mode 2000 ctrl &= ~ATM_LAYER_SELECT; 2001 2002 // Madge B154 setup 2003 // none required? 2004 } 2005 2006 printk (" LEDs"); 2007 2008 GREEN_LED_ON(dev); 2009 YELLOW_LED_ON(dev); 2010 2011 printk (" ESI="); 2012 2013 { 2014 u16 b = 0; 2015 int i; 2016 u8 * esi = dev->atm_dev->esi; 2017 2018 // in the card I have, EEPROM 2019 // addresses 0, 1, 2 contain 0 2020 // addresess 5, 6 etc. contain ffff 2021 // NB: Madge prefix is 00 00 f6 (which is 00 00 6f in Ethernet bit order) 2022 // the read_bia routine gets the BIA in Ethernet bit order 2023 2024 for (i=0; i < ESI_LEN; ++i) { 2025 if (i % 2 == 0) 2026 b = read_bia (dev, i/2 + 2); 2027 else 2028 b = b >> 8; 2029 esi[i] = b & 0xFF; 2030 printk ("%02x", esi[i]); 2031 } 2032 } 2033 2034 // Enable RX_Q and ?X_COMPLETE interrupts only 2035 wr_regl (dev, INT_ENABLE_REG_OFF, INTERESTING_INTERRUPTS); 2036 printk (" IRQ on"); 2037 2038 printk (".\n"); 2039 2040 return onefivefive; 2041} 2042 2043/********** check max_sdu **********/ 2044 2045static int check_max_sdu (hrz_aal aal, struct atm_trafprm * tp, unsigned int max_frame_size) { 2046 PRINTD (DBG_FLOW|DBG_QOS, "check_max_sdu"); 2047 2048 switch (aal) { 2049 case aal0: 2050 if (!(tp->max_sdu)) { 2051 PRINTD (DBG_QOS, "defaulting max_sdu"); 2052 tp->max_sdu = ATM_AAL0_SDU; 2053 } else if (tp->max_sdu != ATM_AAL0_SDU) { 2054 PRINTD (DBG_QOS|DBG_ERR, "rejecting max_sdu"); 2055 return -EINVAL; 2056 } 2057 break; 2058 case aal34: 2059 if (tp->max_sdu == 0 || tp->max_sdu > ATM_MAX_AAL34_PDU) { 2060 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default"); 2061 tp->max_sdu = ATM_MAX_AAL34_PDU; 2062 } 2063 break; 2064 case aal5: 2065 if (tp->max_sdu == 0 || tp->max_sdu > max_frame_size) { 2066 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default"); 2067 tp->max_sdu = max_frame_size; 2068 } 2069 break; 2070 } 2071 return 0; 2072} 2073 2074/********** check pcr **********/ 2075 2076// something like this should be part of ATM Linux 2077static int atm_pcr_check (struct atm_trafprm * tp, unsigned int pcr) { 2078 // we are assuming non-UBR, and non-special values of pcr 2079 if (tp->min_pcr == ATM_MAX_PCR) 2080 PRINTD (DBG_QOS, "luser gave min_pcr = ATM_MAX_PCR"); 2081 else if (tp->min_pcr < 0) 2082 PRINTD (DBG_QOS, "luser gave negative min_pcr"); 2083 else if (tp->min_pcr && tp->min_pcr > pcr) 2084 PRINTD (DBG_QOS, "pcr less than min_pcr"); 2085 else 2086 // !! max_pcr = UNSPEC (0) is equivalent to max_pcr = MAX (-1) 2087 // easier to #define ATM_MAX_PCR 0 and have all rates unsigned? 2088 // [this would get rid of next two conditionals] 2089 if ((0) && tp->max_pcr == ATM_MAX_PCR) 2090 PRINTD (DBG_QOS, "luser gave max_pcr = ATM_MAX_PCR"); 2091 else if ((tp->max_pcr != ATM_MAX_PCR) && tp->max_pcr < 0) 2092 PRINTD (DBG_QOS, "luser gave negative max_pcr"); 2093 else if (tp->max_pcr && tp->max_pcr != ATM_MAX_PCR && tp->max_pcr < pcr) 2094 PRINTD (DBG_QOS, "pcr greater than max_pcr"); 2095 else { 2096 // each limit unspecified or not violated 2097 PRINTD (DBG_QOS, "xBR(pcr) OK"); 2098 return 0; 2099 } 2100 PRINTD (DBG_QOS, "pcr=%u, tp: min_pcr=%d, pcr=%d, max_pcr=%d", 2101 pcr, tp->min_pcr, tp->pcr, tp->max_pcr); 2102 return -EINVAL; 2103} 2104 2105/********** open VC **********/ 2106 2107static int hrz_open (struct atm_vcc *atm_vcc) 2108{ 2109 int error; 2110 u16 channel; 2111 2112 struct atm_qos * qos; 2113 struct atm_trafprm * txtp; 2114 struct atm_trafprm * rxtp; 2115 2116 hrz_dev * dev = HRZ_DEV(atm_vcc->dev); 2117 hrz_vcc vcc; 2118 hrz_vcc * vccp; // allocated late 2119 short vpi = atm_vcc->vpi; 2120 int vci = atm_vcc->vci; 2121 PRINTD (DBG_FLOW|DBG_VCC, "hrz_open %x %x", vpi, vci); 2122 2123#ifdef ATM_VPI_UNSPEC 2124 // UNSPEC is deprecated, remove this code eventually 2125 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) { 2126 PRINTK (KERN_WARNING, "rejecting open with unspecified VPI/VCI (deprecated)"); 2127 return -EINVAL; 2128 } 2129#endif 2130 2131 error = vpivci_to_channel (&channel, vpi, vci); 2132 if (error) { 2133 PRINTD (DBG_WARN|DBG_VCC, "VPI/VCI out of range: %hd/%d", vpi, vci); 2134 return error; 2135 } 2136 2137 vcc.channel = channel; 2138 // max speed for the moment 2139 vcc.tx_rate = 0x0; 2140 2141 qos = &atm_vcc->qos; 2142 2143 // check AAL and remember it 2144 switch (qos->aal) { 2145 case ATM_AAL0: 2146 // we would if it were 48 bytes and not 52! 2147 PRINTD (DBG_QOS|DBG_VCC, "AAL0"); 2148 vcc.aal = aal0; 2149 break; 2150 case ATM_AAL34: 2151 // we would if I knew how do the SAR! 2152 PRINTD (DBG_QOS|DBG_VCC, "AAL3/4"); 2153 vcc.aal = aal34; 2154 break; 2155 case ATM_AAL5: 2156 PRINTD (DBG_QOS|DBG_VCC, "AAL5"); 2157 vcc.aal = aal5; 2158 break; 2159 default: 2160 PRINTD (DBG_QOS|DBG_VCC, "Bad AAL!"); 2161 return -EINVAL; 2162 } 2163 2164 // TX traffic parameters 2165 2166 // there are two, interrelated problems here: 1. the reservation of 2167 // PCR is not a binary choice, we are given bounds and/or a 2168 // desirable value; 2. the device is only capable of certain values, 2169 // most of which are not integers. It is almost certainly acceptable 2170 // to be off by a maximum of 1 to 10 cps. 2171 2172 // Pragmatic choice: always store an integral PCR as that which has 2173 // been allocated, even if we allocate a little (or a lot) less, 2174 // after rounding. The actual allocation depends on what we can 2175 // manage with our rate selection algorithm. The rate selection 2176 // algorithm is given an integral PCR and a tolerance and told 2177 // whether it should round the value up or down if the tolerance is 2178 // exceeded; it returns: a) the actual rate selected (rounded up to 2179 // the nearest integer), b) a bit pattern to feed to the timer 2180 // register, and c) a failure value if no applicable rate exists. 2181 2182 // Part of the job is done by atm_pcr_goal which gives us a PCR 2183 // specification which says: EITHER grab the maximum available PCR 2184 // (and perhaps a lower bound which we musn't pass), OR grab this 2185 // amount, rounding down if you have to (and perhaps a lower bound 2186 // which we musn't pass) OR grab this amount, rounding up if you 2187 // have to (and perhaps an upper bound which we musn't pass). If any 2188 // bounds ARE passed we fail. Note that rounding is only rounding to 2189 // match device limitations, we do not round down to satisfy 2190 // bandwidth availability even if this would not violate any given 2191 // lower bound. 2192 2193 // Note: telephony = 64kb/s = 48 byte cell payload @ 500/3 cells/s 2194 // (say) so this is not even a binary fixpoint cell rate (but this 2195 // device can do it). To avoid this sort of hassle we use a 2196 // tolerance parameter (currently fixed at 10 cps). 2197 2198 PRINTD (DBG_QOS, "TX:"); 2199 2200 txtp = &qos->txtp; 2201 2202 // set up defaults for no traffic 2203 vcc.tx_rate = 0; 2204 // who knows what would actually happen if you try and send on this? 2205 vcc.tx_xbr_bits = IDLE_RATE_TYPE; 2206 vcc.tx_pcr_bits = CLOCK_DISABLE; 2207#if 0 2208 vcc.tx_scr_bits = CLOCK_DISABLE; 2209 vcc.tx_bucket_bits = 0; 2210#endif 2211 2212 if (txtp->traffic_class != ATM_NONE) { 2213 error = check_max_sdu (vcc.aal, txtp, max_tx_size); 2214 if (error) { 2215 PRINTD (DBG_QOS, "TX max_sdu check failed"); 2216 return error; 2217 } 2218 2219 switch (txtp->traffic_class) { 2220 case ATM_UBR: { 2221 // we take "the PCR" as a rate-cap 2222 // not reserved 2223 vcc.tx_rate = 0; 2224 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, NULL); 2225 vcc.tx_xbr_bits = ABR_RATE_TYPE; 2226 break; 2227 } 2228#if 0 2229 case ATM_ABR: { 2230 // reserve min, allow up to max 2231 vcc.tx_rate = 0; // ? 2232 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0); 2233 vcc.tx_xbr_bits = ABR_RATE_TYPE; 2234 break; 2235 } 2236#endif 2237 case ATM_CBR: { 2238 int pcr = atm_pcr_goal (txtp); 2239 rounding r; 2240 if (!pcr) { 2241 // down vs. up, remaining bandwidth vs. unlimited bandwidth!! 2242 // should really have: once someone gets unlimited bandwidth 2243 // that no more non-UBR channels can be opened until the 2244 // unlimited one closes?? For the moment, round_down means 2245 // greedy people actually get something and not nothing 2246 r = round_down; 2247 // slight race (no locking) here so we may get -EAGAIN 2248 // later; the greedy bastards would deserve it :) 2249 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth"); 2250 pcr = dev->tx_avail; 2251 } else if (pcr < 0) { 2252 r = round_down; 2253 pcr = -pcr; 2254 } else { 2255 r = round_up; 2256 } 2257 error = make_rate_with_tolerance (dev, pcr, r, 10, 2258 &vcc.tx_pcr_bits, &vcc.tx_rate); 2259 if (error) { 2260 PRINTD (DBG_QOS, "could not make rate from TX PCR"); 2261 return error; 2262 } 2263 // not really clear what further checking is needed 2264 error = atm_pcr_check (txtp, vcc.tx_rate); 2265 if (error) { 2266 PRINTD (DBG_QOS, "TX PCR failed consistency check"); 2267 return error; 2268 } 2269 vcc.tx_xbr_bits = CBR_RATE_TYPE; 2270 break; 2271 } 2272#if 0 2273 case ATM_VBR: { 2274 int pcr = atm_pcr_goal (txtp); 2275 // int scr = atm_scr_goal (txtp); 2276 int scr = pcr/2; // just for fun 2277 unsigned int mbs = 60; // just for fun 2278 rounding pr; 2279 rounding sr; 2280 unsigned int bucket; 2281 if (!pcr) { 2282 pr = round_nearest; 2283 pcr = 1<<30; 2284 } else if (pcr < 0) { 2285 pr = round_down; 2286 pcr = -pcr; 2287 } else { 2288 pr = round_up; 2289 } 2290 error = make_rate_with_tolerance (dev, pcr, pr, 10, 2291 &vcc.tx_pcr_bits, 0); 2292 if (!scr) { 2293 // see comments for PCR with CBR above 2294 sr = round_down; 2295 // slight race (no locking) here so we may get -EAGAIN 2296 // later; the greedy bastards would deserve it :) 2297 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth"); 2298 scr = dev->tx_avail; 2299 } else if (scr < 0) { 2300 sr = round_down; 2301 scr = -scr; 2302 } else { 2303 sr = round_up; 2304 } 2305 error = make_rate_with_tolerance (dev, scr, sr, 10, 2306 &vcc.tx_scr_bits, &vcc.tx_rate); 2307 if (error) { 2308 PRINTD (DBG_QOS, "could not make rate from TX SCR"); 2309 return error; 2310 } 2311 // not really clear what further checking is needed 2312 // error = atm_scr_check (txtp, vcc.tx_rate); 2313 if (error) { 2314 PRINTD (DBG_QOS, "TX SCR failed consistency check"); 2315 return error; 2316 } 2317 // bucket calculations (from a piece of paper...) cell bucket 2318 // capacity must be largest integer smaller than m(p-s)/p + 1 2319 // where m = max burst size, p = pcr, s = scr 2320 bucket = mbs*(pcr-scr)/pcr; 2321 if (bucket*pcr != mbs*(pcr-scr)) 2322 bucket += 1; 2323 if (bucket > BUCKET_MAX_SIZE) { 2324 PRINTD (DBG_QOS, "shrinking bucket from %u to %u", 2325 bucket, BUCKET_MAX_SIZE); 2326 bucket = BUCKET_MAX_SIZE; 2327 } 2328 vcc.tx_xbr_bits = VBR_RATE_TYPE; 2329 vcc.tx_bucket_bits = bucket; 2330 break; 2331 } 2332#endif 2333 default: { 2334 PRINTD (DBG_QOS, "unsupported TX traffic class"); 2335 return -EINVAL; 2336 } 2337 } 2338 } 2339 2340 // RX traffic parameters 2341 2342 PRINTD (DBG_QOS, "RX:"); 2343 2344 rxtp = &qos->rxtp; 2345 2346 // set up defaults for no traffic 2347 vcc.rx_rate = 0; 2348 2349 if (rxtp->traffic_class != ATM_NONE) { 2350 error = check_max_sdu (vcc.aal, rxtp, max_rx_size); 2351 if (error) { 2352 PRINTD (DBG_QOS, "RX max_sdu check failed"); 2353 return error; 2354 } 2355 switch (rxtp->traffic_class) { 2356 case ATM_UBR: { 2357 // not reserved 2358 break; 2359 } 2360#if 0 2361 case ATM_ABR: { 2362 // reserve min 2363 vcc.rx_rate = 0; // ? 2364 break; 2365 } 2366#endif 2367 case ATM_CBR: { 2368 int pcr = atm_pcr_goal (rxtp); 2369 if (!pcr) { 2370 // slight race (no locking) here so we may get -EAGAIN 2371 // later; the greedy bastards would deserve it :) 2372 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth"); 2373 pcr = dev->rx_avail; 2374 } else if (pcr < 0) { 2375 pcr = -pcr; 2376 } 2377 vcc.rx_rate = pcr; 2378 // not really clear what further checking is needed 2379 error = atm_pcr_check (rxtp, vcc.rx_rate); 2380 if (error) { 2381 PRINTD (DBG_QOS, "RX PCR failed consistency check"); 2382 return error; 2383 } 2384 break; 2385 } 2386#if 0 2387 case ATM_VBR: { 2388 // int scr = atm_scr_goal (rxtp); 2389 int scr = 1<<16; // just for fun 2390 if (!scr) { 2391 // slight race (no locking) here so we may get -EAGAIN 2392 // later; the greedy bastards would deserve it :) 2393 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth"); 2394 scr = dev->rx_avail; 2395 } else if (scr < 0) { 2396 scr = -scr; 2397 } 2398 vcc.rx_rate = scr; 2399 // not really clear what further checking is needed 2400 // error = atm_scr_check (rxtp, vcc.rx_rate); 2401 if (error) { 2402 PRINTD (DBG_QOS, "RX SCR failed consistency check"); 2403 return error; 2404 } 2405 break; 2406 } 2407#endif 2408 default: { 2409 PRINTD (DBG_QOS, "unsupported RX traffic class"); 2410 return -EINVAL; 2411 } 2412 } 2413 } 2414 2415 2416 // late abort useful for diagnostics 2417 if (vcc.aal != aal5) { 2418 PRINTD (DBG_QOS, "AAL not supported"); 2419 return -EINVAL; 2420 } 2421 2422 // get space for our vcc stuff and copy parameters into it 2423 vccp = kmalloc (sizeof(hrz_vcc), GFP_KERNEL); 2424 if (!vccp) { 2425 PRINTK (KERN_ERR, "out of memory!"); 2426 return -ENOMEM; 2427 } 2428 *vccp = vcc; 2429 2430 // clear error and grab cell rate resource lock 2431 error = 0; 2432 spin_lock (&dev->rate_lock); 2433 2434 if (vcc.tx_rate > dev->tx_avail) { 2435 PRINTD (DBG_QOS, "not enough TX PCR left"); 2436 error = -EAGAIN; 2437 } 2438 2439 if (vcc.rx_rate > dev->rx_avail) { 2440 PRINTD (DBG_QOS, "not enough RX PCR left"); 2441 error = -EAGAIN; 2442 } 2443 2444 if (!error) { 2445 // really consume cell rates 2446 dev->tx_avail -= vcc.tx_rate; 2447 dev->rx_avail -= vcc.rx_rate; 2448 PRINTD (DBG_QOS|DBG_VCC, "reserving %u TX PCR and %u RX PCR", 2449 vcc.tx_rate, vcc.rx_rate); 2450 } 2451 2452 // release lock and exit on error 2453 spin_unlock (&dev->rate_lock); 2454 if (error) { 2455 PRINTD (DBG_QOS|DBG_VCC, "insufficient cell rate resources"); 2456 kfree (vccp); 2457 return error; 2458 } 2459 2460 // this is "immediately before allocating the connection identifier 2461 // in hardware" - so long as the next call does not fail :) 2462 set_bit(ATM_VF_ADDR,&atm_vcc->flags); 2463 2464 // any errors here are very serious and should never occur 2465 2466 if (rxtp->traffic_class != ATM_NONE) { 2467 if (dev->rxer[channel]) { 2468 PRINTD (DBG_ERR|DBG_VCC, "VC already open for RX"); 2469 error = -EBUSY; 2470 } 2471 if (!error) 2472 error = hrz_open_rx (dev, channel); 2473 if (error) { 2474 kfree (vccp); 2475 return error; 2476 } 2477 // this link allows RX frames through 2478 dev->rxer[channel] = atm_vcc; 2479 } 2480 2481 // success, set elements of atm_vcc 2482 atm_vcc->dev_data = (void *) vccp; 2483 2484 // indicate readiness 2485 set_bit(ATM_VF_READY,&atm_vcc->flags); 2486 2487 return 0; 2488} 2489 2490/********** close VC **********/ 2491 2492static void hrz_close (struct atm_vcc * atm_vcc) { 2493 hrz_dev * dev = HRZ_DEV(atm_vcc->dev); 2494 hrz_vcc * vcc = HRZ_VCC(atm_vcc); 2495 u16 channel = vcc->channel; 2496 PRINTD (DBG_VCC|DBG_FLOW, "hrz_close"); 2497 2498 // indicate unreadiness 2499 clear_bit(ATM_VF_READY,&atm_vcc->flags); 2500 2501 if (atm_vcc->qos.txtp.traffic_class != ATM_NONE) { 2502 unsigned int i; 2503 2504 // let any TX on this channel that has started complete 2505 // no restart, just keep trying 2506 while (tx_hold (dev)) 2507 ; 2508 // remove record of any tx_channel having been setup for this channel 2509 for (i = 0; i < TX_CHANS; ++i) 2510 if (dev->tx_channel_record[i] == channel) { 2511 dev->tx_channel_record[i] = -1; 2512 break; 2513 } 2514 if (dev->last_vc == channel) 2515 dev->tx_last = -1; 2516 tx_release (dev); 2517 } 2518 2519 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) { 2520 // disable RXing - it tries quite hard 2521 hrz_close_rx (dev, channel); 2522 // forget the vcc - no more skbs will be pushed 2523 if (atm_vcc != dev->rxer[channel]) 2524 PRINTK (KERN_ERR, "%s atm_vcc=%p rxer[channel]=%p", 2525 "arghhh! we're going to die!", 2526 atm_vcc, dev->rxer[channel]); 2527 dev->rxer[channel] = NULL; 2528 } 2529 2530 // atomically release our rate reservation 2531 spin_lock (&dev->rate_lock); 2532 PRINTD (DBG_QOS|DBG_VCC, "releasing %u TX PCR and %u RX PCR", 2533 vcc->tx_rate, vcc->rx_rate); 2534 dev->tx_avail += vcc->tx_rate; 2535 dev->rx_avail += vcc->rx_rate; 2536 spin_unlock (&dev->rate_lock); 2537 2538 // free our structure 2539 kfree (vcc); 2540 // say the VPI/VCI is free again 2541 clear_bit(ATM_VF_ADDR,&atm_vcc->flags); 2542} 2543 2544#if 0 2545static int hrz_getsockopt (struct atm_vcc * atm_vcc, int level, int optname, 2546 void *optval, int optlen) { 2547 hrz_dev * dev = HRZ_DEV(atm_vcc->dev); 2548 PRINTD (DBG_FLOW|DBG_VCC, "hrz_getsockopt"); 2549 switch (level) { 2550 case SOL_SOCKET: 2551 switch (optname) { 2552// case SO_BCTXOPT: 2553// break; 2554// case SO_BCRXOPT: 2555// break; 2556 default: 2557 return -ENOPROTOOPT; 2558 }; 2559 break; 2560 } 2561 return -EINVAL; 2562} 2563 2564static int hrz_setsockopt (struct atm_vcc * atm_vcc, int level, int optname, 2565 void *optval, unsigned int optlen) { 2566 hrz_dev * dev = HRZ_DEV(atm_vcc->dev); 2567 PRINTD (DBG_FLOW|DBG_VCC, "hrz_setsockopt"); 2568 switch (level) { 2569 case SOL_SOCKET: 2570 switch (optname) { 2571// case SO_BCTXOPT: 2572// break; 2573// case SO_BCRXOPT: 2574// break; 2575 default: 2576 return -ENOPROTOOPT; 2577 }; 2578 break; 2579 } 2580 return -EINVAL; 2581} 2582#endif 2583 2584#if 0 2585static int hrz_ioctl (struct atm_dev * atm_dev, unsigned int cmd, void *arg) { 2586 hrz_dev * dev = HRZ_DEV(atm_dev); 2587 PRINTD (DBG_FLOW, "hrz_ioctl"); 2588 return -1; 2589} 2590 2591unsigned char hrz_phy_get (struct atm_dev * atm_dev, unsigned long addr) { 2592 hrz_dev * dev = HRZ_DEV(atm_dev); 2593 PRINTD (DBG_FLOW, "hrz_phy_get"); 2594 return 0; 2595} 2596 2597static void hrz_phy_put (struct atm_dev * atm_dev, unsigned char value, 2598 unsigned long addr) { 2599 hrz_dev * dev = HRZ_DEV(atm_dev); 2600 PRINTD (DBG_FLOW, "hrz_phy_put"); 2601} 2602 2603static int hrz_change_qos (struct atm_vcc * atm_vcc, struct atm_qos *qos, int flgs) { 2604 hrz_dev * dev = HRZ_DEV(vcc->dev); 2605 PRINTD (DBG_FLOW, "hrz_change_qos"); 2606 return -1; 2607} 2608#endif 2609 2610/********** proc file contents **********/ 2611 2612static int hrz_proc_read (struct atm_dev * atm_dev, loff_t * pos, char * page) { 2613 hrz_dev * dev = HRZ_DEV(atm_dev); 2614 int left = *pos; 2615 PRINTD (DBG_FLOW, "hrz_proc_read"); 2616 2617 /* more diagnostics here? */ 2618 2619#if 0 2620 if (!left--) { 2621 unsigned int count = sprintf (page, "vbr buckets:"); 2622 unsigned int i; 2623 for (i = 0; i < TX_CHANS; ++i) 2624 count += sprintf (page, " %u/%u", 2625 query_tx_channel_config (dev, i, BUCKET_FULLNESS_ACCESS), 2626 query_tx_channel_config (dev, i, BUCKET_CAPACITY_ACCESS)); 2627 count += sprintf (page+count, ".\n"); 2628 return count; 2629 } 2630#endif 2631 2632 if (!left--) 2633 return sprintf (page, 2634 "cells: TX %lu, RX %lu, HEC errors %lu, unassigned %lu.\n", 2635 dev->tx_cell_count, dev->rx_cell_count, 2636 dev->hec_error_count, dev->unassigned_cell_count); 2637 2638 if (!left--) 2639 return sprintf (page, 2640 "free cell buffers: TX %hu, RX %hu+%hu.\n", 2641 rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF), 2642 rd_regw (dev, RX_FREE_BUFFER_COUNT_OFF), 2643 dev->noof_spare_buffers); 2644 2645 if (!left--) 2646 return sprintf (page, 2647 "cps remaining: TX %u, RX %u\n", 2648 dev->tx_avail, dev->rx_avail); 2649 2650 return 0; 2651} 2652 2653static const struct atmdev_ops hrz_ops = { 2654 .open = hrz_open, 2655 .close = hrz_close, 2656 .send = hrz_send, 2657 .proc_read = hrz_proc_read, 2658 .owner = THIS_MODULE, 2659}; 2660 2661static int hrz_probe(struct pci_dev *pci_dev, 2662 const struct pci_device_id *pci_ent) 2663{ 2664 hrz_dev * dev; 2665 int err = 0; 2666 2667 // adapter slot free, read resources from PCI configuration space 2668 u32 iobase = pci_resource_start (pci_dev, 0); 2669 u32 * membase = bus_to_virt (pci_resource_start (pci_dev, 1)); 2670 unsigned int irq; 2671 unsigned char lat; 2672 2673 PRINTD (DBG_FLOW, "hrz_probe"); 2674 2675 if (pci_enable_device(pci_dev)) 2676 return -EINVAL; 2677 2678 /* XXX DEV_LABEL is a guess */ 2679 if (!request_region(iobase, HRZ_IO_EXTENT, DEV_LABEL)) { 2680 err = -EINVAL; 2681 goto out_disable; 2682 } 2683 2684 dev = kzalloc(sizeof(hrz_dev), GFP_KERNEL); 2685 if (!dev) { 2686 // perhaps we should be nice: deregister all adapters and abort? 2687 PRINTD(DBG_ERR, "out of memory"); 2688 err = -ENOMEM; 2689 goto out_release; 2690 } 2691 2692 pci_set_drvdata(pci_dev, dev); 2693 2694 // grab IRQ and install handler - move this someplace more sensible 2695 irq = pci_dev->irq; 2696 if (request_irq(irq, 2697 interrupt_handler, 2698 IRQF_SHARED, /* irqflags guess */ 2699 DEV_LABEL, /* name guess */ 2700 dev)) { 2701 PRINTD(DBG_WARN, "request IRQ failed!"); 2702 err = -EINVAL; 2703 goto out_free; 2704 } 2705 2706 PRINTD(DBG_INFO, "found Madge ATM adapter (hrz) at: IO %x, IRQ %u, MEM %p", 2707 iobase, irq, membase); 2708 2709 dev->atm_dev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &hrz_ops, -1, 2710 NULL); 2711 if (!(dev->atm_dev)) { 2712 PRINTD(DBG_ERR, "failed to register Madge ATM adapter"); 2713 err = -EINVAL; 2714 goto out_free_irq; 2715 } 2716 2717 PRINTD(DBG_INFO, "registered Madge ATM adapter (no. %d) (%p) at %p", 2718 dev->atm_dev->number, dev, dev->atm_dev); 2719 dev->atm_dev->dev_data = (void *) dev; 2720 dev->pci_dev = pci_dev; 2721 2722 // enable bus master accesses 2723 pci_set_master(pci_dev); 2724 2725 // frobnicate latency (upwards, usually) 2726 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &lat); 2727 if (pci_lat) { 2728 PRINTD(DBG_INFO, "%s PCI latency timer from %hu to %hu", 2729 "changing", lat, pci_lat); 2730 pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, pci_lat); 2731 } else if (lat < MIN_PCI_LATENCY) { 2732 PRINTK(KERN_INFO, "%s PCI latency timer from %hu to %hu", 2733 "increasing", lat, MIN_PCI_LATENCY); 2734 pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, MIN_PCI_LATENCY); 2735 } 2736 2737 dev->iobase = iobase; 2738 dev->irq = irq; 2739 dev->membase = membase; 2740 2741 dev->rx_q_entry = dev->rx_q_reset = &memmap->rx_q_entries[0]; 2742 dev->rx_q_wrap = &memmap->rx_q_entries[RX_CHANS-1]; 2743 2744 // these next three are performance hacks 2745 dev->last_vc = -1; 2746 dev->tx_last = -1; 2747 dev->tx_idle = 0; 2748 2749 dev->tx_regions = 0; 2750 dev->tx_bytes = 0; 2751 dev->tx_skb = NULL; 2752 dev->tx_iovec = NULL; 2753 2754 dev->tx_cell_count = 0; 2755 dev->rx_cell_count = 0; 2756 dev->hec_error_count = 0; 2757 dev->unassigned_cell_count = 0; 2758 2759 dev->noof_spare_buffers = 0; 2760 2761 { 2762 unsigned int i; 2763 for (i = 0; i < TX_CHANS; ++i) 2764 dev->tx_channel_record[i] = -1; 2765 } 2766 2767 dev->flags = 0; 2768 2769 // Allocate cell rates and remember ASIC version 2770 // Fibre: ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53 2771 // Copper: (WRONG) we want 6 into the above, close to 25Mb/s 2772 // Copper: (plagarise!) 25600000/8/270*260/53 - n/53 2773 2774 if (hrz_init(dev)) { 2775 // to be really pedantic, this should be ATM_OC3c_PCR 2776 dev->tx_avail = ATM_OC3_PCR; 2777 dev->rx_avail = ATM_OC3_PCR; 2778 set_bit(ultra, &dev->flags); // NOT "|= ultra" ! 2779 } else { 2780 dev->tx_avail = ((25600000/8)*26)/(27*53); 2781 dev->rx_avail = ((25600000/8)*26)/(27*53); 2782 PRINTD(DBG_WARN, "Buggy ASIC: no TX bus-mastering."); 2783 } 2784 2785 // rate changes spinlock 2786 spin_lock_init(&dev->rate_lock); 2787 2788 // on-board memory access spinlock; we want atomic reads and 2789 // writes to adapter memory (handles IRQ and SMP) 2790 spin_lock_init(&dev->mem_lock); 2791 2792 init_waitqueue_head(&dev->tx_queue); 2793 2794 // vpi in 0..4, vci in 6..10 2795 dev->atm_dev->ci_range.vpi_bits = vpi_bits; 2796 dev->atm_dev->ci_range.vci_bits = 10-vpi_bits; 2797 2798 init_timer(&dev->housekeeping); 2799 dev->housekeeping.function = do_housekeeping; 2800 dev->housekeeping.data = (unsigned long) dev; 2801 mod_timer(&dev->housekeeping, jiffies); 2802 2803out: 2804 return err; 2805 2806out_free_irq: 2807 free_irq(dev->irq, dev); 2808out_free: 2809 kfree(dev); 2810out_release: 2811 release_region(iobase, HRZ_IO_EXTENT); 2812out_disable: 2813 pci_disable_device(pci_dev); 2814 goto out; 2815} 2816 2817static void hrz_remove_one(struct pci_dev *pci_dev) 2818{ 2819 hrz_dev *dev; 2820 2821 dev = pci_get_drvdata(pci_dev); 2822 2823 PRINTD(DBG_INFO, "closing %p (atm_dev = %p)", dev, dev->atm_dev); 2824 del_timer_sync(&dev->housekeeping); 2825 hrz_reset(dev); 2826 atm_dev_deregister(dev->atm_dev); 2827 free_irq(dev->irq, dev); 2828 release_region(dev->iobase, HRZ_IO_EXTENT); 2829 kfree(dev); 2830 2831 pci_disable_device(pci_dev); 2832} 2833 2834static void __init hrz_check_args (void) { 2835#ifdef DEBUG_HORIZON 2836 PRINTK (KERN_NOTICE, "debug bitmap is %hx", debug &= DBG_MASK); 2837#else 2838 if (debug) 2839 PRINTK (KERN_NOTICE, "no debug support in this image"); 2840#endif 2841 2842 if (vpi_bits > HRZ_MAX_VPI) 2843 PRINTK (KERN_ERR, "vpi_bits has been limited to %hu", 2844 vpi_bits = HRZ_MAX_VPI); 2845 2846 if (max_tx_size < 0 || max_tx_size > TX_AAL5_LIMIT) 2847 PRINTK (KERN_NOTICE, "max_tx_size has been limited to %hu", 2848 max_tx_size = TX_AAL5_LIMIT); 2849 2850 if (max_rx_size < 0 || max_rx_size > RX_AAL5_LIMIT) 2851 PRINTK (KERN_NOTICE, "max_rx_size has been limited to %hu", 2852 max_rx_size = RX_AAL5_LIMIT); 2853 2854 return; 2855} 2856 2857MODULE_AUTHOR(maintainer_string); 2858MODULE_DESCRIPTION(description_string); 2859MODULE_LICENSE("GPL"); 2860module_param(debug, ushort, 0644); 2861module_param(vpi_bits, ushort, 0); 2862module_param(max_tx_size, int, 0); 2863module_param(max_rx_size, int, 0); 2864module_param(pci_lat, byte, 0); 2865MODULE_PARM_DESC(debug, "debug bitmap, see .h file"); 2866MODULE_PARM_DESC(vpi_bits, "number of bits (0..4) to allocate to VPIs"); 2867MODULE_PARM_DESC(max_tx_size, "maximum size of TX AAL5 frames"); 2868MODULE_PARM_DESC(max_rx_size, "maximum size of RX AAL5 frames"); 2869MODULE_PARM_DESC(pci_lat, "PCI latency in bus cycles"); 2870 2871static struct pci_device_id hrz_pci_tbl[] = { 2872 { PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_HORIZON, PCI_ANY_ID, PCI_ANY_ID, 2873 0, 0, 0 }, 2874 { 0, } 2875}; 2876 2877MODULE_DEVICE_TABLE(pci, hrz_pci_tbl); 2878 2879static struct pci_driver hrz_driver = { 2880 .name = "horizon", 2881 .probe = hrz_probe, 2882 .remove = hrz_remove_one, 2883 .id_table = hrz_pci_tbl, 2884}; 2885 2886/********** module entry **********/ 2887 2888static int __init hrz_module_init (void) { 2889 // sanity check - cast is needed since printk does not support %Zu 2890 if (sizeof(struct MEMMAP) != 128*1024/4) { 2891 PRINTK (KERN_ERR, "Fix struct MEMMAP (is %lu fakewords).", 2892 (unsigned long) sizeof(struct MEMMAP)); 2893 return -ENOMEM; 2894 } 2895 2896 show_version(); 2897 2898 // check arguments 2899 hrz_check_args(); 2900 2901 // get the juice 2902 return pci_register_driver(&hrz_driver); 2903} 2904 2905/********** module exit **********/ 2906 2907static void __exit hrz_module_exit (void) { 2908 PRINTD (DBG_FLOW, "cleanup_module"); 2909 2910 pci_unregister_driver(&hrz_driver); 2911} 2912 2913module_init(hrz_module_init); 2914module_exit(hrz_module_exit); 2915