1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/in.h>
37 #include <linux/ip.h>
38 #include <net/ip.h>
39 #include <net/tso.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
46 #include <linux/io.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
52 #include <linux/of.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_mdio.h>
56 #include <linux/of_net.h>
57 #include <linux/regulator/consumer.h>
58 #include <linux/if_vlan.h>
59 #include <linux/pinctrl/consumer.h>
60 #include <linux/prefetch.h>
61
62 #include <asm/cacheflush.h>
63
64 #include "fec.h"
65
66 static void set_multicast_list(struct net_device *ndev);
67 static void fec_enet_itr_coal_init(struct net_device *ndev);
68
69 #define DRIVER_NAME "fec"
70
71 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
72
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
80
81 static struct platform_device_id fec_devtype[] = {
82 {
83 /* keep it for coldfire */
84 .name = DRIVER_NAME,
85 .driver_data = 0,
86 }, {
87 .name = "imx25-fec",
88 .driver_data = FEC_QUIRK_USE_GASKET,
89 }, {
90 .name = "imx27-fec",
91 .driver_data = 0,
92 }, {
93 .name = "imx28-fec",
94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
95 FEC_QUIRK_SINGLE_MDIO,
96 }, {
97 .name = "imx6q-fec",
98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
99 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
100 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
101 }, {
102 .name = "mvf600-fec",
103 .driver_data = FEC_QUIRK_ENET_MAC,
104 }, {
105 .name = "imx6sx-fec",
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
107 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
108 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
109 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE,
110 }, {
111 /* sentinel */
112 }
113 };
114 MODULE_DEVICE_TABLE(platform, fec_devtype);
115
116 enum imx_fec_type {
117 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
118 IMX27_FEC, /* runs on i.mx27/35/51 */
119 IMX28_FEC,
120 IMX6Q_FEC,
121 MVF600_FEC,
122 IMX6SX_FEC,
123 };
124
125 static const struct of_device_id fec_dt_ids[] = {
126 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
127 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
128 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
129 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
130 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
131 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
132 { /* sentinel */ }
133 };
134 MODULE_DEVICE_TABLE(of, fec_dt_ids);
135
136 static unsigned char macaddr[ETH_ALEN];
137 module_param_array(macaddr, byte, NULL, 0);
138 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
139
140 #if defined(CONFIG_M5272)
141 /*
142 * Some hardware gets it MAC address out of local flash memory.
143 * if this is non-zero then assume it is the address to get MAC from.
144 */
145 #if defined(CONFIG_NETtel)
146 #define FEC_FLASHMAC 0xf0006006
147 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
148 #define FEC_FLASHMAC 0xf0006000
149 #elif defined(CONFIG_CANCam)
150 #define FEC_FLASHMAC 0xf0020000
151 #elif defined (CONFIG_M5272C3)
152 #define FEC_FLASHMAC (0xffe04000 + 4)
153 #elif defined(CONFIG_MOD5272)
154 #define FEC_FLASHMAC 0xffc0406b
155 #else
156 #define FEC_FLASHMAC 0
157 #endif
158 #endif /* CONFIG_M5272 */
159
160 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
161 */
162 #define PKT_MAXBUF_SIZE 1522
163 #define PKT_MINBUF_SIZE 64
164 #define PKT_MAXBLR_SIZE 1536
165
166 /* FEC receive acceleration */
167 #define FEC_RACC_IPDIS (1 << 1)
168 #define FEC_RACC_PRODIS (1 << 2)
169 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
170
171 /*
172 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
173 * size bits. Other FEC hardware does not, so we need to take that into
174 * account when setting it.
175 */
176 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
177 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
178 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
179 #else
180 #define OPT_FRAME_SIZE 0
181 #endif
182
183 /* FEC MII MMFR bits definition */
184 #define FEC_MMFR_ST (1 << 30)
185 #define FEC_MMFR_OP_READ (2 << 28)
186 #define FEC_MMFR_OP_WRITE (1 << 28)
187 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
188 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
189 #define FEC_MMFR_TA (2 << 16)
190 #define FEC_MMFR_DATA(v) (v & 0xffff)
191 /* FEC ECR bits definition */
192 #define FEC_ECR_MAGICEN (1 << 2)
193 #define FEC_ECR_SLEEP (1 << 3)
194
195 #define FEC_MII_TIMEOUT 30000 /* us */
196
197 /* Transmitter timeout */
198 #define TX_TIMEOUT (2 * HZ)
199
200 #define FEC_PAUSE_FLAG_AUTONEG 0x1
201 #define FEC_PAUSE_FLAG_ENABLE 0x2
202 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
203 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
204 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
205
206 #define COPYBREAK_DEFAULT 256
207
208 #define TSO_HEADER_SIZE 128
209 /* Max number of allowed TCP segments for software TSO */
210 #define FEC_MAX_TSO_SEGS 100
211 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
212
213 #define IS_TSO_HEADER(txq, addr) \
214 ((addr >= txq->tso_hdrs_dma) && \
215 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
216
217 static int mii_cnt;
218
219 static inline
fec_enet_get_nextdesc(struct bufdesc * bdp,struct fec_enet_private * fep,int queue_id)220 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
221 struct fec_enet_private *fep,
222 int queue_id)
223 {
224 struct bufdesc *new_bd = bdp + 1;
225 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
226 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
227 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
228 struct bufdesc_ex *ex_base;
229 struct bufdesc *base;
230 int ring_size;
231
232 if (bdp >= txq->tx_bd_base) {
233 base = txq->tx_bd_base;
234 ring_size = txq->tx_ring_size;
235 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
236 } else {
237 base = rxq->rx_bd_base;
238 ring_size = rxq->rx_ring_size;
239 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
240 }
241
242 if (fep->bufdesc_ex)
243 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
244 ex_base : ex_new_bd);
245 else
246 return (new_bd >= (base + ring_size)) ?
247 base : new_bd;
248 }
249
250 static inline
fec_enet_get_prevdesc(struct bufdesc * bdp,struct fec_enet_private * fep,int queue_id)251 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
252 struct fec_enet_private *fep,
253 int queue_id)
254 {
255 struct bufdesc *new_bd = bdp - 1;
256 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
257 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
258 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
259 struct bufdesc_ex *ex_base;
260 struct bufdesc *base;
261 int ring_size;
262
263 if (bdp >= txq->tx_bd_base) {
264 base = txq->tx_bd_base;
265 ring_size = txq->tx_ring_size;
266 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
267 } else {
268 base = rxq->rx_bd_base;
269 ring_size = rxq->rx_ring_size;
270 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
271 }
272
273 if (fep->bufdesc_ex)
274 return (struct bufdesc *)((ex_new_bd < ex_base) ?
275 (ex_new_bd + ring_size) : ex_new_bd);
276 else
277 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
278 }
279
fec_enet_get_bd_index(struct bufdesc * base,struct bufdesc * bdp,struct fec_enet_private * fep)280 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
281 struct fec_enet_private *fep)
282 {
283 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
284 }
285
fec_enet_get_free_txdesc_num(struct fec_enet_private * fep,struct fec_enet_priv_tx_q * txq)286 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
287 struct fec_enet_priv_tx_q *txq)
288 {
289 int entries;
290
291 entries = ((const char *)txq->dirty_tx -
292 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
293
294 return entries > 0 ? entries : entries + txq->tx_ring_size;
295 }
296
swap_buffer(void * bufaddr,int len)297 static void swap_buffer(void *bufaddr, int len)
298 {
299 int i;
300 unsigned int *buf = bufaddr;
301
302 for (i = 0; i < len; i += 4, buf++)
303 swab32s(buf);
304 }
305
swap_buffer2(void * dst_buf,void * src_buf,int len)306 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
307 {
308 int i;
309 unsigned int *src = src_buf;
310 unsigned int *dst = dst_buf;
311
312 for (i = 0; i < len; i += 4, src++, dst++)
313 *dst = swab32p(src);
314 }
315
fec_dump(struct net_device * ndev)316 static void fec_dump(struct net_device *ndev)
317 {
318 struct fec_enet_private *fep = netdev_priv(ndev);
319 struct bufdesc *bdp;
320 struct fec_enet_priv_tx_q *txq;
321 int index = 0;
322
323 netdev_info(ndev, "TX ring dump\n");
324 pr_info("Nr SC addr len SKB\n");
325
326 txq = fep->tx_queue[0];
327 bdp = txq->tx_bd_base;
328
329 do {
330 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
331 index,
332 bdp == txq->cur_tx ? 'S' : ' ',
333 bdp == txq->dirty_tx ? 'H' : ' ',
334 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
335 txq->tx_skbuff[index]);
336 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
337 index++;
338 } while (bdp != txq->tx_bd_base);
339 }
340
is_ipv4_pkt(struct sk_buff * skb)341 static inline bool is_ipv4_pkt(struct sk_buff *skb)
342 {
343 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
344 }
345
346 static int
fec_enet_clear_csum(struct sk_buff * skb,struct net_device * ndev)347 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
348 {
349 /* Only run for packets requiring a checksum. */
350 if (skb->ip_summed != CHECKSUM_PARTIAL)
351 return 0;
352
353 if (unlikely(skb_cow_head(skb, 0)))
354 return -1;
355
356 if (is_ipv4_pkt(skb))
357 ip_hdr(skb)->check = 0;
358 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
359
360 return 0;
361 }
362
363 static int
fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev)364 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
365 struct sk_buff *skb,
366 struct net_device *ndev)
367 {
368 struct fec_enet_private *fep = netdev_priv(ndev);
369 struct bufdesc *bdp = txq->cur_tx;
370 struct bufdesc_ex *ebdp;
371 int nr_frags = skb_shinfo(skb)->nr_frags;
372 unsigned short queue = skb_get_queue_mapping(skb);
373 int frag, frag_len;
374 unsigned short status;
375 unsigned int estatus = 0;
376 skb_frag_t *this_frag;
377 unsigned int index;
378 void *bufaddr;
379 dma_addr_t addr;
380 int i;
381
382 for (frag = 0; frag < nr_frags; frag++) {
383 this_frag = &skb_shinfo(skb)->frags[frag];
384 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
385 ebdp = (struct bufdesc_ex *)bdp;
386
387 status = bdp->cbd_sc;
388 status &= ~BD_ENET_TX_STATS;
389 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
390 frag_len = skb_shinfo(skb)->frags[frag].size;
391
392 /* Handle the last BD specially */
393 if (frag == nr_frags - 1) {
394 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
395 if (fep->bufdesc_ex) {
396 estatus |= BD_ENET_TX_INT;
397 if (unlikely(skb_shinfo(skb)->tx_flags &
398 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
399 estatus |= BD_ENET_TX_TS;
400 }
401 }
402
403 if (fep->bufdesc_ex) {
404 if (fep->quirks & FEC_QUIRK_HAS_AVB)
405 estatus |= FEC_TX_BD_FTYPE(queue);
406 if (skb->ip_summed == CHECKSUM_PARTIAL)
407 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
408 ebdp->cbd_bdu = 0;
409 ebdp->cbd_esc = estatus;
410 }
411
412 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
413
414 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
415 if (((unsigned long) bufaddr) & fep->tx_align ||
416 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
417 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
418 bufaddr = txq->tx_bounce[index];
419
420 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
421 swap_buffer(bufaddr, frag_len);
422 }
423
424 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
425 DMA_TO_DEVICE);
426 if (dma_mapping_error(&fep->pdev->dev, addr)) {
427 dev_kfree_skb_any(skb);
428 if (net_ratelimit())
429 netdev_err(ndev, "Tx DMA memory map failed\n");
430 goto dma_mapping_error;
431 }
432
433 bdp->cbd_bufaddr = addr;
434 bdp->cbd_datlen = frag_len;
435 bdp->cbd_sc = status;
436 }
437
438 txq->cur_tx = bdp;
439
440 return 0;
441
442 dma_mapping_error:
443 bdp = txq->cur_tx;
444 for (i = 0; i < frag; i++) {
445 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
446 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
447 bdp->cbd_datlen, DMA_TO_DEVICE);
448 }
449 return NETDEV_TX_OK;
450 }
451
fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev)452 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
453 struct sk_buff *skb, struct net_device *ndev)
454 {
455 struct fec_enet_private *fep = netdev_priv(ndev);
456 int nr_frags = skb_shinfo(skb)->nr_frags;
457 struct bufdesc *bdp, *last_bdp;
458 void *bufaddr;
459 dma_addr_t addr;
460 unsigned short status;
461 unsigned short buflen;
462 unsigned short queue;
463 unsigned int estatus = 0;
464 unsigned int index;
465 int entries_free;
466 int ret;
467
468 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
469 if (entries_free < MAX_SKB_FRAGS + 1) {
470 dev_kfree_skb_any(skb);
471 if (net_ratelimit())
472 netdev_err(ndev, "NOT enough BD for SG!\n");
473 return NETDEV_TX_OK;
474 }
475
476 /* Protocol checksum off-load for TCP and UDP. */
477 if (fec_enet_clear_csum(skb, ndev)) {
478 dev_kfree_skb_any(skb);
479 return NETDEV_TX_OK;
480 }
481
482 /* Fill in a Tx ring entry */
483 bdp = txq->cur_tx;
484 status = bdp->cbd_sc;
485 status &= ~BD_ENET_TX_STATS;
486
487 /* Set buffer length and buffer pointer */
488 bufaddr = skb->data;
489 buflen = skb_headlen(skb);
490
491 queue = skb_get_queue_mapping(skb);
492 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
493 if (((unsigned long) bufaddr) & fep->tx_align ||
494 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
495 memcpy(txq->tx_bounce[index], skb->data, buflen);
496 bufaddr = txq->tx_bounce[index];
497
498 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
499 swap_buffer(bufaddr, buflen);
500 }
501
502 /* Push the data cache so the CPM does not get stale memory data. */
503 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
504 if (dma_mapping_error(&fep->pdev->dev, addr)) {
505 dev_kfree_skb_any(skb);
506 if (net_ratelimit())
507 netdev_err(ndev, "Tx DMA memory map failed\n");
508 return NETDEV_TX_OK;
509 }
510
511 if (nr_frags) {
512 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
513 if (ret)
514 return ret;
515 } else {
516 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
517 if (fep->bufdesc_ex) {
518 estatus = BD_ENET_TX_INT;
519 if (unlikely(skb_shinfo(skb)->tx_flags &
520 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
521 estatus |= BD_ENET_TX_TS;
522 }
523 }
524
525 if (fep->bufdesc_ex) {
526
527 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
528
529 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
530 fep->hwts_tx_en))
531 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
532
533 if (fep->quirks & FEC_QUIRK_HAS_AVB)
534 estatus |= FEC_TX_BD_FTYPE(queue);
535
536 if (skb->ip_summed == CHECKSUM_PARTIAL)
537 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
538
539 ebdp->cbd_bdu = 0;
540 ebdp->cbd_esc = estatus;
541 }
542
543 last_bdp = txq->cur_tx;
544 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
545 /* Save skb pointer */
546 txq->tx_skbuff[index] = skb;
547
548 bdp->cbd_datlen = buflen;
549 bdp->cbd_bufaddr = addr;
550
551 /* Send it on its way. Tell FEC it's ready, interrupt when done,
552 * it's the last BD of the frame, and to put the CRC on the end.
553 */
554 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
555 bdp->cbd_sc = status;
556
557 /* If this was the last BD in the ring, start at the beginning again. */
558 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
559
560 skb_tx_timestamp(skb);
561
562 txq->cur_tx = bdp;
563
564 /* Trigger transmission start */
565 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
566
567 return 0;
568 }
569
570 static int
fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev,struct bufdesc * bdp,int index,char * data,int size,bool last_tcp,bool is_last)571 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
572 struct net_device *ndev,
573 struct bufdesc *bdp, int index, char *data,
574 int size, bool last_tcp, bool is_last)
575 {
576 struct fec_enet_private *fep = netdev_priv(ndev);
577 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
578 unsigned short queue = skb_get_queue_mapping(skb);
579 unsigned short status;
580 unsigned int estatus = 0;
581 dma_addr_t addr;
582
583 status = bdp->cbd_sc;
584 status &= ~BD_ENET_TX_STATS;
585
586 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
587
588 if (((unsigned long) data) & fep->tx_align ||
589 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
590 memcpy(txq->tx_bounce[index], data, size);
591 data = txq->tx_bounce[index];
592
593 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
594 swap_buffer(data, size);
595 }
596
597 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
598 if (dma_mapping_error(&fep->pdev->dev, addr)) {
599 dev_kfree_skb_any(skb);
600 if (net_ratelimit())
601 netdev_err(ndev, "Tx DMA memory map failed\n");
602 return NETDEV_TX_BUSY;
603 }
604
605 bdp->cbd_datlen = size;
606 bdp->cbd_bufaddr = addr;
607
608 if (fep->bufdesc_ex) {
609 if (fep->quirks & FEC_QUIRK_HAS_AVB)
610 estatus |= FEC_TX_BD_FTYPE(queue);
611 if (skb->ip_summed == CHECKSUM_PARTIAL)
612 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
613 ebdp->cbd_bdu = 0;
614 ebdp->cbd_esc = estatus;
615 }
616
617 /* Handle the last BD specially */
618 if (last_tcp)
619 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
620 if (is_last) {
621 status |= BD_ENET_TX_INTR;
622 if (fep->bufdesc_ex)
623 ebdp->cbd_esc |= BD_ENET_TX_INT;
624 }
625
626 bdp->cbd_sc = status;
627
628 return 0;
629 }
630
631 static int
fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev,struct bufdesc * bdp,int index)632 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
633 struct sk_buff *skb, struct net_device *ndev,
634 struct bufdesc *bdp, int index)
635 {
636 struct fec_enet_private *fep = netdev_priv(ndev);
637 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
638 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
639 unsigned short queue = skb_get_queue_mapping(skb);
640 void *bufaddr;
641 unsigned long dmabuf;
642 unsigned short status;
643 unsigned int estatus = 0;
644
645 status = bdp->cbd_sc;
646 status &= ~BD_ENET_TX_STATS;
647 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
648
649 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
650 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
651 if (((unsigned long)bufaddr) & fep->tx_align ||
652 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
653 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
654 bufaddr = txq->tx_bounce[index];
655
656 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
657 swap_buffer(bufaddr, hdr_len);
658
659 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
660 hdr_len, DMA_TO_DEVICE);
661 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
662 dev_kfree_skb_any(skb);
663 if (net_ratelimit())
664 netdev_err(ndev, "Tx DMA memory map failed\n");
665 return NETDEV_TX_BUSY;
666 }
667 }
668
669 bdp->cbd_bufaddr = dmabuf;
670 bdp->cbd_datlen = hdr_len;
671
672 if (fep->bufdesc_ex) {
673 if (fep->quirks & FEC_QUIRK_HAS_AVB)
674 estatus |= FEC_TX_BD_FTYPE(queue);
675 if (skb->ip_summed == CHECKSUM_PARTIAL)
676 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
677 ebdp->cbd_bdu = 0;
678 ebdp->cbd_esc = estatus;
679 }
680
681 bdp->cbd_sc = status;
682
683 return 0;
684 }
685
fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev)686 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
687 struct sk_buff *skb,
688 struct net_device *ndev)
689 {
690 struct fec_enet_private *fep = netdev_priv(ndev);
691 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
692 int total_len, data_left;
693 struct bufdesc *bdp = txq->cur_tx;
694 unsigned short queue = skb_get_queue_mapping(skb);
695 struct tso_t tso;
696 unsigned int index = 0;
697 int ret;
698
699 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
700 dev_kfree_skb_any(skb);
701 if (net_ratelimit())
702 netdev_err(ndev, "NOT enough BD for TSO!\n");
703 return NETDEV_TX_OK;
704 }
705
706 /* Protocol checksum off-load for TCP and UDP. */
707 if (fec_enet_clear_csum(skb, ndev)) {
708 dev_kfree_skb_any(skb);
709 return NETDEV_TX_OK;
710 }
711
712 /* Initialize the TSO handler, and prepare the first payload */
713 tso_start(skb, &tso);
714
715 total_len = skb->len - hdr_len;
716 while (total_len > 0) {
717 char *hdr;
718
719 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
720 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
721 total_len -= data_left;
722
723 /* prepare packet headers: MAC + IP + TCP */
724 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
725 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
726 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
727 if (ret)
728 goto err_release;
729
730 while (data_left > 0) {
731 int size;
732
733 size = min_t(int, tso.size, data_left);
734 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
735 index = fec_enet_get_bd_index(txq->tx_bd_base,
736 bdp, fep);
737 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
738 bdp, index,
739 tso.data, size,
740 size == data_left,
741 total_len == 0);
742 if (ret)
743 goto err_release;
744
745 data_left -= size;
746 tso_build_data(skb, &tso, size);
747 }
748
749 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
750 }
751
752 /* Save skb pointer */
753 txq->tx_skbuff[index] = skb;
754
755 skb_tx_timestamp(skb);
756 txq->cur_tx = bdp;
757
758 /* Trigger transmission start */
759 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
760 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
761 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
762 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
763 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
764 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
765
766 return 0;
767
768 err_release:
769 /* TODO: Release all used data descriptors for TSO */
770 return ret;
771 }
772
773 static netdev_tx_t
fec_enet_start_xmit(struct sk_buff * skb,struct net_device * ndev)774 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
775 {
776 struct fec_enet_private *fep = netdev_priv(ndev);
777 int entries_free;
778 unsigned short queue;
779 struct fec_enet_priv_tx_q *txq;
780 struct netdev_queue *nq;
781 int ret;
782
783 queue = skb_get_queue_mapping(skb);
784 txq = fep->tx_queue[queue];
785 nq = netdev_get_tx_queue(ndev, queue);
786
787 if (skb_is_gso(skb))
788 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
789 else
790 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
791 if (ret)
792 return ret;
793
794 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
795 if (entries_free <= txq->tx_stop_threshold)
796 netif_tx_stop_queue(nq);
797
798 return NETDEV_TX_OK;
799 }
800
801 /* Init RX & TX buffer descriptors
802 */
fec_enet_bd_init(struct net_device * dev)803 static void fec_enet_bd_init(struct net_device *dev)
804 {
805 struct fec_enet_private *fep = netdev_priv(dev);
806 struct fec_enet_priv_tx_q *txq;
807 struct fec_enet_priv_rx_q *rxq;
808 struct bufdesc *bdp;
809 unsigned int i;
810 unsigned int q;
811
812 for (q = 0; q < fep->num_rx_queues; q++) {
813 /* Initialize the receive buffer descriptors. */
814 rxq = fep->rx_queue[q];
815 bdp = rxq->rx_bd_base;
816
817 for (i = 0; i < rxq->rx_ring_size; i++) {
818
819 /* Initialize the BD for every fragment in the page. */
820 if (bdp->cbd_bufaddr)
821 bdp->cbd_sc = BD_ENET_RX_EMPTY;
822 else
823 bdp->cbd_sc = 0;
824 bdp = fec_enet_get_nextdesc(bdp, fep, q);
825 }
826
827 /* Set the last buffer to wrap */
828 bdp = fec_enet_get_prevdesc(bdp, fep, q);
829 bdp->cbd_sc |= BD_SC_WRAP;
830
831 rxq->cur_rx = rxq->rx_bd_base;
832 }
833
834 for (q = 0; q < fep->num_tx_queues; q++) {
835 /* ...and the same for transmit */
836 txq = fep->tx_queue[q];
837 bdp = txq->tx_bd_base;
838 txq->cur_tx = bdp;
839
840 for (i = 0; i < txq->tx_ring_size; i++) {
841 /* Initialize the BD for every fragment in the page. */
842 bdp->cbd_sc = 0;
843 if (txq->tx_skbuff[i]) {
844 dev_kfree_skb_any(txq->tx_skbuff[i]);
845 txq->tx_skbuff[i] = NULL;
846 }
847 bdp->cbd_bufaddr = 0;
848 bdp = fec_enet_get_nextdesc(bdp, fep, q);
849 }
850
851 /* Set the last buffer to wrap */
852 bdp = fec_enet_get_prevdesc(bdp, fep, q);
853 bdp->cbd_sc |= BD_SC_WRAP;
854 txq->dirty_tx = bdp;
855 }
856 }
857
fec_enet_active_rxring(struct net_device * ndev)858 static void fec_enet_active_rxring(struct net_device *ndev)
859 {
860 struct fec_enet_private *fep = netdev_priv(ndev);
861 int i;
862
863 for (i = 0; i < fep->num_rx_queues; i++)
864 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
865 }
866
fec_enet_enable_ring(struct net_device * ndev)867 static void fec_enet_enable_ring(struct net_device *ndev)
868 {
869 struct fec_enet_private *fep = netdev_priv(ndev);
870 struct fec_enet_priv_tx_q *txq;
871 struct fec_enet_priv_rx_q *rxq;
872 int i;
873
874 for (i = 0; i < fep->num_rx_queues; i++) {
875 rxq = fep->rx_queue[i];
876 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
877 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
878
879 /* enable DMA1/2 */
880 if (i)
881 writel(RCMR_MATCHEN | RCMR_CMP(i),
882 fep->hwp + FEC_RCMR(i));
883 }
884
885 for (i = 0; i < fep->num_tx_queues; i++) {
886 txq = fep->tx_queue[i];
887 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
888
889 /* enable DMA1/2 */
890 if (i)
891 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
892 fep->hwp + FEC_DMA_CFG(i));
893 }
894 }
895
fec_enet_reset_skb(struct net_device * ndev)896 static void fec_enet_reset_skb(struct net_device *ndev)
897 {
898 struct fec_enet_private *fep = netdev_priv(ndev);
899 struct fec_enet_priv_tx_q *txq;
900 int i, j;
901
902 for (i = 0; i < fep->num_tx_queues; i++) {
903 txq = fep->tx_queue[i];
904
905 for (j = 0; j < txq->tx_ring_size; j++) {
906 if (txq->tx_skbuff[j]) {
907 dev_kfree_skb_any(txq->tx_skbuff[j]);
908 txq->tx_skbuff[j] = NULL;
909 }
910 }
911 }
912 }
913
914 /*
915 * This function is called to start or restart the FEC during a link
916 * change, transmit timeout, or to reconfigure the FEC. The network
917 * packet processing for this device must be stopped before this call.
918 */
919 static void
fec_restart(struct net_device * ndev)920 fec_restart(struct net_device *ndev)
921 {
922 struct fec_enet_private *fep = netdev_priv(ndev);
923 u32 val;
924 u32 temp_mac[2];
925 u32 rcntl = OPT_FRAME_SIZE | 0x04;
926 u32 ecntl = 0x2; /* ETHEREN */
927
928 /* Whack a reset. We should wait for this.
929 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
930 * instead of reset MAC itself.
931 */
932 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
933 writel(0, fep->hwp + FEC_ECNTRL);
934 } else {
935 writel(1, fep->hwp + FEC_ECNTRL);
936 udelay(10);
937 }
938
939 /*
940 * enet-mac reset will reset mac address registers too,
941 * so need to reconfigure it.
942 */
943 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
944 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
945 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
946 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
947 }
948
949 /* Clear any outstanding interrupt. */
950 writel(0xffffffff, fep->hwp + FEC_IEVENT);
951
952 fec_enet_bd_init(ndev);
953
954 fec_enet_enable_ring(ndev);
955
956 /* Reset tx SKB buffers. */
957 fec_enet_reset_skb(ndev);
958
959 /* Enable MII mode */
960 if (fep->full_duplex == DUPLEX_FULL) {
961 /* FD enable */
962 writel(0x04, fep->hwp + FEC_X_CNTRL);
963 } else {
964 /* No Rcv on Xmit */
965 rcntl |= 0x02;
966 writel(0x0, fep->hwp + FEC_X_CNTRL);
967 }
968
969 /* Set MII speed */
970 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
971
972 #if !defined(CONFIG_M5272)
973 /* set RX checksum */
974 val = readl(fep->hwp + FEC_RACC);
975 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
976 val |= FEC_RACC_OPTIONS;
977 else
978 val &= ~FEC_RACC_OPTIONS;
979 writel(val, fep->hwp + FEC_RACC);
980 #endif
981
982 /*
983 * The phy interface and speed need to get configured
984 * differently on enet-mac.
985 */
986 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
987 /* Enable flow control and length check */
988 rcntl |= 0x40000000 | 0x00000020;
989
990 /* RGMII, RMII or MII */
991 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
992 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
993 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
994 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
995 rcntl |= (1 << 6);
996 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
997 rcntl |= (1 << 8);
998 else
999 rcntl &= ~(1 << 8);
1000
1001 /* 1G, 100M or 10M */
1002 if (fep->phy_dev) {
1003 if (fep->phy_dev->speed == SPEED_1000)
1004 ecntl |= (1 << 5);
1005 else if (fep->phy_dev->speed == SPEED_100)
1006 rcntl &= ~(1 << 9);
1007 else
1008 rcntl |= (1 << 9);
1009 }
1010 } else {
1011 #ifdef FEC_MIIGSK_ENR
1012 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1013 u32 cfgr;
1014 /* disable the gasket and wait */
1015 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1016 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1017 udelay(1);
1018
1019 /*
1020 * configure the gasket:
1021 * RMII, 50 MHz, no loopback, no echo
1022 * MII, 25 MHz, no loopback, no echo
1023 */
1024 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1025 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1026 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1027 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1028 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1029
1030 /* re-enable the gasket */
1031 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1032 }
1033 #endif
1034 }
1035
1036 #if !defined(CONFIG_M5272)
1037 /* enable pause frame*/
1038 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1039 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1040 fep->phy_dev && fep->phy_dev->pause)) {
1041 rcntl |= FEC_ENET_FCE;
1042
1043 /* set FIFO threshold parameter to reduce overrun */
1044 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1045 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1046 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1047 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1048
1049 /* OPD */
1050 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1051 } else {
1052 rcntl &= ~FEC_ENET_FCE;
1053 }
1054 #endif /* !defined(CONFIG_M5272) */
1055
1056 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1057
1058 /* Setup multicast filter. */
1059 set_multicast_list(ndev);
1060 #ifndef CONFIG_M5272
1061 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1062 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1063 #endif
1064
1065 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1066 /* enable ENET endian swap */
1067 ecntl |= (1 << 8);
1068 /* enable ENET store and forward mode */
1069 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1070 }
1071
1072 if (fep->bufdesc_ex)
1073 ecntl |= (1 << 4);
1074
1075 #ifndef CONFIG_M5272
1076 /* Enable the MIB statistic event counters */
1077 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1078 #endif
1079
1080 /* And last, enable the transmit and receive processing */
1081 writel(ecntl, fep->hwp + FEC_ECNTRL);
1082 fec_enet_active_rxring(ndev);
1083
1084 if (fep->bufdesc_ex)
1085 fec_ptp_start_cyclecounter(ndev);
1086
1087 /* Enable interrupts we wish to service */
1088 if (fep->link)
1089 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1090 else
1091 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1092
1093 /* Init the interrupt coalescing */
1094 fec_enet_itr_coal_init(ndev);
1095
1096 }
1097
1098 static void
fec_stop(struct net_device * ndev)1099 fec_stop(struct net_device *ndev)
1100 {
1101 struct fec_enet_private *fep = netdev_priv(ndev);
1102 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1103 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1104 u32 val;
1105
1106 /* We cannot expect a graceful transmit stop without link !!! */
1107 if (fep->link) {
1108 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1109 udelay(10);
1110 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1111 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1112 }
1113
1114 /* Whack a reset. We should wait for this.
1115 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1116 * instead of reset MAC itself.
1117 */
1118 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1119 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1120 writel(0, fep->hwp + FEC_ECNTRL);
1121 } else {
1122 writel(1, fep->hwp + FEC_ECNTRL);
1123 udelay(10);
1124 }
1125 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1126 } else {
1127 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1128 val = readl(fep->hwp + FEC_ECNTRL);
1129 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1130 writel(val, fep->hwp + FEC_ECNTRL);
1131
1132 if (pdata && pdata->sleep_mode_enable)
1133 pdata->sleep_mode_enable(true);
1134 }
1135 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1136
1137 /* We have to keep ENET enabled to have MII interrupt stay working */
1138 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1139 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1140 writel(2, fep->hwp + FEC_ECNTRL);
1141 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1142 }
1143 }
1144
1145
1146 static void
fec_timeout(struct net_device * ndev)1147 fec_timeout(struct net_device *ndev)
1148 {
1149 struct fec_enet_private *fep = netdev_priv(ndev);
1150
1151 fec_dump(ndev);
1152
1153 ndev->stats.tx_errors++;
1154
1155 schedule_work(&fep->tx_timeout_work);
1156 }
1157
fec_enet_timeout_work(struct work_struct * work)1158 static void fec_enet_timeout_work(struct work_struct *work)
1159 {
1160 struct fec_enet_private *fep =
1161 container_of(work, struct fec_enet_private, tx_timeout_work);
1162 struct net_device *ndev = fep->netdev;
1163
1164 rtnl_lock();
1165 if (netif_device_present(ndev) || netif_running(ndev)) {
1166 napi_disable(&fep->napi);
1167 netif_tx_lock_bh(ndev);
1168 fec_restart(ndev);
1169 netif_wake_queue(ndev);
1170 netif_tx_unlock_bh(ndev);
1171 napi_enable(&fep->napi);
1172 }
1173 rtnl_unlock();
1174 }
1175
1176 static void
fec_enet_hwtstamp(struct fec_enet_private * fep,unsigned ts,struct skb_shared_hwtstamps * hwtstamps)1177 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1178 struct skb_shared_hwtstamps *hwtstamps)
1179 {
1180 unsigned long flags;
1181 u64 ns;
1182
1183 spin_lock_irqsave(&fep->tmreg_lock, flags);
1184 ns = timecounter_cyc2time(&fep->tc, ts);
1185 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1186
1187 memset(hwtstamps, 0, sizeof(*hwtstamps));
1188 hwtstamps->hwtstamp = ns_to_ktime(ns);
1189 }
1190
1191 static void
fec_enet_tx_queue(struct net_device * ndev,u16 queue_id)1192 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1193 {
1194 struct fec_enet_private *fep;
1195 struct bufdesc *bdp;
1196 unsigned short status;
1197 struct sk_buff *skb;
1198 struct fec_enet_priv_tx_q *txq;
1199 struct netdev_queue *nq;
1200 int index = 0;
1201 int entries_free;
1202
1203 fep = netdev_priv(ndev);
1204
1205 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1206
1207 txq = fep->tx_queue[queue_id];
1208 /* get next bdp of dirty_tx */
1209 nq = netdev_get_tx_queue(ndev, queue_id);
1210 bdp = txq->dirty_tx;
1211
1212 /* get next bdp of dirty_tx */
1213 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1214
1215 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
1216
1217 /* current queue is empty */
1218 if (bdp == txq->cur_tx)
1219 break;
1220
1221 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1222
1223 skb = txq->tx_skbuff[index];
1224 txq->tx_skbuff[index] = NULL;
1225 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
1226 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1227 bdp->cbd_datlen, DMA_TO_DEVICE);
1228 bdp->cbd_bufaddr = 0;
1229 if (!skb) {
1230 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1231 continue;
1232 }
1233
1234 /* Check for errors. */
1235 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1236 BD_ENET_TX_RL | BD_ENET_TX_UN |
1237 BD_ENET_TX_CSL)) {
1238 ndev->stats.tx_errors++;
1239 if (status & BD_ENET_TX_HB) /* No heartbeat */
1240 ndev->stats.tx_heartbeat_errors++;
1241 if (status & BD_ENET_TX_LC) /* Late collision */
1242 ndev->stats.tx_window_errors++;
1243 if (status & BD_ENET_TX_RL) /* Retrans limit */
1244 ndev->stats.tx_aborted_errors++;
1245 if (status & BD_ENET_TX_UN) /* Underrun */
1246 ndev->stats.tx_fifo_errors++;
1247 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1248 ndev->stats.tx_carrier_errors++;
1249 } else {
1250 ndev->stats.tx_packets++;
1251 ndev->stats.tx_bytes += skb->len;
1252 }
1253
1254 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1255 fep->bufdesc_ex) {
1256 struct skb_shared_hwtstamps shhwtstamps;
1257 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1258
1259 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
1260 skb_tstamp_tx(skb, &shhwtstamps);
1261 }
1262
1263 /* Deferred means some collisions occurred during transmit,
1264 * but we eventually sent the packet OK.
1265 */
1266 if (status & BD_ENET_TX_DEF)
1267 ndev->stats.collisions++;
1268
1269 /* Free the sk buffer associated with this last transmit */
1270 dev_kfree_skb_any(skb);
1271
1272 txq->dirty_tx = bdp;
1273
1274 /* Update pointer to next buffer descriptor to be transmitted */
1275 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1276
1277 /* Since we have freed up a buffer, the ring is no longer full
1278 */
1279 if (netif_queue_stopped(ndev)) {
1280 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1281 if (entries_free >= txq->tx_wake_threshold)
1282 netif_tx_wake_queue(nq);
1283 }
1284 }
1285
1286 /* ERR006538: Keep the transmitter going */
1287 if (bdp != txq->cur_tx &&
1288 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1289 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1290 }
1291
1292 static void
fec_enet_tx(struct net_device * ndev)1293 fec_enet_tx(struct net_device *ndev)
1294 {
1295 struct fec_enet_private *fep = netdev_priv(ndev);
1296 u16 queue_id;
1297 /* First process class A queue, then Class B and Best Effort queue */
1298 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1299 clear_bit(queue_id, &fep->work_tx);
1300 fec_enet_tx_queue(ndev, queue_id);
1301 }
1302 return;
1303 }
1304
1305 static int
fec_enet_new_rxbdp(struct net_device * ndev,struct bufdesc * bdp,struct sk_buff * skb)1306 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1307 {
1308 struct fec_enet_private *fep = netdev_priv(ndev);
1309 int off;
1310
1311 off = ((unsigned long)skb->data) & fep->rx_align;
1312 if (off)
1313 skb_reserve(skb, fep->rx_align + 1 - off);
1314
1315 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1316 FEC_ENET_RX_FRSIZE - fep->rx_align,
1317 DMA_FROM_DEVICE);
1318 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1319 if (net_ratelimit())
1320 netdev_err(ndev, "Rx DMA memory map failed\n");
1321 return -ENOMEM;
1322 }
1323
1324 return 0;
1325 }
1326
fec_enet_copybreak(struct net_device * ndev,struct sk_buff ** skb,struct bufdesc * bdp,u32 length,bool swap)1327 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1328 struct bufdesc *bdp, u32 length, bool swap)
1329 {
1330 struct fec_enet_private *fep = netdev_priv(ndev);
1331 struct sk_buff *new_skb;
1332
1333 if (length > fep->rx_copybreak)
1334 return false;
1335
1336 new_skb = netdev_alloc_skb(ndev, length);
1337 if (!new_skb)
1338 return false;
1339
1340 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1341 FEC_ENET_RX_FRSIZE - fep->rx_align,
1342 DMA_FROM_DEVICE);
1343 if (!swap)
1344 memcpy(new_skb->data, (*skb)->data, length);
1345 else
1346 swap_buffer2(new_skb->data, (*skb)->data, length);
1347 *skb = new_skb;
1348
1349 return true;
1350 }
1351
1352 /* During a receive, the cur_rx points to the current incoming buffer.
1353 * When we update through the ring, if the next incoming buffer has
1354 * not been given to the system, we just set the empty indicator,
1355 * effectively tossing the packet.
1356 */
1357 static int
fec_enet_rx_queue(struct net_device * ndev,int budget,u16 queue_id)1358 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1359 {
1360 struct fec_enet_private *fep = netdev_priv(ndev);
1361 struct fec_enet_priv_rx_q *rxq;
1362 struct bufdesc *bdp;
1363 unsigned short status;
1364 struct sk_buff *skb_new = NULL;
1365 struct sk_buff *skb;
1366 ushort pkt_len;
1367 __u8 *data;
1368 int pkt_received = 0;
1369 struct bufdesc_ex *ebdp = NULL;
1370 bool vlan_packet_rcvd = false;
1371 u16 vlan_tag;
1372 int index = 0;
1373 bool is_copybreak;
1374 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1375
1376 #ifdef CONFIG_M532x
1377 flush_cache_all();
1378 #endif
1379 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1380 rxq = fep->rx_queue[queue_id];
1381
1382 /* First, grab all of the stats for the incoming packet.
1383 * These get messed up if we get called due to a busy condition.
1384 */
1385 bdp = rxq->cur_rx;
1386
1387 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1388
1389 if (pkt_received >= budget)
1390 break;
1391 pkt_received++;
1392
1393 /* Since we have allocated space to hold a complete frame,
1394 * the last indicator should be set.
1395 */
1396 if ((status & BD_ENET_RX_LAST) == 0)
1397 netdev_err(ndev, "rcv is not +last\n");
1398
1399 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1400
1401 /* Check for errors. */
1402 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1403 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1404 ndev->stats.rx_errors++;
1405 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1406 /* Frame too long or too short. */
1407 ndev->stats.rx_length_errors++;
1408 }
1409 if (status & BD_ENET_RX_NO) /* Frame alignment */
1410 ndev->stats.rx_frame_errors++;
1411 if (status & BD_ENET_RX_CR) /* CRC Error */
1412 ndev->stats.rx_crc_errors++;
1413 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1414 ndev->stats.rx_fifo_errors++;
1415 }
1416
1417 /* Report late collisions as a frame error.
1418 * On this error, the BD is closed, but we don't know what we
1419 * have in the buffer. So, just drop this frame on the floor.
1420 */
1421 if (status & BD_ENET_RX_CL) {
1422 ndev->stats.rx_errors++;
1423 ndev->stats.rx_frame_errors++;
1424 goto rx_processing_done;
1425 }
1426
1427 /* Process the incoming frame. */
1428 ndev->stats.rx_packets++;
1429 pkt_len = bdp->cbd_datlen;
1430 ndev->stats.rx_bytes += pkt_len;
1431
1432 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1433 skb = rxq->rx_skbuff[index];
1434
1435 /* The packet length includes FCS, but we don't want to
1436 * include that when passing upstream as it messes up
1437 * bridging applications.
1438 */
1439 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1440 need_swap);
1441 if (!is_copybreak) {
1442 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1443 if (unlikely(!skb_new)) {
1444 ndev->stats.rx_dropped++;
1445 goto rx_processing_done;
1446 }
1447 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1448 FEC_ENET_RX_FRSIZE - fep->rx_align,
1449 DMA_FROM_DEVICE);
1450 }
1451
1452 prefetch(skb->data - NET_IP_ALIGN);
1453 skb_put(skb, pkt_len - 4);
1454 data = skb->data;
1455 if (!is_copybreak && need_swap)
1456 swap_buffer(data, pkt_len);
1457
1458 /* Extract the enhanced buffer descriptor */
1459 ebdp = NULL;
1460 if (fep->bufdesc_ex)
1461 ebdp = (struct bufdesc_ex *)bdp;
1462
1463 /* If this is a VLAN packet remove the VLAN Tag */
1464 vlan_packet_rcvd = false;
1465 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1466 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1467 /* Push and remove the vlan tag */
1468 struct vlan_hdr *vlan_header =
1469 (struct vlan_hdr *) (data + ETH_HLEN);
1470 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1471
1472 vlan_packet_rcvd = true;
1473
1474 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1475 skb_pull(skb, VLAN_HLEN);
1476 }
1477
1478 skb->protocol = eth_type_trans(skb, ndev);
1479
1480 /* Get receive timestamp from the skb */
1481 if (fep->hwts_rx_en && fep->bufdesc_ex)
1482 fec_enet_hwtstamp(fep, ebdp->ts,
1483 skb_hwtstamps(skb));
1484
1485 if (fep->bufdesc_ex &&
1486 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1487 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1488 /* don't check it */
1489 skb->ip_summed = CHECKSUM_UNNECESSARY;
1490 } else {
1491 skb_checksum_none_assert(skb);
1492 }
1493 }
1494
1495 /* Handle received VLAN packets */
1496 if (vlan_packet_rcvd)
1497 __vlan_hwaccel_put_tag(skb,
1498 htons(ETH_P_8021Q),
1499 vlan_tag);
1500
1501 napi_gro_receive(&fep->napi, skb);
1502
1503 if (is_copybreak) {
1504 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1505 FEC_ENET_RX_FRSIZE - fep->rx_align,
1506 DMA_FROM_DEVICE);
1507 } else {
1508 rxq->rx_skbuff[index] = skb_new;
1509 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1510 }
1511
1512 rx_processing_done:
1513 /* Clear the status flags for this buffer */
1514 status &= ~BD_ENET_RX_STATS;
1515
1516 /* Mark the buffer empty */
1517 status |= BD_ENET_RX_EMPTY;
1518 bdp->cbd_sc = status;
1519
1520 if (fep->bufdesc_ex) {
1521 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1522
1523 ebdp->cbd_esc = BD_ENET_RX_INT;
1524 ebdp->cbd_prot = 0;
1525 ebdp->cbd_bdu = 0;
1526 }
1527
1528 /* Update BD pointer to next entry */
1529 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1530
1531 /* Doing this here will keep the FEC running while we process
1532 * incoming frames. On a heavily loaded network, we should be
1533 * able to keep up at the expense of system resources.
1534 */
1535 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1536 }
1537 rxq->cur_rx = bdp;
1538 return pkt_received;
1539 }
1540
1541 static int
fec_enet_rx(struct net_device * ndev,int budget)1542 fec_enet_rx(struct net_device *ndev, int budget)
1543 {
1544 int pkt_received = 0;
1545 u16 queue_id;
1546 struct fec_enet_private *fep = netdev_priv(ndev);
1547
1548 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1549 clear_bit(queue_id, &fep->work_rx);
1550 pkt_received += fec_enet_rx_queue(ndev,
1551 budget - pkt_received, queue_id);
1552 }
1553 return pkt_received;
1554 }
1555
1556 static bool
fec_enet_collect_events(struct fec_enet_private * fep,uint int_events)1557 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1558 {
1559 if (int_events == 0)
1560 return false;
1561
1562 if (int_events & FEC_ENET_RXF)
1563 fep->work_rx |= (1 << 2);
1564 if (int_events & FEC_ENET_RXF_1)
1565 fep->work_rx |= (1 << 0);
1566 if (int_events & FEC_ENET_RXF_2)
1567 fep->work_rx |= (1 << 1);
1568
1569 if (int_events & FEC_ENET_TXF)
1570 fep->work_tx |= (1 << 2);
1571 if (int_events & FEC_ENET_TXF_1)
1572 fep->work_tx |= (1 << 0);
1573 if (int_events & FEC_ENET_TXF_2)
1574 fep->work_tx |= (1 << 1);
1575
1576 return true;
1577 }
1578
1579 static irqreturn_t
fec_enet_interrupt(int irq,void * dev_id)1580 fec_enet_interrupt(int irq, void *dev_id)
1581 {
1582 struct net_device *ndev = dev_id;
1583 struct fec_enet_private *fep = netdev_priv(ndev);
1584 uint int_events;
1585 irqreturn_t ret = IRQ_NONE;
1586
1587 int_events = readl(fep->hwp + FEC_IEVENT);
1588 writel(int_events, fep->hwp + FEC_IEVENT);
1589 fec_enet_collect_events(fep, int_events);
1590
1591 if ((fep->work_tx || fep->work_rx) && fep->link) {
1592 ret = IRQ_HANDLED;
1593
1594 if (napi_schedule_prep(&fep->napi)) {
1595 /* Disable the NAPI interrupts */
1596 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1597 __napi_schedule(&fep->napi);
1598 }
1599 }
1600
1601 if (int_events & FEC_ENET_MII) {
1602 ret = IRQ_HANDLED;
1603 complete(&fep->mdio_done);
1604 }
1605
1606 if (fep->ptp_clock)
1607 fec_ptp_check_pps_event(fep);
1608
1609 return ret;
1610 }
1611
fec_enet_rx_napi(struct napi_struct * napi,int budget)1612 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1613 {
1614 struct net_device *ndev = napi->dev;
1615 struct fec_enet_private *fep = netdev_priv(ndev);
1616 int pkts;
1617
1618 pkts = fec_enet_rx(ndev, budget);
1619
1620 fec_enet_tx(ndev);
1621
1622 if (pkts < budget) {
1623 napi_complete(napi);
1624 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1625 }
1626 return pkts;
1627 }
1628
1629 /* ------------------------------------------------------------------------- */
fec_get_mac(struct net_device * ndev)1630 static void fec_get_mac(struct net_device *ndev)
1631 {
1632 struct fec_enet_private *fep = netdev_priv(ndev);
1633 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1634 unsigned char *iap, tmpaddr[ETH_ALEN];
1635
1636 /*
1637 * try to get mac address in following order:
1638 *
1639 * 1) module parameter via kernel command line in form
1640 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1641 */
1642 iap = macaddr;
1643
1644 /*
1645 * 2) from device tree data
1646 */
1647 if (!is_valid_ether_addr(iap)) {
1648 struct device_node *np = fep->pdev->dev.of_node;
1649 if (np) {
1650 const char *mac = of_get_mac_address(np);
1651 if (mac)
1652 iap = (unsigned char *) mac;
1653 }
1654 }
1655
1656 /*
1657 * 3) from flash or fuse (via platform data)
1658 */
1659 if (!is_valid_ether_addr(iap)) {
1660 #ifdef CONFIG_M5272
1661 if (FEC_FLASHMAC)
1662 iap = (unsigned char *)FEC_FLASHMAC;
1663 #else
1664 if (pdata)
1665 iap = (unsigned char *)&pdata->mac;
1666 #endif
1667 }
1668
1669 /*
1670 * 4) FEC mac registers set by bootloader
1671 */
1672 if (!is_valid_ether_addr(iap)) {
1673 *((__be32 *) &tmpaddr[0]) =
1674 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1675 *((__be16 *) &tmpaddr[4]) =
1676 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1677 iap = &tmpaddr[0];
1678 }
1679
1680 /*
1681 * 5) random mac address
1682 */
1683 if (!is_valid_ether_addr(iap)) {
1684 /* Report it and use a random ethernet address instead */
1685 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1686 eth_hw_addr_random(ndev);
1687 netdev_info(ndev, "Using random MAC address: %pM\n",
1688 ndev->dev_addr);
1689 return;
1690 }
1691
1692 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1693
1694 /* Adjust MAC if using macaddr */
1695 if (iap == macaddr)
1696 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1697 }
1698
1699 /* ------------------------------------------------------------------------- */
1700
1701 /*
1702 * Phy section
1703 */
fec_enet_adjust_link(struct net_device * ndev)1704 static void fec_enet_adjust_link(struct net_device *ndev)
1705 {
1706 struct fec_enet_private *fep = netdev_priv(ndev);
1707 struct phy_device *phy_dev = fep->phy_dev;
1708 int status_change = 0;
1709
1710 /* Prevent a state halted on mii error */
1711 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1712 phy_dev->state = PHY_RESUMING;
1713 return;
1714 }
1715
1716 /*
1717 * If the netdev is down, or is going down, we're not interested
1718 * in link state events, so just mark our idea of the link as down
1719 * and ignore the event.
1720 */
1721 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1722 fep->link = 0;
1723 } else if (phy_dev->link) {
1724 if (!fep->link) {
1725 fep->link = phy_dev->link;
1726 status_change = 1;
1727 }
1728
1729 if (fep->full_duplex != phy_dev->duplex) {
1730 fep->full_duplex = phy_dev->duplex;
1731 status_change = 1;
1732 }
1733
1734 if (phy_dev->speed != fep->speed) {
1735 fep->speed = phy_dev->speed;
1736 status_change = 1;
1737 }
1738
1739 /* if any of the above changed restart the FEC */
1740 if (status_change) {
1741 napi_disable(&fep->napi);
1742 netif_tx_lock_bh(ndev);
1743 fec_restart(ndev);
1744 netif_wake_queue(ndev);
1745 netif_tx_unlock_bh(ndev);
1746 napi_enable(&fep->napi);
1747 }
1748 } else {
1749 if (fep->link) {
1750 napi_disable(&fep->napi);
1751 netif_tx_lock_bh(ndev);
1752 fec_stop(ndev);
1753 netif_tx_unlock_bh(ndev);
1754 napi_enable(&fep->napi);
1755 fep->link = phy_dev->link;
1756 status_change = 1;
1757 }
1758 }
1759
1760 if (status_change)
1761 phy_print_status(phy_dev);
1762 }
1763
fec_enet_mdio_read(struct mii_bus * bus,int mii_id,int regnum)1764 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1765 {
1766 struct fec_enet_private *fep = bus->priv;
1767 unsigned long time_left;
1768
1769 fep->mii_timeout = 0;
1770 init_completion(&fep->mdio_done);
1771
1772 /* start a read op */
1773 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1774 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1775 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1776
1777 /* wait for end of transfer */
1778 time_left = wait_for_completion_timeout(&fep->mdio_done,
1779 usecs_to_jiffies(FEC_MII_TIMEOUT));
1780 if (time_left == 0) {
1781 fep->mii_timeout = 1;
1782 netdev_err(fep->netdev, "MDIO read timeout\n");
1783 return -ETIMEDOUT;
1784 }
1785
1786 /* return value */
1787 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1788 }
1789
fec_enet_mdio_write(struct mii_bus * bus,int mii_id,int regnum,u16 value)1790 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1791 u16 value)
1792 {
1793 struct fec_enet_private *fep = bus->priv;
1794 unsigned long time_left;
1795
1796 fep->mii_timeout = 0;
1797 init_completion(&fep->mdio_done);
1798
1799 /* start a write op */
1800 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1801 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1802 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1803 fep->hwp + FEC_MII_DATA);
1804
1805 /* wait for end of transfer */
1806 time_left = wait_for_completion_timeout(&fep->mdio_done,
1807 usecs_to_jiffies(FEC_MII_TIMEOUT));
1808 if (time_left == 0) {
1809 fep->mii_timeout = 1;
1810 netdev_err(fep->netdev, "MDIO write timeout\n");
1811 return -ETIMEDOUT;
1812 }
1813
1814 return 0;
1815 }
1816
fec_enet_clk_enable(struct net_device * ndev,bool enable)1817 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1818 {
1819 struct fec_enet_private *fep = netdev_priv(ndev);
1820 int ret;
1821
1822 if (enable) {
1823 ret = clk_prepare_enable(fep->clk_ahb);
1824 if (ret)
1825 return ret;
1826 ret = clk_prepare_enable(fep->clk_ipg);
1827 if (ret)
1828 goto failed_clk_ipg;
1829 if (fep->clk_enet_out) {
1830 ret = clk_prepare_enable(fep->clk_enet_out);
1831 if (ret)
1832 goto failed_clk_enet_out;
1833 }
1834 if (fep->clk_ptp) {
1835 mutex_lock(&fep->ptp_clk_mutex);
1836 ret = clk_prepare_enable(fep->clk_ptp);
1837 if (ret) {
1838 mutex_unlock(&fep->ptp_clk_mutex);
1839 goto failed_clk_ptp;
1840 } else {
1841 fep->ptp_clk_on = true;
1842 }
1843 mutex_unlock(&fep->ptp_clk_mutex);
1844 }
1845 if (fep->clk_ref) {
1846 ret = clk_prepare_enable(fep->clk_ref);
1847 if (ret)
1848 goto failed_clk_ref;
1849 }
1850 } else {
1851 clk_disable_unprepare(fep->clk_ahb);
1852 clk_disable_unprepare(fep->clk_ipg);
1853 if (fep->clk_enet_out)
1854 clk_disable_unprepare(fep->clk_enet_out);
1855 if (fep->clk_ptp) {
1856 mutex_lock(&fep->ptp_clk_mutex);
1857 clk_disable_unprepare(fep->clk_ptp);
1858 fep->ptp_clk_on = false;
1859 mutex_unlock(&fep->ptp_clk_mutex);
1860 }
1861 if (fep->clk_ref)
1862 clk_disable_unprepare(fep->clk_ref);
1863 }
1864
1865 return 0;
1866
1867 failed_clk_ref:
1868 if (fep->clk_ref)
1869 clk_disable_unprepare(fep->clk_ref);
1870 failed_clk_ptp:
1871 if (fep->clk_enet_out)
1872 clk_disable_unprepare(fep->clk_enet_out);
1873 failed_clk_enet_out:
1874 clk_disable_unprepare(fep->clk_ipg);
1875 failed_clk_ipg:
1876 clk_disable_unprepare(fep->clk_ahb);
1877
1878 return ret;
1879 }
1880
fec_enet_mii_probe(struct net_device * ndev)1881 static int fec_enet_mii_probe(struct net_device *ndev)
1882 {
1883 struct fec_enet_private *fep = netdev_priv(ndev);
1884 struct phy_device *phy_dev = NULL;
1885 char mdio_bus_id[MII_BUS_ID_SIZE];
1886 char phy_name[MII_BUS_ID_SIZE + 3];
1887 int phy_id;
1888 int dev_id = fep->dev_id;
1889
1890 fep->phy_dev = NULL;
1891
1892 if (fep->phy_node) {
1893 phy_dev = of_phy_connect(ndev, fep->phy_node,
1894 &fec_enet_adjust_link, 0,
1895 fep->phy_interface);
1896 if (!phy_dev)
1897 return -ENODEV;
1898 } else {
1899 /* check for attached phy */
1900 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1901 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1902 continue;
1903 if (fep->mii_bus->phy_map[phy_id] == NULL)
1904 continue;
1905 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1906 continue;
1907 if (dev_id--)
1908 continue;
1909 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1910 break;
1911 }
1912
1913 if (phy_id >= PHY_MAX_ADDR) {
1914 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1915 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1916 phy_id = 0;
1917 }
1918
1919 snprintf(phy_name, sizeof(phy_name),
1920 PHY_ID_FMT, mdio_bus_id, phy_id);
1921 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1922 fep->phy_interface);
1923 }
1924
1925 if (IS_ERR(phy_dev)) {
1926 netdev_err(ndev, "could not attach to PHY\n");
1927 return PTR_ERR(phy_dev);
1928 }
1929
1930 /* mask with MAC supported features */
1931 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1932 phy_dev->supported &= PHY_GBIT_FEATURES;
1933 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1934 #if !defined(CONFIG_M5272)
1935 phy_dev->supported |= SUPPORTED_Pause;
1936 #endif
1937 }
1938 else
1939 phy_dev->supported &= PHY_BASIC_FEATURES;
1940
1941 phy_dev->advertising = phy_dev->supported;
1942
1943 fep->phy_dev = phy_dev;
1944 fep->link = 0;
1945 fep->full_duplex = 0;
1946
1947 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1948 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1949 fep->phy_dev->irq);
1950
1951 return 0;
1952 }
1953
fec_enet_mii_init(struct platform_device * pdev)1954 static int fec_enet_mii_init(struct platform_device *pdev)
1955 {
1956 static struct mii_bus *fec0_mii_bus;
1957 struct net_device *ndev = platform_get_drvdata(pdev);
1958 struct fec_enet_private *fep = netdev_priv(ndev);
1959 struct device_node *node;
1960 int err = -ENXIO, i;
1961 u32 mii_speed, holdtime;
1962
1963 /*
1964 * The i.MX28 dual fec interfaces are not equal.
1965 * Here are the differences:
1966 *
1967 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1968 * - fec0 acts as the 1588 time master while fec1 is slave
1969 * - external phys can only be configured by fec0
1970 *
1971 * That is to say fec1 can not work independently. It only works
1972 * when fec0 is working. The reason behind this design is that the
1973 * second interface is added primarily for Switch mode.
1974 *
1975 * Because of the last point above, both phys are attached on fec0
1976 * mdio interface in board design, and need to be configured by
1977 * fec0 mii_bus.
1978 */
1979 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
1980 /* fec1 uses fec0 mii_bus */
1981 if (mii_cnt && fec0_mii_bus) {
1982 fep->mii_bus = fec0_mii_bus;
1983 mii_cnt++;
1984 return 0;
1985 }
1986 return -ENOENT;
1987 }
1988
1989 fep->mii_timeout = 0;
1990
1991 /*
1992 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1993 *
1994 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1995 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1996 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1997 * document.
1998 */
1999 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2000 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2001 mii_speed--;
2002 if (mii_speed > 63) {
2003 dev_err(&pdev->dev,
2004 "fec clock (%lu) to fast to get right mii speed\n",
2005 clk_get_rate(fep->clk_ipg));
2006 err = -EINVAL;
2007 goto err_out;
2008 }
2009
2010 /*
2011 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2012 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2013 * versions are RAZ there, so just ignore the difference and write the
2014 * register always.
2015 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2016 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2017 * output.
2018 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2019 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2020 * holdtime cannot result in a value greater than 3.
2021 */
2022 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2023
2024 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2025
2026 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2027
2028 fep->mii_bus = mdiobus_alloc();
2029 if (fep->mii_bus == NULL) {
2030 err = -ENOMEM;
2031 goto err_out;
2032 }
2033
2034 fep->mii_bus->name = "fec_enet_mii_bus";
2035 fep->mii_bus->read = fec_enet_mdio_read;
2036 fep->mii_bus->write = fec_enet_mdio_write;
2037 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2038 pdev->name, fep->dev_id + 1);
2039 fep->mii_bus->priv = fep;
2040 fep->mii_bus->parent = &pdev->dev;
2041
2042 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
2043 if (!fep->mii_bus->irq) {
2044 err = -ENOMEM;
2045 goto err_out_free_mdiobus;
2046 }
2047
2048 for (i = 0; i < PHY_MAX_ADDR; i++)
2049 fep->mii_bus->irq[i] = PHY_POLL;
2050
2051 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2052 if (node) {
2053 err = of_mdiobus_register(fep->mii_bus, node);
2054 of_node_put(node);
2055 } else {
2056 err = mdiobus_register(fep->mii_bus);
2057 }
2058
2059 if (err)
2060 goto err_out_free_mdio_irq;
2061
2062 mii_cnt++;
2063
2064 /* save fec0 mii_bus */
2065 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2066 fec0_mii_bus = fep->mii_bus;
2067
2068 return 0;
2069
2070 err_out_free_mdio_irq:
2071 kfree(fep->mii_bus->irq);
2072 err_out_free_mdiobus:
2073 mdiobus_free(fep->mii_bus);
2074 err_out:
2075 return err;
2076 }
2077
fec_enet_mii_remove(struct fec_enet_private * fep)2078 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2079 {
2080 if (--mii_cnt == 0) {
2081 mdiobus_unregister(fep->mii_bus);
2082 kfree(fep->mii_bus->irq);
2083 mdiobus_free(fep->mii_bus);
2084 }
2085 }
2086
fec_enet_get_settings(struct net_device * ndev,struct ethtool_cmd * cmd)2087 static int fec_enet_get_settings(struct net_device *ndev,
2088 struct ethtool_cmd *cmd)
2089 {
2090 struct fec_enet_private *fep = netdev_priv(ndev);
2091 struct phy_device *phydev = fep->phy_dev;
2092
2093 if (!phydev)
2094 return -ENODEV;
2095
2096 return phy_ethtool_gset(phydev, cmd);
2097 }
2098
fec_enet_set_settings(struct net_device * ndev,struct ethtool_cmd * cmd)2099 static int fec_enet_set_settings(struct net_device *ndev,
2100 struct ethtool_cmd *cmd)
2101 {
2102 struct fec_enet_private *fep = netdev_priv(ndev);
2103 struct phy_device *phydev = fep->phy_dev;
2104
2105 if (!phydev)
2106 return -ENODEV;
2107
2108 return phy_ethtool_sset(phydev, cmd);
2109 }
2110
fec_enet_get_drvinfo(struct net_device * ndev,struct ethtool_drvinfo * info)2111 static void fec_enet_get_drvinfo(struct net_device *ndev,
2112 struct ethtool_drvinfo *info)
2113 {
2114 struct fec_enet_private *fep = netdev_priv(ndev);
2115
2116 strlcpy(info->driver, fep->pdev->dev.driver->name,
2117 sizeof(info->driver));
2118 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2119 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2120 }
2121
fec_enet_get_ts_info(struct net_device * ndev,struct ethtool_ts_info * info)2122 static int fec_enet_get_ts_info(struct net_device *ndev,
2123 struct ethtool_ts_info *info)
2124 {
2125 struct fec_enet_private *fep = netdev_priv(ndev);
2126
2127 if (fep->bufdesc_ex) {
2128
2129 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2130 SOF_TIMESTAMPING_RX_SOFTWARE |
2131 SOF_TIMESTAMPING_SOFTWARE |
2132 SOF_TIMESTAMPING_TX_HARDWARE |
2133 SOF_TIMESTAMPING_RX_HARDWARE |
2134 SOF_TIMESTAMPING_RAW_HARDWARE;
2135 if (fep->ptp_clock)
2136 info->phc_index = ptp_clock_index(fep->ptp_clock);
2137 else
2138 info->phc_index = -1;
2139
2140 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2141 (1 << HWTSTAMP_TX_ON);
2142
2143 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2144 (1 << HWTSTAMP_FILTER_ALL);
2145 return 0;
2146 } else {
2147 return ethtool_op_get_ts_info(ndev, info);
2148 }
2149 }
2150
2151 #if !defined(CONFIG_M5272)
2152
fec_enet_get_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * pause)2153 static void fec_enet_get_pauseparam(struct net_device *ndev,
2154 struct ethtool_pauseparam *pause)
2155 {
2156 struct fec_enet_private *fep = netdev_priv(ndev);
2157
2158 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2159 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2160 pause->rx_pause = pause->tx_pause;
2161 }
2162
fec_enet_set_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * pause)2163 static int fec_enet_set_pauseparam(struct net_device *ndev,
2164 struct ethtool_pauseparam *pause)
2165 {
2166 struct fec_enet_private *fep = netdev_priv(ndev);
2167
2168 if (!fep->phy_dev)
2169 return -ENODEV;
2170
2171 if (pause->tx_pause != pause->rx_pause) {
2172 netdev_info(ndev,
2173 "hardware only support enable/disable both tx and rx");
2174 return -EINVAL;
2175 }
2176
2177 fep->pause_flag = 0;
2178
2179 /* tx pause must be same as rx pause */
2180 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2181 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2182
2183 if (pause->rx_pause || pause->autoneg) {
2184 fep->phy_dev->supported |= ADVERTISED_Pause;
2185 fep->phy_dev->advertising |= ADVERTISED_Pause;
2186 } else {
2187 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2188 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2189 }
2190
2191 if (pause->autoneg) {
2192 if (netif_running(ndev))
2193 fec_stop(ndev);
2194 phy_start_aneg(fep->phy_dev);
2195 }
2196 if (netif_running(ndev)) {
2197 napi_disable(&fep->napi);
2198 netif_tx_lock_bh(ndev);
2199 fec_restart(ndev);
2200 netif_wake_queue(ndev);
2201 netif_tx_unlock_bh(ndev);
2202 napi_enable(&fep->napi);
2203 }
2204
2205 return 0;
2206 }
2207
2208 static const struct fec_stat {
2209 char name[ETH_GSTRING_LEN];
2210 u16 offset;
2211 } fec_stats[] = {
2212 /* RMON TX */
2213 { "tx_dropped", RMON_T_DROP },
2214 { "tx_packets", RMON_T_PACKETS },
2215 { "tx_broadcast", RMON_T_BC_PKT },
2216 { "tx_multicast", RMON_T_MC_PKT },
2217 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2218 { "tx_undersize", RMON_T_UNDERSIZE },
2219 { "tx_oversize", RMON_T_OVERSIZE },
2220 { "tx_fragment", RMON_T_FRAG },
2221 { "tx_jabber", RMON_T_JAB },
2222 { "tx_collision", RMON_T_COL },
2223 { "tx_64byte", RMON_T_P64 },
2224 { "tx_65to127byte", RMON_T_P65TO127 },
2225 { "tx_128to255byte", RMON_T_P128TO255 },
2226 { "tx_256to511byte", RMON_T_P256TO511 },
2227 { "tx_512to1023byte", RMON_T_P512TO1023 },
2228 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2229 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2230 { "tx_octets", RMON_T_OCTETS },
2231
2232 /* IEEE TX */
2233 { "IEEE_tx_drop", IEEE_T_DROP },
2234 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2235 { "IEEE_tx_1col", IEEE_T_1COL },
2236 { "IEEE_tx_mcol", IEEE_T_MCOL },
2237 { "IEEE_tx_def", IEEE_T_DEF },
2238 { "IEEE_tx_lcol", IEEE_T_LCOL },
2239 { "IEEE_tx_excol", IEEE_T_EXCOL },
2240 { "IEEE_tx_macerr", IEEE_T_MACERR },
2241 { "IEEE_tx_cserr", IEEE_T_CSERR },
2242 { "IEEE_tx_sqe", IEEE_T_SQE },
2243 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2244 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2245
2246 /* RMON RX */
2247 { "rx_packets", RMON_R_PACKETS },
2248 { "rx_broadcast", RMON_R_BC_PKT },
2249 { "rx_multicast", RMON_R_MC_PKT },
2250 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2251 { "rx_undersize", RMON_R_UNDERSIZE },
2252 { "rx_oversize", RMON_R_OVERSIZE },
2253 { "rx_fragment", RMON_R_FRAG },
2254 { "rx_jabber", RMON_R_JAB },
2255 { "rx_64byte", RMON_R_P64 },
2256 { "rx_65to127byte", RMON_R_P65TO127 },
2257 { "rx_128to255byte", RMON_R_P128TO255 },
2258 { "rx_256to511byte", RMON_R_P256TO511 },
2259 { "rx_512to1023byte", RMON_R_P512TO1023 },
2260 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2261 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2262 { "rx_octets", RMON_R_OCTETS },
2263
2264 /* IEEE RX */
2265 { "IEEE_rx_drop", IEEE_R_DROP },
2266 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2267 { "IEEE_rx_crc", IEEE_R_CRC },
2268 { "IEEE_rx_align", IEEE_R_ALIGN },
2269 { "IEEE_rx_macerr", IEEE_R_MACERR },
2270 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2271 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2272 };
2273
fec_enet_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)2274 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2275 struct ethtool_stats *stats, u64 *data)
2276 {
2277 struct fec_enet_private *fep = netdev_priv(dev);
2278 int i;
2279
2280 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2281 data[i] = readl(fep->hwp + fec_stats[i].offset);
2282 }
2283
fec_enet_get_strings(struct net_device * netdev,u32 stringset,u8 * data)2284 static void fec_enet_get_strings(struct net_device *netdev,
2285 u32 stringset, u8 *data)
2286 {
2287 int i;
2288 switch (stringset) {
2289 case ETH_SS_STATS:
2290 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2291 memcpy(data + i * ETH_GSTRING_LEN,
2292 fec_stats[i].name, ETH_GSTRING_LEN);
2293 break;
2294 }
2295 }
2296
fec_enet_get_sset_count(struct net_device * dev,int sset)2297 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2298 {
2299 switch (sset) {
2300 case ETH_SS_STATS:
2301 return ARRAY_SIZE(fec_stats);
2302 default:
2303 return -EOPNOTSUPP;
2304 }
2305 }
2306 #endif /* !defined(CONFIG_M5272) */
2307
fec_enet_nway_reset(struct net_device * dev)2308 static int fec_enet_nway_reset(struct net_device *dev)
2309 {
2310 struct fec_enet_private *fep = netdev_priv(dev);
2311 struct phy_device *phydev = fep->phy_dev;
2312
2313 if (!phydev)
2314 return -ENODEV;
2315
2316 return genphy_restart_aneg(phydev);
2317 }
2318
2319 /* ITR clock source is enet system clock (clk_ahb).
2320 * TCTT unit is cycle_ns * 64 cycle
2321 * So, the ICTT value = X us / (cycle_ns * 64)
2322 */
fec_enet_us_to_itr_clock(struct net_device * ndev,int us)2323 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2324 {
2325 struct fec_enet_private *fep = netdev_priv(ndev);
2326
2327 return us * (fep->itr_clk_rate / 64000) / 1000;
2328 }
2329
2330 /* Set threshold for interrupt coalescing */
fec_enet_itr_coal_set(struct net_device * ndev)2331 static void fec_enet_itr_coal_set(struct net_device *ndev)
2332 {
2333 struct fec_enet_private *fep = netdev_priv(ndev);
2334 int rx_itr, tx_itr;
2335
2336 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2337 return;
2338
2339 /* Must be greater than zero to avoid unpredictable behavior */
2340 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2341 !fep->tx_time_itr || !fep->tx_pkts_itr)
2342 return;
2343
2344 /* Select enet system clock as Interrupt Coalescing
2345 * timer Clock Source
2346 */
2347 rx_itr = FEC_ITR_CLK_SEL;
2348 tx_itr = FEC_ITR_CLK_SEL;
2349
2350 /* set ICFT and ICTT */
2351 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2352 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2353 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2354 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2355
2356 rx_itr |= FEC_ITR_EN;
2357 tx_itr |= FEC_ITR_EN;
2358
2359 writel(tx_itr, fep->hwp + FEC_TXIC0);
2360 writel(rx_itr, fep->hwp + FEC_RXIC0);
2361 writel(tx_itr, fep->hwp + FEC_TXIC1);
2362 writel(rx_itr, fep->hwp + FEC_RXIC1);
2363 writel(tx_itr, fep->hwp + FEC_TXIC2);
2364 writel(rx_itr, fep->hwp + FEC_RXIC2);
2365 }
2366
2367 static int
fec_enet_get_coalesce(struct net_device * ndev,struct ethtool_coalesce * ec)2368 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2369 {
2370 struct fec_enet_private *fep = netdev_priv(ndev);
2371
2372 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2373 return -EOPNOTSUPP;
2374
2375 ec->rx_coalesce_usecs = fep->rx_time_itr;
2376 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2377
2378 ec->tx_coalesce_usecs = fep->tx_time_itr;
2379 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2380
2381 return 0;
2382 }
2383
2384 static int
fec_enet_set_coalesce(struct net_device * ndev,struct ethtool_coalesce * ec)2385 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2386 {
2387 struct fec_enet_private *fep = netdev_priv(ndev);
2388 unsigned int cycle;
2389
2390 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2391 return -EOPNOTSUPP;
2392
2393 if (ec->rx_max_coalesced_frames > 255) {
2394 pr_err("Rx coalesced frames exceed hardware limiation");
2395 return -EINVAL;
2396 }
2397
2398 if (ec->tx_max_coalesced_frames > 255) {
2399 pr_err("Tx coalesced frame exceed hardware limiation");
2400 return -EINVAL;
2401 }
2402
2403 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2404 if (cycle > 0xFFFF) {
2405 pr_err("Rx coalesed usec exceeed hardware limiation");
2406 return -EINVAL;
2407 }
2408
2409 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2410 if (cycle > 0xFFFF) {
2411 pr_err("Rx coalesed usec exceeed hardware limiation");
2412 return -EINVAL;
2413 }
2414
2415 fep->rx_time_itr = ec->rx_coalesce_usecs;
2416 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2417
2418 fep->tx_time_itr = ec->tx_coalesce_usecs;
2419 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2420
2421 fec_enet_itr_coal_set(ndev);
2422
2423 return 0;
2424 }
2425
fec_enet_itr_coal_init(struct net_device * ndev)2426 static void fec_enet_itr_coal_init(struct net_device *ndev)
2427 {
2428 struct ethtool_coalesce ec;
2429
2430 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2431 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2432
2433 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2434 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2435
2436 fec_enet_set_coalesce(ndev, &ec);
2437 }
2438
fec_enet_get_tunable(struct net_device * netdev,const struct ethtool_tunable * tuna,void * data)2439 static int fec_enet_get_tunable(struct net_device *netdev,
2440 const struct ethtool_tunable *tuna,
2441 void *data)
2442 {
2443 struct fec_enet_private *fep = netdev_priv(netdev);
2444 int ret = 0;
2445
2446 switch (tuna->id) {
2447 case ETHTOOL_RX_COPYBREAK:
2448 *(u32 *)data = fep->rx_copybreak;
2449 break;
2450 default:
2451 ret = -EINVAL;
2452 break;
2453 }
2454
2455 return ret;
2456 }
2457
fec_enet_set_tunable(struct net_device * netdev,const struct ethtool_tunable * tuna,const void * data)2458 static int fec_enet_set_tunable(struct net_device *netdev,
2459 const struct ethtool_tunable *tuna,
2460 const void *data)
2461 {
2462 struct fec_enet_private *fep = netdev_priv(netdev);
2463 int ret = 0;
2464
2465 switch (tuna->id) {
2466 case ETHTOOL_RX_COPYBREAK:
2467 fep->rx_copybreak = *(u32 *)data;
2468 break;
2469 default:
2470 ret = -EINVAL;
2471 break;
2472 }
2473
2474 return ret;
2475 }
2476
2477 static void
fec_enet_get_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)2478 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2479 {
2480 struct fec_enet_private *fep = netdev_priv(ndev);
2481
2482 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2483 wol->supported = WAKE_MAGIC;
2484 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2485 } else {
2486 wol->supported = wol->wolopts = 0;
2487 }
2488 }
2489
2490 static int
fec_enet_set_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)2491 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2492 {
2493 struct fec_enet_private *fep = netdev_priv(ndev);
2494
2495 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2496 return -EINVAL;
2497
2498 if (wol->wolopts & ~WAKE_MAGIC)
2499 return -EINVAL;
2500
2501 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2502 if (device_may_wakeup(&ndev->dev)) {
2503 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2504 if (fep->irq[0] > 0)
2505 enable_irq_wake(fep->irq[0]);
2506 } else {
2507 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2508 if (fep->irq[0] > 0)
2509 disable_irq_wake(fep->irq[0]);
2510 }
2511
2512 return 0;
2513 }
2514
2515 static const struct ethtool_ops fec_enet_ethtool_ops = {
2516 .get_settings = fec_enet_get_settings,
2517 .set_settings = fec_enet_set_settings,
2518 .get_drvinfo = fec_enet_get_drvinfo,
2519 .nway_reset = fec_enet_nway_reset,
2520 .get_link = ethtool_op_get_link,
2521 .get_coalesce = fec_enet_get_coalesce,
2522 .set_coalesce = fec_enet_set_coalesce,
2523 #ifndef CONFIG_M5272
2524 .get_pauseparam = fec_enet_get_pauseparam,
2525 .set_pauseparam = fec_enet_set_pauseparam,
2526 .get_strings = fec_enet_get_strings,
2527 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2528 .get_sset_count = fec_enet_get_sset_count,
2529 #endif
2530 .get_ts_info = fec_enet_get_ts_info,
2531 .get_tunable = fec_enet_get_tunable,
2532 .set_tunable = fec_enet_set_tunable,
2533 .get_wol = fec_enet_get_wol,
2534 .set_wol = fec_enet_set_wol,
2535 };
2536
fec_enet_ioctl(struct net_device * ndev,struct ifreq * rq,int cmd)2537 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2538 {
2539 struct fec_enet_private *fep = netdev_priv(ndev);
2540 struct phy_device *phydev = fep->phy_dev;
2541
2542 if (!netif_running(ndev))
2543 return -EINVAL;
2544
2545 if (!phydev)
2546 return -ENODEV;
2547
2548 if (fep->bufdesc_ex) {
2549 if (cmd == SIOCSHWTSTAMP)
2550 return fec_ptp_set(ndev, rq);
2551 if (cmd == SIOCGHWTSTAMP)
2552 return fec_ptp_get(ndev, rq);
2553 }
2554
2555 return phy_mii_ioctl(phydev, rq, cmd);
2556 }
2557
fec_enet_free_buffers(struct net_device * ndev)2558 static void fec_enet_free_buffers(struct net_device *ndev)
2559 {
2560 struct fec_enet_private *fep = netdev_priv(ndev);
2561 unsigned int i;
2562 struct sk_buff *skb;
2563 struct bufdesc *bdp;
2564 struct fec_enet_priv_tx_q *txq;
2565 struct fec_enet_priv_rx_q *rxq;
2566 unsigned int q;
2567
2568 for (q = 0; q < fep->num_rx_queues; q++) {
2569 rxq = fep->rx_queue[q];
2570 bdp = rxq->rx_bd_base;
2571 for (i = 0; i < rxq->rx_ring_size; i++) {
2572 skb = rxq->rx_skbuff[i];
2573 rxq->rx_skbuff[i] = NULL;
2574 if (skb) {
2575 dma_unmap_single(&fep->pdev->dev,
2576 bdp->cbd_bufaddr,
2577 FEC_ENET_RX_FRSIZE - fep->rx_align,
2578 DMA_FROM_DEVICE);
2579 dev_kfree_skb(skb);
2580 }
2581 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2582 }
2583 }
2584
2585 for (q = 0; q < fep->num_tx_queues; q++) {
2586 txq = fep->tx_queue[q];
2587 bdp = txq->tx_bd_base;
2588 for (i = 0; i < txq->tx_ring_size; i++) {
2589 kfree(txq->tx_bounce[i]);
2590 txq->tx_bounce[i] = NULL;
2591 skb = txq->tx_skbuff[i];
2592 txq->tx_skbuff[i] = NULL;
2593 dev_kfree_skb(skb);
2594 }
2595 }
2596 }
2597
fec_enet_free_queue(struct net_device * ndev)2598 static void fec_enet_free_queue(struct net_device *ndev)
2599 {
2600 struct fec_enet_private *fep = netdev_priv(ndev);
2601 int i;
2602 struct fec_enet_priv_tx_q *txq;
2603
2604 for (i = 0; i < fep->num_tx_queues; i++)
2605 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2606 txq = fep->tx_queue[i];
2607 dma_free_coherent(NULL,
2608 txq->tx_ring_size * TSO_HEADER_SIZE,
2609 txq->tso_hdrs,
2610 txq->tso_hdrs_dma);
2611 }
2612
2613 for (i = 0; i < fep->num_rx_queues; i++)
2614 kfree(fep->rx_queue[i]);
2615 for (i = 0; i < fep->num_tx_queues; i++)
2616 kfree(fep->tx_queue[i]);
2617 }
2618
fec_enet_alloc_queue(struct net_device * ndev)2619 static int fec_enet_alloc_queue(struct net_device *ndev)
2620 {
2621 struct fec_enet_private *fep = netdev_priv(ndev);
2622 int i;
2623 int ret = 0;
2624 struct fec_enet_priv_tx_q *txq;
2625
2626 for (i = 0; i < fep->num_tx_queues; i++) {
2627 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2628 if (!txq) {
2629 ret = -ENOMEM;
2630 goto alloc_failed;
2631 }
2632
2633 fep->tx_queue[i] = txq;
2634 txq->tx_ring_size = TX_RING_SIZE;
2635 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2636
2637 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2638 txq->tx_wake_threshold =
2639 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2640
2641 txq->tso_hdrs = dma_alloc_coherent(NULL,
2642 txq->tx_ring_size * TSO_HEADER_SIZE,
2643 &txq->tso_hdrs_dma,
2644 GFP_KERNEL);
2645 if (!txq->tso_hdrs) {
2646 ret = -ENOMEM;
2647 goto alloc_failed;
2648 }
2649 }
2650
2651 for (i = 0; i < fep->num_rx_queues; i++) {
2652 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2653 GFP_KERNEL);
2654 if (!fep->rx_queue[i]) {
2655 ret = -ENOMEM;
2656 goto alloc_failed;
2657 }
2658
2659 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2660 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2661 }
2662 return ret;
2663
2664 alloc_failed:
2665 fec_enet_free_queue(ndev);
2666 return ret;
2667 }
2668
2669 static int
fec_enet_alloc_rxq_buffers(struct net_device * ndev,unsigned int queue)2670 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2671 {
2672 struct fec_enet_private *fep = netdev_priv(ndev);
2673 unsigned int i;
2674 struct sk_buff *skb;
2675 struct bufdesc *bdp;
2676 struct fec_enet_priv_rx_q *rxq;
2677
2678 rxq = fep->rx_queue[queue];
2679 bdp = rxq->rx_bd_base;
2680 for (i = 0; i < rxq->rx_ring_size; i++) {
2681 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2682 if (!skb)
2683 goto err_alloc;
2684
2685 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2686 dev_kfree_skb(skb);
2687 goto err_alloc;
2688 }
2689
2690 rxq->rx_skbuff[i] = skb;
2691 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2692
2693 if (fep->bufdesc_ex) {
2694 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2695 ebdp->cbd_esc = BD_ENET_RX_INT;
2696 }
2697
2698 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2699 }
2700
2701 /* Set the last buffer to wrap. */
2702 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2703 bdp->cbd_sc |= BD_SC_WRAP;
2704 return 0;
2705
2706 err_alloc:
2707 fec_enet_free_buffers(ndev);
2708 return -ENOMEM;
2709 }
2710
2711 static int
fec_enet_alloc_txq_buffers(struct net_device * ndev,unsigned int queue)2712 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2713 {
2714 struct fec_enet_private *fep = netdev_priv(ndev);
2715 unsigned int i;
2716 struct bufdesc *bdp;
2717 struct fec_enet_priv_tx_q *txq;
2718
2719 txq = fep->tx_queue[queue];
2720 bdp = txq->tx_bd_base;
2721 for (i = 0; i < txq->tx_ring_size; i++) {
2722 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2723 if (!txq->tx_bounce[i])
2724 goto err_alloc;
2725
2726 bdp->cbd_sc = 0;
2727 bdp->cbd_bufaddr = 0;
2728
2729 if (fep->bufdesc_ex) {
2730 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2731 ebdp->cbd_esc = BD_ENET_TX_INT;
2732 }
2733
2734 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2735 }
2736
2737 /* Set the last buffer to wrap. */
2738 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2739 bdp->cbd_sc |= BD_SC_WRAP;
2740
2741 return 0;
2742
2743 err_alloc:
2744 fec_enet_free_buffers(ndev);
2745 return -ENOMEM;
2746 }
2747
fec_enet_alloc_buffers(struct net_device * ndev)2748 static int fec_enet_alloc_buffers(struct net_device *ndev)
2749 {
2750 struct fec_enet_private *fep = netdev_priv(ndev);
2751 unsigned int i;
2752
2753 for (i = 0; i < fep->num_rx_queues; i++)
2754 if (fec_enet_alloc_rxq_buffers(ndev, i))
2755 return -ENOMEM;
2756
2757 for (i = 0; i < fep->num_tx_queues; i++)
2758 if (fec_enet_alloc_txq_buffers(ndev, i))
2759 return -ENOMEM;
2760 return 0;
2761 }
2762
2763 static int
fec_enet_open(struct net_device * ndev)2764 fec_enet_open(struct net_device *ndev)
2765 {
2766 struct fec_enet_private *fep = netdev_priv(ndev);
2767 int ret;
2768
2769 pinctrl_pm_select_default_state(&fep->pdev->dev);
2770 ret = fec_enet_clk_enable(ndev, true);
2771 if (ret)
2772 return ret;
2773
2774 /* I should reset the ring buffers here, but I don't yet know
2775 * a simple way to do that.
2776 */
2777
2778 ret = fec_enet_alloc_buffers(ndev);
2779 if (ret)
2780 goto err_enet_alloc;
2781
2782 /* Probe and connect to PHY when open the interface */
2783 ret = fec_enet_mii_probe(ndev);
2784 if (ret)
2785 goto err_enet_mii_probe;
2786
2787 fec_restart(ndev);
2788 napi_enable(&fep->napi);
2789 phy_start(fep->phy_dev);
2790 netif_tx_start_all_queues(ndev);
2791
2792 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2793 FEC_WOL_FLAG_ENABLE);
2794
2795 return 0;
2796
2797 err_enet_mii_probe:
2798 fec_enet_free_buffers(ndev);
2799 err_enet_alloc:
2800 fec_enet_clk_enable(ndev, false);
2801 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2802 return ret;
2803 }
2804
2805 static int
fec_enet_close(struct net_device * ndev)2806 fec_enet_close(struct net_device *ndev)
2807 {
2808 struct fec_enet_private *fep = netdev_priv(ndev);
2809
2810 phy_stop(fep->phy_dev);
2811
2812 if (netif_device_present(ndev)) {
2813 napi_disable(&fep->napi);
2814 netif_tx_disable(ndev);
2815 fec_stop(ndev);
2816 }
2817
2818 phy_disconnect(fep->phy_dev);
2819 fep->phy_dev = NULL;
2820
2821 fec_enet_clk_enable(ndev, false);
2822 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2823 fec_enet_free_buffers(ndev);
2824
2825 return 0;
2826 }
2827
2828 /* Set or clear the multicast filter for this adaptor.
2829 * Skeleton taken from sunlance driver.
2830 * The CPM Ethernet implementation allows Multicast as well as individual
2831 * MAC address filtering. Some of the drivers check to make sure it is
2832 * a group multicast address, and discard those that are not. I guess I
2833 * will do the same for now, but just remove the test if you want
2834 * individual filtering as well (do the upper net layers want or support
2835 * this kind of feature?).
2836 */
2837
2838 #define HASH_BITS 6 /* #bits in hash */
2839 #define CRC32_POLY 0xEDB88320
2840
set_multicast_list(struct net_device * ndev)2841 static void set_multicast_list(struct net_device *ndev)
2842 {
2843 struct fec_enet_private *fep = netdev_priv(ndev);
2844 struct netdev_hw_addr *ha;
2845 unsigned int i, bit, data, crc, tmp;
2846 unsigned char hash;
2847
2848 if (ndev->flags & IFF_PROMISC) {
2849 tmp = readl(fep->hwp + FEC_R_CNTRL);
2850 tmp |= 0x8;
2851 writel(tmp, fep->hwp + FEC_R_CNTRL);
2852 return;
2853 }
2854
2855 tmp = readl(fep->hwp + FEC_R_CNTRL);
2856 tmp &= ~0x8;
2857 writel(tmp, fep->hwp + FEC_R_CNTRL);
2858
2859 if (ndev->flags & IFF_ALLMULTI) {
2860 /* Catch all multicast addresses, so set the
2861 * filter to all 1's
2862 */
2863 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2864 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2865
2866 return;
2867 }
2868
2869 /* Clear filter and add the addresses in hash register
2870 */
2871 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2872 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2873
2874 netdev_for_each_mc_addr(ha, ndev) {
2875 /* calculate crc32 value of mac address */
2876 crc = 0xffffffff;
2877
2878 for (i = 0; i < ndev->addr_len; i++) {
2879 data = ha->addr[i];
2880 for (bit = 0; bit < 8; bit++, data >>= 1) {
2881 crc = (crc >> 1) ^
2882 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2883 }
2884 }
2885
2886 /* only upper 6 bits (HASH_BITS) are used
2887 * which point to specific bit in he hash registers
2888 */
2889 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2890
2891 if (hash > 31) {
2892 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2893 tmp |= 1 << (hash - 32);
2894 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2895 } else {
2896 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2897 tmp |= 1 << hash;
2898 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2899 }
2900 }
2901 }
2902
2903 /* Set a MAC change in hardware. */
2904 static int
fec_set_mac_address(struct net_device * ndev,void * p)2905 fec_set_mac_address(struct net_device *ndev, void *p)
2906 {
2907 struct fec_enet_private *fep = netdev_priv(ndev);
2908 struct sockaddr *addr = p;
2909
2910 if (addr) {
2911 if (!is_valid_ether_addr(addr->sa_data))
2912 return -EADDRNOTAVAIL;
2913 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2914 }
2915
2916 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2917 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2918 fep->hwp + FEC_ADDR_LOW);
2919 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2920 fep->hwp + FEC_ADDR_HIGH);
2921 return 0;
2922 }
2923
2924 #ifdef CONFIG_NET_POLL_CONTROLLER
2925 /**
2926 * fec_poll_controller - FEC Poll controller function
2927 * @dev: The FEC network adapter
2928 *
2929 * Polled functionality used by netconsole and others in non interrupt mode
2930 *
2931 */
fec_poll_controller(struct net_device * dev)2932 static void fec_poll_controller(struct net_device *dev)
2933 {
2934 int i;
2935 struct fec_enet_private *fep = netdev_priv(dev);
2936
2937 for (i = 0; i < FEC_IRQ_NUM; i++) {
2938 if (fep->irq[i] > 0) {
2939 disable_irq(fep->irq[i]);
2940 fec_enet_interrupt(fep->irq[i], dev);
2941 enable_irq(fep->irq[i]);
2942 }
2943 }
2944 }
2945 #endif
2946
2947 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
fec_enet_set_netdev_features(struct net_device * netdev,netdev_features_t features)2948 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
2949 netdev_features_t features)
2950 {
2951 struct fec_enet_private *fep = netdev_priv(netdev);
2952 netdev_features_t changed = features ^ netdev->features;
2953
2954 netdev->features = features;
2955
2956 /* Receive checksum has been changed */
2957 if (changed & NETIF_F_RXCSUM) {
2958 if (features & NETIF_F_RXCSUM)
2959 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2960 else
2961 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2962 }
2963 }
2964
fec_set_features(struct net_device * netdev,netdev_features_t features)2965 static int fec_set_features(struct net_device *netdev,
2966 netdev_features_t features)
2967 {
2968 struct fec_enet_private *fep = netdev_priv(netdev);
2969 netdev_features_t changed = features ^ netdev->features;
2970
2971 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
2972 napi_disable(&fep->napi);
2973 netif_tx_lock_bh(netdev);
2974 fec_stop(netdev);
2975 fec_enet_set_netdev_features(netdev, features);
2976 fec_restart(netdev);
2977 netif_tx_wake_all_queues(netdev);
2978 netif_tx_unlock_bh(netdev);
2979 napi_enable(&fep->napi);
2980 } else {
2981 fec_enet_set_netdev_features(netdev, features);
2982 }
2983
2984 return 0;
2985 }
2986
2987 static const struct net_device_ops fec_netdev_ops = {
2988 .ndo_open = fec_enet_open,
2989 .ndo_stop = fec_enet_close,
2990 .ndo_start_xmit = fec_enet_start_xmit,
2991 .ndo_set_rx_mode = set_multicast_list,
2992 .ndo_change_mtu = eth_change_mtu,
2993 .ndo_validate_addr = eth_validate_addr,
2994 .ndo_tx_timeout = fec_timeout,
2995 .ndo_set_mac_address = fec_set_mac_address,
2996 .ndo_do_ioctl = fec_enet_ioctl,
2997 #ifdef CONFIG_NET_POLL_CONTROLLER
2998 .ndo_poll_controller = fec_poll_controller,
2999 #endif
3000 .ndo_set_features = fec_set_features,
3001 };
3002
3003 /*
3004 * XXX: We need to clean up on failure exits here.
3005 *
3006 */
fec_enet_init(struct net_device * ndev)3007 static int fec_enet_init(struct net_device *ndev)
3008 {
3009 struct fec_enet_private *fep = netdev_priv(ndev);
3010 struct fec_enet_priv_tx_q *txq;
3011 struct fec_enet_priv_rx_q *rxq;
3012 struct bufdesc *cbd_base;
3013 dma_addr_t bd_dma;
3014 int bd_size;
3015 unsigned int i;
3016
3017 #if defined(CONFIG_ARM)
3018 fep->rx_align = 0xf;
3019 fep->tx_align = 0xf;
3020 #else
3021 fep->rx_align = 0x3;
3022 fep->tx_align = 0x3;
3023 #endif
3024
3025 fec_enet_alloc_queue(ndev);
3026
3027 if (fep->bufdesc_ex)
3028 fep->bufdesc_size = sizeof(struct bufdesc_ex);
3029 else
3030 fep->bufdesc_size = sizeof(struct bufdesc);
3031 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
3032 fep->bufdesc_size;
3033
3034 /* Allocate memory for buffer descriptors. */
3035 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma,
3036 GFP_KERNEL);
3037 if (!cbd_base) {
3038 return -ENOMEM;
3039 }
3040
3041 memset(cbd_base, 0, bd_size);
3042
3043 /* Get the Ethernet address */
3044 fec_get_mac(ndev);
3045 /* make sure MAC we just acquired is programmed into the hw */
3046 fec_set_mac_address(ndev, NULL);
3047
3048 /* Set receive and transmit descriptor base. */
3049 for (i = 0; i < fep->num_rx_queues; i++) {
3050 rxq = fep->rx_queue[i];
3051 rxq->index = i;
3052 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
3053 rxq->bd_dma = bd_dma;
3054 if (fep->bufdesc_ex) {
3055 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
3056 cbd_base = (struct bufdesc *)
3057 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
3058 } else {
3059 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
3060 cbd_base += rxq->rx_ring_size;
3061 }
3062 }
3063
3064 for (i = 0; i < fep->num_tx_queues; i++) {
3065 txq = fep->tx_queue[i];
3066 txq->index = i;
3067 txq->tx_bd_base = (struct bufdesc *)cbd_base;
3068 txq->bd_dma = bd_dma;
3069 if (fep->bufdesc_ex) {
3070 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
3071 cbd_base = (struct bufdesc *)
3072 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
3073 } else {
3074 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
3075 cbd_base += txq->tx_ring_size;
3076 }
3077 }
3078
3079
3080 /* The FEC Ethernet specific entries in the device structure */
3081 ndev->watchdog_timeo = TX_TIMEOUT;
3082 ndev->netdev_ops = &fec_netdev_ops;
3083 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3084
3085 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3086 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3087
3088 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3089 /* enable hw VLAN support */
3090 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3091
3092 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3093 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3094
3095 /* enable hw accelerator */
3096 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3097 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3098 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3099 }
3100
3101 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3102 fep->tx_align = 0;
3103 fep->rx_align = 0x3f;
3104 }
3105
3106 ndev->hw_features = ndev->features;
3107
3108 fec_restart(ndev);
3109
3110 return 0;
3111 }
3112
3113 #ifdef CONFIG_OF
fec_reset_phy(struct platform_device * pdev)3114 static void fec_reset_phy(struct platform_device *pdev)
3115 {
3116 int err, phy_reset;
3117 int msec = 1;
3118 struct device_node *np = pdev->dev.of_node;
3119
3120 if (!np)
3121 return;
3122
3123 of_property_read_u32(np, "phy-reset-duration", &msec);
3124 /* A sane reset duration should not be longer than 1s */
3125 if (msec > 1000)
3126 msec = 1;
3127
3128 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3129 if (!gpio_is_valid(phy_reset))
3130 return;
3131
3132 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3133 GPIOF_OUT_INIT_LOW, "phy-reset");
3134 if (err) {
3135 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3136 return;
3137 }
3138 msleep(msec);
3139 gpio_set_value(phy_reset, 1);
3140 }
3141 #else /* CONFIG_OF */
fec_reset_phy(struct platform_device * pdev)3142 static void fec_reset_phy(struct platform_device *pdev)
3143 {
3144 /*
3145 * In case of platform probe, the reset has been done
3146 * by machine code.
3147 */
3148 }
3149 #endif /* CONFIG_OF */
3150
3151 static void
fec_enet_get_queue_num(struct platform_device * pdev,int * num_tx,int * num_rx)3152 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3153 {
3154 struct device_node *np = pdev->dev.of_node;
3155 int err;
3156
3157 *num_tx = *num_rx = 1;
3158
3159 if (!np || !of_device_is_available(np))
3160 return;
3161
3162 /* parse the num of tx and rx queues */
3163 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3164 if (err)
3165 *num_tx = 1;
3166
3167 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3168 if (err)
3169 *num_rx = 1;
3170
3171 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3172 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3173 *num_tx);
3174 *num_tx = 1;
3175 return;
3176 }
3177
3178 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3179 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3180 *num_rx);
3181 *num_rx = 1;
3182 return;
3183 }
3184
3185 }
3186
3187 static int
fec_probe(struct platform_device * pdev)3188 fec_probe(struct platform_device *pdev)
3189 {
3190 struct fec_enet_private *fep;
3191 struct fec_platform_data *pdata;
3192 struct net_device *ndev;
3193 int i, irq, ret = 0;
3194 struct resource *r;
3195 const struct of_device_id *of_id;
3196 static int dev_id;
3197 struct device_node *np = pdev->dev.of_node, *phy_node;
3198 int num_tx_qs;
3199 int num_rx_qs;
3200
3201 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3202
3203 /* Init network device */
3204 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3205 num_tx_qs, num_rx_qs);
3206 if (!ndev)
3207 return -ENOMEM;
3208
3209 SET_NETDEV_DEV(ndev, &pdev->dev);
3210
3211 /* setup board info structure */
3212 fep = netdev_priv(ndev);
3213
3214 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3215 if (of_id)
3216 pdev->id_entry = of_id->data;
3217 fep->quirks = pdev->id_entry->driver_data;
3218
3219 fep->netdev = ndev;
3220 fep->num_rx_queues = num_rx_qs;
3221 fep->num_tx_queues = num_tx_qs;
3222
3223 #if !defined(CONFIG_M5272)
3224 /* default enable pause frame auto negotiation */
3225 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3226 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3227 #endif
3228
3229 /* Select default pin state */
3230 pinctrl_pm_select_default_state(&pdev->dev);
3231
3232 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3233 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3234 if (IS_ERR(fep->hwp)) {
3235 ret = PTR_ERR(fep->hwp);
3236 goto failed_ioremap;
3237 }
3238
3239 fep->pdev = pdev;
3240 fep->dev_id = dev_id++;
3241
3242 platform_set_drvdata(pdev, ndev);
3243
3244 if (of_get_property(np, "fsl,magic-packet", NULL))
3245 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3246
3247 phy_node = of_parse_phandle(np, "phy-handle", 0);
3248 if (!phy_node && of_phy_is_fixed_link(np)) {
3249 ret = of_phy_register_fixed_link(np);
3250 if (ret < 0) {
3251 dev_err(&pdev->dev,
3252 "broken fixed-link specification\n");
3253 goto failed_phy;
3254 }
3255 phy_node = of_node_get(np);
3256 }
3257 fep->phy_node = phy_node;
3258
3259 ret = of_get_phy_mode(pdev->dev.of_node);
3260 if (ret < 0) {
3261 pdata = dev_get_platdata(&pdev->dev);
3262 if (pdata)
3263 fep->phy_interface = pdata->phy;
3264 else
3265 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3266 } else {
3267 fep->phy_interface = ret;
3268 }
3269
3270 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3271 if (IS_ERR(fep->clk_ipg)) {
3272 ret = PTR_ERR(fep->clk_ipg);
3273 goto failed_clk;
3274 }
3275
3276 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3277 if (IS_ERR(fep->clk_ahb)) {
3278 ret = PTR_ERR(fep->clk_ahb);
3279 goto failed_clk;
3280 }
3281
3282 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3283
3284 /* enet_out is optional, depends on board */
3285 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3286 if (IS_ERR(fep->clk_enet_out))
3287 fep->clk_enet_out = NULL;
3288
3289 fep->ptp_clk_on = false;
3290 mutex_init(&fep->ptp_clk_mutex);
3291
3292 /* clk_ref is optional, depends on board */
3293 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3294 if (IS_ERR(fep->clk_ref))
3295 fep->clk_ref = NULL;
3296
3297 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3298 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3299 if (IS_ERR(fep->clk_ptp)) {
3300 fep->clk_ptp = NULL;
3301 fep->bufdesc_ex = false;
3302 }
3303
3304 ret = fec_enet_clk_enable(ndev, true);
3305 if (ret)
3306 goto failed_clk;
3307
3308 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3309 if (!IS_ERR(fep->reg_phy)) {
3310 ret = regulator_enable(fep->reg_phy);
3311 if (ret) {
3312 dev_err(&pdev->dev,
3313 "Failed to enable phy regulator: %d\n", ret);
3314 goto failed_regulator;
3315 }
3316 } else {
3317 fep->reg_phy = NULL;
3318 }
3319
3320 fec_reset_phy(pdev);
3321
3322 if (fep->bufdesc_ex)
3323 fec_ptp_init(pdev);
3324
3325 ret = fec_enet_init(ndev);
3326 if (ret)
3327 goto failed_init;
3328
3329 for (i = 0; i < FEC_IRQ_NUM; i++) {
3330 irq = platform_get_irq(pdev, i);
3331 if (irq < 0) {
3332 if (i)
3333 break;
3334 ret = irq;
3335 goto failed_irq;
3336 }
3337 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3338 0, pdev->name, ndev);
3339 if (ret)
3340 goto failed_irq;
3341
3342 fep->irq[i] = irq;
3343 }
3344
3345 init_completion(&fep->mdio_done);
3346 ret = fec_enet_mii_init(pdev);
3347 if (ret)
3348 goto failed_mii_init;
3349
3350 /* Carrier starts down, phylib will bring it up */
3351 netif_carrier_off(ndev);
3352 fec_enet_clk_enable(ndev, false);
3353 pinctrl_pm_select_sleep_state(&pdev->dev);
3354
3355 ret = register_netdev(ndev);
3356 if (ret)
3357 goto failed_register;
3358
3359 device_init_wakeup(&ndev->dev, fep->wol_flag &
3360 FEC_WOL_HAS_MAGIC_PACKET);
3361
3362 if (fep->bufdesc_ex && fep->ptp_clock)
3363 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3364
3365 fep->rx_copybreak = COPYBREAK_DEFAULT;
3366 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3367 return 0;
3368
3369 failed_register:
3370 fec_enet_mii_remove(fep);
3371 failed_mii_init:
3372 failed_irq:
3373 failed_init:
3374 if (fep->reg_phy)
3375 regulator_disable(fep->reg_phy);
3376 failed_regulator:
3377 fec_enet_clk_enable(ndev, false);
3378 failed_clk:
3379 failed_phy:
3380 of_node_put(phy_node);
3381 failed_ioremap:
3382 free_netdev(ndev);
3383
3384 return ret;
3385 }
3386
3387 static int
fec_drv_remove(struct platform_device * pdev)3388 fec_drv_remove(struct platform_device *pdev)
3389 {
3390 struct net_device *ndev = platform_get_drvdata(pdev);
3391 struct fec_enet_private *fep = netdev_priv(ndev);
3392
3393 cancel_delayed_work_sync(&fep->time_keep);
3394 cancel_work_sync(&fep->tx_timeout_work);
3395 unregister_netdev(ndev);
3396 fec_enet_mii_remove(fep);
3397 if (fep->reg_phy)
3398 regulator_disable(fep->reg_phy);
3399 if (fep->ptp_clock)
3400 ptp_clock_unregister(fep->ptp_clock);
3401 of_node_put(fep->phy_node);
3402 free_netdev(ndev);
3403
3404 return 0;
3405 }
3406
fec_suspend(struct device * dev)3407 static int __maybe_unused fec_suspend(struct device *dev)
3408 {
3409 struct net_device *ndev = dev_get_drvdata(dev);
3410 struct fec_enet_private *fep = netdev_priv(ndev);
3411
3412 rtnl_lock();
3413 if (netif_running(ndev)) {
3414 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3415 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3416 phy_stop(fep->phy_dev);
3417 napi_disable(&fep->napi);
3418 netif_tx_lock_bh(ndev);
3419 netif_device_detach(ndev);
3420 netif_tx_unlock_bh(ndev);
3421 fec_stop(ndev);
3422 fec_enet_clk_enable(ndev, false);
3423 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3424 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3425 }
3426 rtnl_unlock();
3427
3428 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3429 regulator_disable(fep->reg_phy);
3430
3431 /* SOC supply clock to phy, when clock is disabled, phy link down
3432 * SOC control phy regulator, when regulator is disabled, phy link down
3433 */
3434 if (fep->clk_enet_out || fep->reg_phy)
3435 fep->link = 0;
3436
3437 return 0;
3438 }
3439
fec_resume(struct device * dev)3440 static int __maybe_unused fec_resume(struct device *dev)
3441 {
3442 struct net_device *ndev = dev_get_drvdata(dev);
3443 struct fec_enet_private *fep = netdev_priv(ndev);
3444 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3445 int ret;
3446 int val;
3447
3448 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3449 ret = regulator_enable(fep->reg_phy);
3450 if (ret)
3451 return ret;
3452 }
3453
3454 rtnl_lock();
3455 if (netif_running(ndev)) {
3456 ret = fec_enet_clk_enable(ndev, true);
3457 if (ret) {
3458 rtnl_unlock();
3459 goto failed_clk;
3460 }
3461 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3462 if (pdata && pdata->sleep_mode_enable)
3463 pdata->sleep_mode_enable(false);
3464 val = readl(fep->hwp + FEC_ECNTRL);
3465 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3466 writel(val, fep->hwp + FEC_ECNTRL);
3467 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3468 } else {
3469 pinctrl_pm_select_default_state(&fep->pdev->dev);
3470 }
3471 fec_restart(ndev);
3472 netif_tx_lock_bh(ndev);
3473 netif_device_attach(ndev);
3474 netif_tx_unlock_bh(ndev);
3475 napi_enable(&fep->napi);
3476 phy_start(fep->phy_dev);
3477 }
3478 rtnl_unlock();
3479
3480 return 0;
3481
3482 failed_clk:
3483 if (fep->reg_phy)
3484 regulator_disable(fep->reg_phy);
3485 return ret;
3486 }
3487
3488 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
3489
3490 static struct platform_driver fec_driver = {
3491 .driver = {
3492 .name = DRIVER_NAME,
3493 .pm = &fec_pm_ops,
3494 .of_match_table = fec_dt_ids,
3495 },
3496 .id_table = fec_devtype,
3497 .probe = fec_probe,
3498 .remove = fec_drv_remove,
3499 };
3500
3501 module_platform_driver(fec_driver);
3502
3503 MODULE_ALIAS("platform:"DRIVER_NAME);
3504 MODULE_LICENSE("GPL");
3505