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Searched refs:divider (Results 1 – 177 of 177) sorted by relevance

/linux-4.4.14/drivers/clk/tegra/
Dclk-divider.c32 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, in get_div() argument
36 u8 flags = divider->flags; in get_div()
42 mul = get_mul(divider); in get_div()
60 if (divider_ux1 > get_max_div(divider)) in get_div()
61 return get_max_div(divider); in get_div()
69 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local
74 reg = readl_relaxed(divider->reg) >> divider->shift; in clk_frac_div_recalc_rate()
75 div = reg & div_mask(divider); in clk_frac_div_recalc_rate()
77 mul = get_mul(divider); in clk_frac_div_recalc_rate()
90 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_round_rate() local
[all …]
Dclk-periph.c51 struct clk_hw *div_hw = &periph->divider.hw; in clk_periph_recalc_rate()
63 struct clk_hw *div_hw = &periph->divider.hw; in clk_periph_round_rate()
75 struct clk_hw *div_hw = &periph->divider.hw; in clk_periph_set_rate()
172 periph->divider.reg = div ? (clk_base + offset) : NULL; in _tegra_clk_register_periph()
182 periph->divider.hw.clk = div ? clk : NULL; in _tegra_clk_register_periph()
DMakefile4 obj-y += clk-divider.o
Dclk.h446 struct tegra_clk_frac_div divider; member
480 .divider = { \
/linux-4.4.14/drivers/clk/qcom/
Dclk-regmap-divider.c29 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_rate() local
31 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate()
38 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_set_rate() local
39 struct clk_regmap *clkr = &divider->clkr; in div_set_rate()
42 div = divider_get_val(rate, parent_rate, NULL, divider->width, in div_set_rate()
45 return regmap_update_bits(clkr->regmap, divider->reg, in div_set_rate()
46 (BIT(divider->width) - 1) << divider->shift, in div_set_rate()
47 div << divider->shift); in div_set_rate()
53 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_recalc_rate() local
54 struct clk_regmap *clkr = &divider->clkr; in div_recalc_rate()
[all …]
DMakefile9 clk-qcom-y += clk-regmap-divider.o
/linux-4.4.14/drivers/clk/ti/
Ddivider.c44 static unsigned int _get_maxdiv(struct clk_divider *divider) in _get_maxdiv() argument
46 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_maxdiv()
47 return div_mask(divider); in _get_maxdiv()
48 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _get_maxdiv()
49 return 1 << div_mask(divider); in _get_maxdiv()
50 if (divider->table) in _get_maxdiv()
51 return _get_table_maxdiv(divider->table); in _get_maxdiv()
52 return div_mask(divider) + 1; in _get_maxdiv()
66 static unsigned int _get_div(struct clk_divider *divider, unsigned int val) in _get_div() argument
68 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_div()
[all …]
Dclk-dra7-atl.c54 u32 divider; /* Cached divider value */ member
90 cdesc->divider - 1); in atl_clk_enable()
125 return parent_rate / cdesc->divider; in atl_clk_recalc_rate()
131 unsigned divider; in atl_clk_round_rate() local
133 divider = (*parent_rate + rate / 2) / rate; in atl_clk_round_rate()
134 if (divider > DRA7_ATL_DIVIDER_MASK + 1) in atl_clk_round_rate()
135 divider = DRA7_ATL_DIVIDER_MASK + 1; in atl_clk_round_rate()
137 return *parent_rate / divider; in atl_clk_round_rate()
144 u32 divider; in atl_clk_set_rate() local
150 divider = ((parent_rate + rate / 2) / rate) - 1; in atl_clk_set_rate()
[all …]
Dcomposite.c134 div = ti_clk_build_component_div(comp->divider); in ti_clk_register_composite()
139 parent_names = &comp->divider->parent; in ti_clk_register_composite()
DMakefile2 clk-common = dpll.o composite.o divider.o gate.o \
Dclock.h120 struct ti_clk_divider *divider; member
Dclk-3xxx-legacy.c718 .divider = &ssi_ssr_div_fck_3430es1_data,
1607 .divider = &usb_l4_div_ick_data,
3287 .divider = &ssi_ssr_div_fck_3430es2_data,
/linux-4.4.14/drivers/clk/mxs/
Dclk-div.c28 struct clk_divider divider; member
36 struct clk_divider *divider = container_of(hw, struct clk_divider, hw); in to_clk_div() local
38 return container_of(divider, struct clk_div, divider); in to_clk_div()
46 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
54 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
63 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
96 div->divider.reg = reg; in mxs_clk_div()
97 div->divider.shift = shift; in mxs_clk_div()
98 div->divider.width = width; in mxs_clk_div()
99 div->divider.flags = CLK_DIVIDER_ONE_BASED; in mxs_clk_div()
[all …]
/linux-4.4.14/drivers/clk/imx/
Dclk-fixup-div.c31 struct clk_divider divider; member
38 struct clk_divider *divider = to_clk_div(hw); in to_clk_fixup_div() local
40 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
48 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); in clk_fixup_div_recalc_rate()
56 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); in clk_fixup_div_round_rate()
64 unsigned int divider, value; in clk_fixup_div_set_rate() local
68 divider = parent_rate / rate; in clk_fixup_div_set_rate()
71 value = divider - 1; in clk_fixup_div_set_rate()
116 fixup_div->divider.reg = reg; in imx_clk_fixup_divider()
117 fixup_div->divider.shift = shift; in imx_clk_fixup_divider()
[all …]
/linux-4.4.14/drivers/clk/
Dclk-divider.c124 struct clk_divider *divider = to_clk_divider(hw); in divider_recalc_rate() local
127 div = _get_div(table, val, flags, divider->width); in divider_recalc_rate()
142 struct clk_divider *divider = to_clk_divider(hw); in clk_divider_recalc_rate() local
145 val = clk_readl(divider->reg) >> divider->shift; in clk_divider_recalc_rate()
146 val &= div_mask(divider->width); in clk_divider_recalc_rate()
148 return divider_recalc_rate(hw, parent_rate, val, divider->table, in clk_divider_recalc_rate()
149 divider->flags); in clk_divider_recalc_rate()
352 struct clk_divider *divider = to_clk_divider(hw); in clk_divider_round_rate() local
356 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in clk_divider_round_rate()
357 bestdiv = readl(divider->reg) >> divider->shift; in clk_divider_round_rate()
[all …]
Dclk-cdce925.c340 unsigned long divider; in cdce925_calc_divider() local
347 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in cdce925_calc_divider()
348 if (divider > 0x7F) in cdce925_calc_divider()
349 divider = 0x7F; in cdce925_calc_divider()
351 return (u16)divider; in cdce925_calc_divider()
401 u16 divider = cdce925_calc_divider(rate, l_parent_rate); in cdce925_clk_round_rate() local
403 if (l_parent_rate / divider != rate) { in cdce925_clk_round_rate()
405 divider = cdce925_calc_divider(rate, l_parent_rate); in cdce925_clk_round_rate()
409 if (divider) in cdce925_clk_round_rate()
410 return (long)(l_parent_rate / divider); in cdce925_clk_round_rate()
[all …]
Dclk-xgene.c337 u32 divider; in xgene_clk_set_rate() local
347 divider_save = divider = parent_rate / rate; /* Rounded down */ in xgene_clk_set_rate()
348 divider &= (1 << pclk->param.reg_divider_width) - 1; in xgene_clk_set_rate()
349 divider <<= pclk->param.reg_divider_shift; in xgene_clk_set_rate()
355 data |= divider; in xgene_clk_set_rate()
375 u32 divider; in xgene_clk_round_rate() local
381 divider = parent_rate / rate; /* Rounded down */ in xgene_clk_round_rate()
383 divider = 1; in xgene_clk_round_rate()
386 return parent_rate / divider; in xgene_clk_round_rate()
Dclk-cdce706.c90 struct cdce706_hw_data divider[6]; member
568 for (i = 0; i < ARRAY_SIZE(cdce->divider); ++i) { in cdce706_register_dividers()
574 cdce->divider[i].parent = in cdce706_register_dividers()
581 cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK; in cdce706_register_dividers()
584 cdce->divider[i].parent, cdce->divider[i].div); in cdce706_register_dividers()
587 ret = cdce706_register_hw(cdce, cdce->divider, in cdce706_register_dividers()
588 ARRAY_SIZE(cdce->divider), in cdce706_register_dividers()
Dclk-axi-clkgen.c185 static void axi_clkgen_calc_clk_params(unsigned int divider, unsigned int *low, in axi_clkgen_calc_clk_params() argument
188 if (divider == 1) in axi_clkgen_calc_clk_params()
193 *high = divider / 2; in axi_clkgen_calc_clk_params()
194 *edge = divider % 2; in axi_clkgen_calc_clk_params()
195 *low = divider - *high; in axi_clkgen_calc_clk_params()
DMakefile5 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
12 obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o
DKconfig117 divider to best approximate the desired output.
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dxgene.txt25 reset and/or the divider. Either may be omitted, but at least
43 - divider-offset : Offset to the divider CSR register from the divider base.
45 - divider-width : Width of the divider register. Default is 0.
46 - divider-shift : Bit shift of the divider register. Default is 0.
87 divider-offset = <0x238>;
88 divider-width = <0x9>;
89 divider-shift = <0x0>;
105 divider-offset = <0x10>;
106 divider-width = <0x2>;
107 divider-shift = <0x0>;
Dkeystone-pll.txt4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
29 reg-names = "control", "multiplier", "post-divider";
66 - compatible : shall be "ti,keystone,pll-divider-clock"
70 - bit-mask : arbitrary bitmask for programming the divider
78 compatible = "ti,keystone,pll-divider-clock";
Dnspire-clock.txt5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
Dsilabs,si5351.txt39 - silabs,clock-source: source clock of the output divider stage N, shall be
46 divider.
84 * - multisynth0 as clock source of output divider
101 * - multisynth1 as clock source of output divider
114 * - xtal as clock source of output divider
Daltr_socfpga.txt21 - fixed-divider : If clocks have a fixed divider value, use this property.
25 the divider register, bit shift, and width.
Drenesas,h8300-div-clock.txt1 * Renesas H8/300 divider clock
Dfixed-factor-clock.txt10 - clock-div: fixed divider.
Dzx296702-clk.txt10 zx296702 top clock selection, divider and gating
Dti,cdce706.txt2 synthesizer/multiplier/divider.
Demev2-clock.txt14 Function block with an input mux and a divider, which corresponds to
/linux-4.4.14/Documentation/devicetree/bindings/clock/ti/
Ddivider.txt1 Binding for TI divider clock
6 register-mapped adjustable clock rate divider that does not gate and has
44 The binding must also provide the register to control the divider and
45 unless the divider array is provided, min and max dividers. Optionally
56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
59 - reg : offset for register controlling adjustable divider
64 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
82 compatible = "ti,divider-clock";
91 compatible = "ti,divider-clock";
100 compatible = "ti,composite-divider-clock";
[all …]
Dcomposite.txt11 an adjustable clock rate divider, this behaves exactly as [3]
22 [3] Documentation/devicetree/bindings/clock/ti/divider.txt
42 compatible = "ti,composite-divider-clock";
Dautoidle.txt8 clock, it is always a derivative of some basic clock like a gate, divider,
21 compatible = "ti,divider-clock";
Dfixed-factor-clock.txt14 - ti,clock-div: fixed divider.
Dmux.txt8 gate or adjust the parent rate via a divider or multiplier.
Ddpll.txt43 "mult-div1" - contains the multiplier / divider register base address
/linux-4.4.14/drivers/media/i2c/cx25840/
Dcx25840-ir.c159 static inline unsigned int clock_divider_to_ns(unsigned int divider) in clock_divider_to_ns() argument
162 return DIV_ROUND_CLOSEST((divider + 1) * 1000, in clock_divider_to_ns()
172 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
174 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
184 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
188 (divider + 1) * rollovers); in clock_divider_to_freq()
229 static u32 clock_divider_to_resolution(u16 divider) in clock_divider_to_resolution() argument
236 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, in clock_divider_to_resolution()
240 static u64 pulse_width_count_to_ns(u16 count, u16 divider) in pulse_width_count_to_ns() argument
249 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ in pulse_width_count_to_ns()
[all …]
/linux-4.4.14/drivers/media/pci/cx23885/
Dcx23888-ir.c193 static inline unsigned int clock_divider_to_ns(unsigned int divider) in clock_divider_to_ns() argument
196 return DIV_ROUND_CLOSEST((divider + 1) * 1000, in clock_divider_to_ns()
206 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
208 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
218 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
222 (divider + 1) * rollovers); in clock_divider_to_freq()
263 static u32 clock_divider_to_resolution(u16 divider) in clock_divider_to_resolution() argument
270 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, in clock_divider_to_resolution()
274 static u64 pulse_width_count_to_ns(u16 count, u16 divider) in pulse_width_count_to_ns() argument
283 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ in pulse_width_count_to_ns()
[all …]
/linux-4.4.14/arch/arm/boot/dts/
Ddm816x-clocks.dtsi99 compatible = "ti,divider-clock";
117 compatible = "ti,divider-clock";
125 compatible = "ti,divider-clock";
133 compatible = "ti,divider-clock";
141 compatible = "ti,divider-clock";
149 compatible = "ti,divider-clock";
157 compatible = "ti,divider-clock";
165 compatible = "ti,divider-clock";
173 compatible = "ti,divider-clock";
189 compatible = "ti,divider-clock";
Domap54xx-clocks.dtsi120 compatible = "ti,divider-clock";
137 compatible = "ti,divider-clock";
146 compatible = "ti,divider-clock";
163 compatible = "ti,divider-clock";
193 compatible = "ti,divider-clock";
218 compatible = "ti,divider-clock";
227 compatible = "ti,divider-clock";
236 compatible = "ti,divider-clock";
245 compatible = "ti,divider-clock";
254 compatible = "ti,divider-clock";
[all …]
Ddra7xx-clocks.dtsi206 compatible = "ti,divider-clock";
217 compatible = "ti,divider-clock";
226 compatible = "ti,divider-clock";
237 compatible = "ti,divider-clock";
269 compatible = "ti,divider-clock";
295 compatible = "ti,divider-clock";
337 compatible = "ti,divider-clock";
371 compatible = "ti,divider-clock";
405 compatible = "ti,divider-clock";
416 compatible = "ti,divider-clock";
[all …]
Domap44xx-clocks.dtsi151 compatible = "ti,divider-clock";
170 compatible = "ti,divider-clock";
179 compatible = "ti,divider-clock";
188 compatible = "ti,divider-clock";
220 compatible = "ti,divider-clock";
231 compatible = "ti,divider-clock";
250 compatible = "ti,divider-clock";
261 compatible = "ti,divider-clock";
269 compatible = "ti,divider-clock";
278 compatible = "ti,divider-clock";
[all …]
Dam33xx-clocks.dtsi181 compatible = "ti,divider-clock";
190 compatible = "ti,divider-clock";
199 compatible = "ti,divider-clock";
215 compatible = "ti,divider-clock";
231 compatible = "ti,divider-clock";
255 compatible = "ti,divider-clock";
272 compatible = "ti,divider-clock";
558 compatible = "ti,divider-clock";
573 compatible = "ti,divider-clock";
614 compatible = "ti,divider-clock";
[all …]
Dam43xx-clocks.dtsi213 compatible = "ti,divider-clock";
224 compatible = "ti,divider-clock";
235 compatible = "ti,divider-clock";
253 compatible = "ti,divider-clock";
279 compatible = "ti,divider-clock";
297 compatible = "ti,divider-clock";
316 compatible = "ti,divider-clock";
499 compatible = "ti,divider-clock";
585 compatible = "ti,divider-clock";
608 compatible = "ti,divider-clock";
[all …]
Domap3xxx-clocks.dtsi26 compatible = "ti,divider-clock";
205 compatible = "ti,divider-clock";
246 compatible = "ti,divider-clock";
293 compatible = "ti,divider-clock";
311 compatible = "ti,divider-clock";
336 compatible = "ti,divider-clock";
361 compatible = "ti,divider-clock";
420 compatible = "ti,divider-clock";
448 compatible = "ti,divider-clock";
476 compatible = "ti,divider-clock";
[all …]
Domap3430es1-clocks.dtsi21 compatible = "ti,divider-clock";
78 compatible = "ti,composite-divider-clock";
141 compatible = "ti,composite-divider-clock";
Domap2420-clocks.dtsi36 compatible = "ti,divider-clock";
54 compatible = "ti,composite-divider-clock";
78 compatible = "ti,composite-divider-clock";
Domap24xx-clocks.dtsi104 compatible = "ti,divider-clock";
218 compatible = "ti,divider-clock";
236 compatible = "ti,divider-clock";
253 compatible = "ti,composite-divider-clock";
266 compatible = "ti,divider-clock";
283 compatible = "ti,composite-divider-clock";
306 compatible = "ti,composite-divider-clock";
329 compatible = "ti,divider-clock";
485 compatible = "ti,composite-divider-clock";
507 compatible = "ti,composite-divider-clock";
Domap446x-clocks.dtsi13 compatible = "ti,divider-clock";
Dnspire-classic.dtsi51 compatible = "lsi,nspire-classic-ahb-divider";
Domap34xx-omap36xx-clocks.dtsi158 compatible = "ti,divider-clock";
178 compatible = "ti,divider-clock";
Dsocfpga.dtsi286 fixed-divider = <4>;
293 fixed-divider = <2>;
307 fixed-divider = <1>;
460 fixed-divider = <4>;
475 fixed-divider = <4>;
Dk2e-clocks.dtsi17 reg-names = "control", "multiplier", "post-divider";
Dnspire-cx.dts43 compatible = "lsi,nspire-cx-ahb-divider";
Domap2430-clocks.dtsi65 compatible = "ti,composite-divider-clock";
89 compatible = "ti,composite-divider-clock";
Dimx35-eukrea-mbimxsd35-baseboard.dts162 external-vbus-divider;
Dimx25-eukrea-mbimxsd25-baseboard.dts184 external-vbus-divider;
Dsocfpga_arria10.dtsi317 fixed-divider = <4>;
325 fixed-divider = <4>;
356 fixed-divider = <4>;
Dkeystone-clocks.dtsi46 compatible = "ti,keystone,pll-divider-clock";
56 compatible = "ti,keystone,pll-divider-clock";
Domap36xx-omap3430es2plus-clocks.dtsi21 compatible = "ti,composite-divider-clock";
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi39 compatible = "ti,divider-clock";
Dimx25-pdk.dts314 external-vbus-divider;
Dk2l-clocks.dtsi26 reg-names = "control", "multiplier", "post-divider";
Dk2hk-clocks.dtsi26 reg-names = "control", "multiplier", "post-divider";
/linux-4.4.14/Documentation/devicetree/bindings/regulator/
Dltc3589.txt17 - lltc,fb-voltage-divider: An array of two integers containing the resistor
18 values R1 and R2 of the feedback voltage divider in ohms.
39 lltc,fb-voltage-divider = <100000 158000>;
48 lltc,fb-voltage-divider = <180000 191000>;
57 lltc,fb-voltage-divider = <270000 100000>;
66 lltc,fb-voltage-divider = <511000 158000>;
74 lltc,fb-voltage-divider = <100000 158000>;
82 lltc,fb-voltage-divider = <180000 191000>;
/linux-4.4.14/sound/soc/omap/
Domap-dmic.c135 int divider = -EINVAL; in omap_dmic_select_divider() local
143 divider = 0x6; /* Divider: 5 (192KHz sampling rate) */ in omap_dmic_select_divider()
148 return divider; in omap_dmic_select_divider()
155 divider = 0x4; /* Divider: 16 */ in omap_dmic_select_divider()
160 divider = 0x5; /* Divider: 5 */ in omap_dmic_select_divider()
163 divider = 0x0; /* Divider: 8 */ in omap_dmic_select_divider()
166 divider = 0x2; /* Divider: 10 */ in omap_dmic_select_divider()
175 divider = 0x3; /* Divider: 8 */ in omap_dmic_select_divider()
180 divider = 0x1; /* Divider: 5 (96KHz sampling rate) */ in omap_dmic_select_divider()
188 return divider; in omap_dmic_select_divider()
Domap-mcbsp.c246 int divider = 0; in omap_mcbsp_dai_hw_params() local
260 divider = period_words / max_thrsh; in omap_mcbsp_dai_hw_params()
262 divider++; in omap_mcbsp_dai_hw_params()
263 while (period_words % divider && in omap_mcbsp_dai_hw_params()
264 divider < period_words) in omap_mcbsp_dai_hw_params()
265 divider++; in omap_mcbsp_dai_hw_params()
266 if (divider == period_words) in omap_mcbsp_dai_hw_params()
269 pkt_size = period_words / divider; in omap_mcbsp_dai_hw_params()
/linux-4.4.14/drivers/video/fbdev/aty/
Dmach64_gx.c505 short divider = 0, tempA; in aty_var_to_pll_1703() local
522 divider = 0; in aty_var_to_pll_1703()
525 divider += 0x20; in aty_var_to_pll_1703()
543 divider &= ~0x1f; in aty_var_to_pll_1703()
544 divider |= tempA; in aty_var_to_pll_1703()
545 divider = in aty_var_to_pll_1703()
546 (divider & 0x00ff) + in aty_var_to_pll_1703()
554 program_bits = divider; in aty_var_to_pll_1703()
559 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_1703()
745 short divider = 0, tempA; in aty_var_to_pll_408() local
[all …]
Dmach64_ct.c122 u32 multiplier, divider, ras_multiplier, ras_divider, tmp; in aty_dsp_gt() local
127 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; in aty_dsp_gt()
133 divider = divider * (bpp >> 2); in aty_dsp_gt()
145 divider = divider * pll->xres & ~7; in aty_dsp_gt()
153 while (((multiplier | divider) & 1) == 0) { in aty_dsp_gt()
155 divider = divider >> 1; in aty_dsp_gt()
159 tmp = ((multiplier * pll->fifo_size) << vshift) / divider; in aty_dsp_gt()
172 dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider - in aty_dsp_gt()
179 dsp_on = ((multiplier << vshift) + divider) / divider; in aty_dsp_gt()
191 dsp_on = dsp_off - (multiplier << vshift) / divider; in aty_dsp_gt()
[all …]
Dradeon_base.c1539 int divider; in radeon_calc_pll_regs() member
1610 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_calc_pll_regs()
1611 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1615 if (uses_dvo && (post_div->divider & 1)) in radeon_calc_pll_regs()
1624 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1626 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1634 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1636 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
/linux-4.4.14/drivers/i2c/busses/
Di2c-mxs.c698 uint32_t divider; in mxs_i2c_derive_timing() local
703 divider = DIV_ROUND_UP(clk, speed); in mxs_i2c_derive_timing()
705 if (divider < 25) { in mxs_i2c_derive_timing()
710 divider = 25; in mxs_i2c_derive_timing()
714 clk / divider / 1000, clk / divider % 1000); in mxs_i2c_derive_timing()
715 } else if (divider > 1897) { in mxs_i2c_derive_timing()
720 divider = 1897; in mxs_i2c_derive_timing()
724 clk / divider / 1000, clk / divider % 1000); in mxs_i2c_derive_timing()
743 low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6)); in mxs_i2c_derive_timing()
744 high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6)); in mxs_i2c_derive_timing()
[all …]
Di2c-bcm2835.c229 u32 bus_clk_rate, divider; in bcm2835_i2c_probe() local
259 divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk), bus_clk_rate); in bcm2835_i2c_probe()
265 if (divider & 1) in bcm2835_i2c_probe()
266 divider++; in bcm2835_i2c_probe()
267 if ((divider < BCM2835_I2C_CDIV_MIN) || in bcm2835_i2c_probe()
268 (divider > BCM2835_I2C_CDIV_MAX)) { in bcm2835_i2c_probe()
272 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider); in bcm2835_i2c_probe()
Di2c-mpc.c76 u16 divider; member
208 u32 divider; in mpc_i2c_get_fdr_52xx() local
218 divider = mpc5xxx_get_bus_frequency(node) / clock; in mpc_i2c_get_fdr_52xx()
229 if (div->divider >= divider) in mpc_i2c_get_fdr_52xx()
233 *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider; in mpc_i2c_get_fdr_52xx()
382 u32 divider; in mpc_i2c_get_fdr_8xxx() local
397 divider = fsl_get_sys_freq() / clock / prescaler; in mpc_i2c_get_fdr_8xxx()
400 fsl_get_sys_freq(), clock, divider); in mpc_i2c_get_fdr_8xxx()
408 if (div->divider >= divider) in mpc_i2c_get_fdr_8xxx()
412 *real_clk = fsl_get_sys_freq() / prescaler / div->divider; in mpc_i2c_get_fdr_8xxx()
/linux-4.4.14/drivers/clk/bcm/
Dclk-bcm2835.c1046 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); in bcm2835_pll_divider_is_on() local
1047 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_is_on()
1048 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_is_on()
1063 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); in bcm2835_pll_divider_get_rate() local
1064 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_get_rate()
1065 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_get_rate()
1077 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); in bcm2835_pll_divider_off() local
1078 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_off()
1079 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_off()
1091 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); in bcm2835_pll_divider_on() local
[all …]
Dclk-kona.c108 divider(struct bcm_clk_div *div, u64 scaled_div) in divider() function
615 reg_div = divider(div, div->u.s.scaled_div); in __div_commit()
/linux-4.4.14/Documentation/devicetree/bindings/spi/
Dspi_oc_tiny.txt8 - baud-width: width, in bits, of the programmable divider used to scale
11 The clock-frequency and baud-width properties are needed only if the divider
12 is programmable. They are not needed if the divider is fixed.
/linux-4.4.14/drivers/staging/comedi/drivers/
Ddt3000.c354 int divider, base, prescale; in dt3k_ns_to_timer() local
364 divider = (*nanosec + base / 2) / base; in dt3k_ns_to_timer()
367 divider = (*nanosec) / base; in dt3k_ns_to_timer()
370 divider = (*nanosec) / base; in dt3k_ns_to_timer()
373 if (divider < 65536) { in dt3k_ns_to_timer()
374 *nanosec = divider * base; in dt3k_ns_to_timer()
375 return (prescale << 16) | (divider); in dt3k_ns_to_timer()
381 divider = 65535; in dt3k_ns_to_timer()
382 *nanosec = divider * base; in dt3k_ns_to_timer()
383 return (prescale << 16) | (divider); in dt3k_ns_to_timer()
[all …]
Ddt282x.c365 unsigned int prescale, base, divider; in dt282x_ns_to_timer() local
374 divider = (*ns + base / 2) / base; in dt282x_ns_to_timer()
377 divider = (*ns) / base; in dt282x_ns_to_timer()
380 divider = (*ns + base - 1) / base; in dt282x_ns_to_timer()
383 if (divider < 256) { in dt282x_ns_to_timer()
384 *ns = divider * base; in dt282x_ns_to_timer()
385 return (prescale << 8) | (255 - divider); in dt282x_ns_to_timer()
389 divider = 255; in dt282x_ns_to_timer()
390 *ns = divider * base; in dt282x_ns_to_timer()
391 return (15 << 8) | (255 - divider); in dt282x_ns_to_timer()
Drtd520.c386 int divider; in rtd_ns_to_timer_base() local
391 divider = DIV_ROUND_CLOSEST(*nanosec, base); in rtd_ns_to_timer_base()
394 divider = (*nanosec) / base; in rtd_ns_to_timer_base()
397 divider = DIV_ROUND_UP(*nanosec, base); in rtd_ns_to_timer_base()
400 if (divider < 2) in rtd_ns_to_timer_base()
401 divider = 2; /* min is divide by 2 */ in rtd_ns_to_timer_base()
408 *nanosec = base * divider; in rtd_ns_to_timer_base()
409 return divider - 1; /* countdown is divisor+1 */ in rtd_ns_to_timer_base()
Dni_pcidio.c521 int divider, base; in ni_pcidio_ns_to_timer() local
528 divider = (*nanosec + base / 2) / base; in ni_pcidio_ns_to_timer()
531 divider = (*nanosec) / base; in ni_pcidio_ns_to_timer()
534 divider = (*nanosec + base - 1) / base; in ni_pcidio_ns_to_timer()
538 *nanosec = base * divider; in ni_pcidio_ns_to_timer()
539 return divider; in ni_pcidio_ns_to_timer()
Ds626.c1947 int divider, base; in s626_ns_to_timer() local
1954 divider = DIV_ROUND_CLOSEST(*nanosec, base); in s626_ns_to_timer()
1957 divider = (*nanosec) / base; in s626_ns_to_timer()
1960 divider = DIV_ROUND_UP(*nanosec, base); in s626_ns_to_timer()
1964 *nanosec = base * divider; in s626_ns_to_timer()
1965 return divider - 1; in s626_ns_to_timer()
Dni_mio_common.c2032 int divider; in ni_ns_to_timer() local
2037 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns; in ni_ns_to_timer()
2040 divider = (nanosec) / devpriv->clock_ns; in ni_ns_to_timer()
2043 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns; in ni_ns_to_timer()
2046 return divider - 1; in ni_ns_to_timer()
/linux-4.4.14/drivers/media/rc/
Dir-xmp-decoder.c85 int divider, i; in ir_xmp_decode() local
103 divider = (n[3] - XMP_NIBBLE_PREFIX) / 15 - 2000; in ir_xmp_decode()
104 if (divider < 50) { in ir_xmp_decode()
105 IR_dprintk(2, "divider to small %d.\n", divider); in ir_xmp_decode()
112 n[i] = (n[i] - XMP_NIBBLE_PREFIX) / divider; in ir_xmp_decode()
/linux-4.4.14/drivers/media/dvb-frontends/
Dstv6110.c241 u32 nbsteps, divider, psd2, freq; in stv6110_get_frequency() local
246 divider = (priv->regs[RSTV6110_TUNING2] & 0x0f) << 8; in stv6110_get_frequency()
247 divider += priv->regs[RSTV6110_TUNING1]; in stv6110_get_frequency()
254 freq = divider * (priv->mclk / 1000); in stv6110_get_frequency()
268 u32 divider, ref, p, presc, i, result_freq, vco_freq; in stv6110_set_frequency() local
324 divider = (((frequency * 1000) + (ref >> 1)) / ref); in stv6110_set_frequency()
332 priv->regs[RSTV6110_TUNING2] |= (((divider) >> 8) & 0x0f); in stv6110_set_frequency()
335 priv->regs[RSTV6110_TUNING1] = (divider & 0xff); in stv6110_set_frequency()
353 vco_freq = divider * ((priv->mclk / 1000) / ((1 << (r_div_opt + 1)))); in stv6110_set_frequency()
Dstv6110x.c121 u32 rDiv, divider; in stv6110x_set_frequency() local
154 divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz; in stv6110x_set_frequency()
155 divider = (divider + 5) / 10; in stv6110x_set_frequency()
158 STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_N_DIV_11_8, MSB(divider)); in stv6110x_set_frequency()
159 STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG0], TNG0_N_DIV_7_0, LSB(divider)); in stv6110x_set_frequency()
/linux-4.4.14/Documentation/devicetree/bindings/net/can/
Dmpc5xxx-mscan.txt21 also specify which clock source and divider shall be used for the controller:
32 - fsl,mscan-clock-divider: for the reference and system clock, an additional
33 clock divider can be specified. By default, a
52 fsl,mscan-clock-divider = <3>;
/linux-4.4.14/drivers/clk/berlin/
Dberlin2-div.c191 u32 divsw, div3sw, divider = 1; in berlin2_div_recalc_rate() local
203 divider = 3; in berlin2_div_recalc_rate()
206 divider = 1; in berlin2_div_recalc_rate()
213 divider = clk_div[reg]; in berlin2_div_recalc_rate()
219 return parent_rate / divider; in berlin2_div_recalc_rate()
Dberlin2-avpll.c266 u32 reg, div_av2, div_av3, divider = 1; in berlin2_avpll_channel_recalc_rate() local
282 divider = reg & VCO_SYNC1_MASK; in berlin2_avpll_channel_recalc_rate()
298 divider *= div_hdmi[reg & 0x3]; in berlin2_avpll_channel_recalc_rate()
312 divider *= div_av1[reg & 0x3]; in berlin2_avpll_channel_recalc_rate()
329 divider *= div_av2; in berlin2_avpll_channel_recalc_rate()
347 do_div(freq, divider); in berlin2_avpll_channel_recalc_rate()
/linux-4.4.14/Documentation/devicetree/bindings/iio/frequency/
Dadf4350.txt21 - adi,reference-div2-enable: Enables reference divider.
48 - adi,12bit-clk-divider: Clock divider value used when
50 - adi,clk-divider-mode:
52 0: Clock divider off (default)
/linux-4.4.14/drivers/spi/
Dspi-xcomm.c80 unsigned int divider; in spi_xcomm_setup_transfer() local
82 divider = DIV_ROUND_UP(SPI_XCOMM_CLOCK, t->speed_hz); in spi_xcomm_setup_transfer()
83 if (divider >= 64) in spi_xcomm_setup_transfer()
85 else if (divider >= 16) in spi_xcomm_setup_transfer()
Dspi-nuc900.c312 __raw_writel(hw->pdata->divider, hw->regs + USI_DIV); in nuc900_set_divider()
/linux-4.4.14/Documentation/hwmon/
Dadm924083 clock via a divider to an 8-bit counter. Fan speed (rpm) is calculated by:
85 rpm = (22500 * 60) / (count * divider)
87 Automatic fan clock divider
91 - fan clock divider not changed
96 - fan clock divider set to max
105 - fan clock divider set to suit fan_min
113 * fan speed may be displayed as zero until the auto fan clock divider
114 adjuster brings fan speed clock divider back into chip measurement
Dltc426038 registers. If a set of voltage divider resistors is installed, calculate the
40 value of the divider resistor against the measured voltage and R2 is the value
41 of the divider resistor against Ground.
Dltc426138 registers. If a set of voltage divider resistors is installed, calculate the
40 value of the divider resistor against the measured voltage and R2 is the value
41 of the divider resistor against Ground.
Dltc294538 registers. If a set of voltage divider resistors is installed, calculate the
40 value of the divider resistor against the measured voltage and R2 is the value
41 of the divider resistor against Ground.
Demc210321 readings can be divided by a programmable divider (1, 2, 4 or 8) to give
23 represented, so some rounding is done. With a divider of 1, the lowest
Dpc8736064 Fan readings are affected by a programmable clock divider, giving the
66 but this driver implements dynamic clock divider selection, so you don't
73 divider speed (RPM) RPM (RPM) speed (RPM)
80 * slowest measurable speed: clock/(255*divider)
89 divider is selected. This is not only true for the measured speeds, but
Dsmsc47m146 readings can be divided by a programmable divider (1, 2, 4 or 8) to give
48 represented, so some rounding is done. With a divider of 2, the lowest
Dlm8043 readings can be divided by a programmable divider (1, 2, 4 or 8) to give
45 represented, so some rounding is done. With a divider of 2, the lowest
Dgl518sm46 Fan readings can be divided by a programmable divider (1, 2, 4 or 8) to
48 accurately be represented, so some rounding is done. With a divider
Dlm8740 readings can be divided by a programmable divider (1, 2, 4 or 8) to give
42 represented, so some rounding is done. With a divider of 2, the lowest
Dlm7843 readings can be divided by a programmable divider (1, 2, 4 or 8) to give
45 represented, so some rounding is done. With a divider of 2, the lowest
Dvia686a48 readings can be divided by a programmable divider (1, 2, 4 or 8) to give
50 represented, so some rounding is done. With a divider of 2, the lowest
Dw83l786ng34 readings can be divided by a programmable divider (1, 2, 4, 8, 16, 32, 64
Dsis559575 readings can be divided by a programmable divider (1, 2, 4 or 8) to give
77 represented, so some rounding is done. With a divider of 2, the lowest
Dnct677569 NCT6775F, fan readings can be divided by a programmable divider (1, 2, 4, 8,
71 do not have a fan speed divider. The driver sets the most suitable fan divisor
72 itself; specifically, it increases the divider value each time a fan speed
Dit87146 counters for fans 1 to 3. This is better (no more fan clock divider mess) but
175 a programmable divider (1, 2, 4 or 8) to give the readings more range or
176 accuracy. With a divider of 2, the lowest representable value is around
Dlm6349 store the value in an 8-bit register and have a selectable clock divider
Dadm102654 rounding is done. With a divider of 8, the slowest measurable speed of a
Dw83791d75 readings can be divided by a programmable divider (1, 2, 4, 8, 16,
Dw83792d60 readings can be divided by a programmable divider (1, 2, 4, 8, 16, 32, 64 or
Df71805f68 name use R1 R2 divider raw val.
Dvt1211140 pin (Vpin) is formed by a voltage divider made of the thermistor (Rth) and a
Dw83627ehf73 readings can be divided by a programmable divider (1, 2, 4, 8, 16, 32, 64 or
Dw83781d94 readings can be divided by a programmable divider (1, 2, 4 or 8 for the
97 be represented, so some rounding is done. With a divider of 2, the lowest
Dsysfs-interface749 Example2, fan divider setting, valid values 2, 4 and 8:
/linux-4.4.14/drivers/clk/sunxi/
Dclk-sunxi.c985 struct clk_divider *divider; in sunxi_divs_clk_setup() local
1054 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in sunxi_divs_clk_setup()
1055 if (!divider) in sunxi_divs_clk_setup()
1060 divider->reg = reg; in sunxi_divs_clk_setup()
1061 divider->shift = data->div[i].shift; in sunxi_divs_clk_setup()
1062 divider->width = SUNXI_DIVISOR_WIDTH; in sunxi_divs_clk_setup()
1063 divider->flags = flags; in sunxi_divs_clk_setup()
1064 divider->lock = &clk_lock; in sunxi_divs_clk_setup()
1065 divider->table = data->div[i].table; in sunxi_divs_clk_setup()
1067 rate_hw = &divider->hw; in sunxi_divs_clk_setup()
/linux-4.4.14/drivers/mfd/
Dsm501.c393 int divider; member
412 int divider; in sm501_calc_clock() local
419 for (divider = 1; divider <= max_div; divider += 2) { in sm501_calc_clock()
423 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq; in sm501_calc_clock()
432 clock->divider = divider; in sm501_calc_clock()
477 return clock->mclk / (clock->divider << clock->shift); in sm501_calc_pll()
500 return clock->mclk / (clock->divider << clock->shift); in sm501_select_clock()
538 if (to.divider == 3) in sm501_set_clock()
540 else if (to.divider == 5) in sm501_set_clock()
548 if (to.divider == 3) in sm501_set_clock()
[all …]
/linux-4.4.14/drivers/media/usb/dvb-usb/
Ddib0700_core.c398 u16 divider; in dib0700_set_i2c_speed() local
410 divider = (u16) (30000 / scl_kHz); in dib0700_set_i2c_speed()
412 st->buf[2] = (u8) (divider >> 8); in dib0700_set_i2c_speed()
413 st->buf[3] = (u8) (divider & 0xff); in dib0700_set_i2c_speed()
414 divider = (u16) (72000 / scl_kHz); in dib0700_set_i2c_speed()
415 st->buf[4] = (u8) (divider >> 8); in dib0700_set_i2c_speed()
416 st->buf[5] = (u8) (divider & 0xff); in dib0700_set_i2c_speed()
417 divider = (u16) (72000 / scl_kHz); /* clock: 72MHz */ in dib0700_set_i2c_speed()
418 st->buf[6] = (u8) (divider >> 8); in dib0700_set_i2c_speed()
419 st->buf[7] = (u8) (divider & 0xff); in dib0700_set_i2c_speed()
/linux-4.4.14/drivers/media/platform/omap3isp/
Disp.c160 static void isp_xclk_update(struct isp_xclk *xclk, u32 divider) in isp_xclk_update() argument
166 divider << ISPTCTRL_CTRL_DIVA_SHIFT); in isp_xclk_update()
171 divider << ISPTCTRL_CTRL_DIVB_SHIFT); in isp_xclk_update()
198 isp_xclk_update(xclk, xclk->divider); in isp_xclk_enable()
221 return parent_rate / xclk->divider; in isp_xclk_recalc_rate()
226 u32 divider; in isp_xclk_calc_divider() local
236 divider = DIV_ROUND_CLOSEST(parent_rate, *rate); in isp_xclk_calc_divider()
237 if (divider >= ISPTCTRL_CTRL_DIV_BYPASS) in isp_xclk_calc_divider()
238 divider = ISPTCTRL_CTRL_DIV_BYPASS - 1; in isp_xclk_calc_divider()
240 *rate = parent_rate / divider; in isp_xclk_calc_divider()
[all …]
Disp.h136 unsigned int divider; member
/linux-4.4.14/Documentation/devicetree/bindings/mmc/
Dexynos-dw-mshc.txt26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
28 ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
52 - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
/linux-4.4.14/drivers/net/can/sja1000/
Dsja1000_platform.c143 u32 divider = priv->can.clock.freq * 2 / prop; in sp_populate_of() local
145 if (divider > 1) in sp_populate_of()
146 priv->cdr |= divider / 2 - 1; in sp_populate_of()
/linux-4.4.14/drivers/video/fbdev/matrox/
Dmatroxfb_misc.c194 unsigned int divider; in matroxfb_vgaHWinit() local
246 divider = minfo->curr.final_bppShift; in matroxfb_vgaHWinit()
247 while (divider & 3) { in matroxfb_vgaHWinit()
252 divider <<= 1; in matroxfb_vgaHWinit()
254 divider = divider / 4; in matroxfb_vgaHWinit()
256 while (divider > 8) { in matroxfb_vgaHWinit()
261 divider >>= 1; in matroxfb_vgaHWinit()
300 hw->CRTCEXT[3] = (divider - 1) | 0x80; in matroxfb_vgaHWinit()
/linux-4.4.14/drivers/media/i2c/soc_camera/
Dmt9t112.c426 priv->info->divider.m, in mt9t112_init_pll()
427 priv->info->divider.n, in mt9t112_init_pll()
428 priv->info->divider.p1, in mt9t112_init_pll()
429 priv->info->divider.p2, in mt9t112_init_pll()
430 priv->info->divider.p3, in mt9t112_init_pll()
431 priv->info->divider.p4, in mt9t112_init_pll()
432 priv->info->divider.p5, in mt9t112_init_pll()
433 priv->info->divider.p6, in mt9t112_init_pll()
434 priv->info->divider.p7); in mt9t112_init_pll()
/linux-4.4.14/drivers/gpu/drm/radeon/
Dr600_dpm.h179 u32 index, u32 divider);
181 u32 index, u32 divider);
183 u32 index, u32 divider);
Dtrinity_dpm.c612 u32 index, u32 divider) in trinity_set_ds_dividers() argument
619 value |= DS_DIV(divider); in trinity_set_ds_dividers()
624 u32 index, u32 divider) in trinity_set_ss_dividers() argument
631 value |= DS_SH_DIV(divider); in trinity_set_ss_dividers()
1828 u32 divider; in trinity_convert_did_to_freq() local
1831 divider = did * 25; in trinity_convert_did_to_freq()
1833 divider = (did - 64) * 50 + 1600; in trinity_convert_did_to_freq()
1835 divider = (did - 96) * 100 + 3200; in trinity_convert_did_to_freq()
1837 divider = 128 * 100; in trinity_convert_did_to_freq()
1841 return ((pi->sys_info.dentist_vco_freq * 100) + (divider - 1)) / divider; in trinity_convert_did_to_freq()
Dradeon_legacy_crtc.c754 int divider; in radeon_set_pll() member
822 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_set_pll()
823 if (post_div->divider == post_divider) in radeon_set_pll()
827 if (!post_div->divider) in radeon_set_pll()
Dsumo_dpm.c475 u32 index, u32 divider) in sumo_set_divider_value() argument
482 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK); in sumo_set_divider_value()
485 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK); in sumo_set_divider_value()
488 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK); in sumo_set_divider_value()
491 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK); in sumo_set_divider_value()
495 u32 index, u32 divider) in sumo_set_ds_dividers() argument
503 dpm_ctrl |= (divider << (index * 3)); in sumo_set_ds_dividers()
509 u32 index, u32 divider) in sumo_set_ss_dividers() argument
517 dpm_ctrl |= (divider << (index * 3)); in sumo_set_ss_dividers()
Dr600_dpm.c476 u32 index, u32 divider) in r600_engine_clock_entry_set_post_divider() argument
479 STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK); in r600_engine_clock_entry_set_post_divider()
483 u32 index, u32 divider) in r600_engine_clock_entry_set_reference_divider() argument
486 STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK); in r600_engine_clock_entry_set_reference_divider()
490 u32 index, u32 divider) in r600_engine_clock_entry_set_feedback_divider() argument
493 STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK); in r600_engine_clock_entry_set_feedback_divider()
Drv6xx_dpm.c381 u32 index, u32 divider) in rv6xx_memory_clock_entry_set_post_divider() argument
384 LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK); in rv6xx_memory_clock_entry_set_post_divider()
388 u32 index, u32 divider) in rv6xx_memory_clock_entry_set_feedback_divider() argument
390 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider), in rv6xx_memory_clock_entry_set_feedback_divider()
395 u32 index, u32 divider) in rv6xx_memory_clock_entry_set_reference_divider() argument
398 LEVEL0_MPLL_REF_DIV(divider), ~LEVEL0_MPLL_REF_DIV_MASK); in rv6xx_memory_clock_entry_set_reference_divider()
/linux-4.4.14/include/linux/platform_data/
Dspi-nuc900.h22 unsigned int divider; member
/linux-4.4.14/include/media/
Dmt9t112.h27 struct mt9t112_pll_divider divider; member
/linux-4.4.14/sound/oss/dmasound/
Ddmasound_atari.c1034 int divider, i, idx; in FalconInit() local
1064 divider = 1; in FalconInit()
1068 divider = 1; in FalconInit()
1071 divider = 2; in FalconInit()
1074 divider = 3; in FalconInit()
1077 divider = 4; in FalconInit()
1080 divider = 5; in FalconInit()
1083 divider = 7; in FalconInit()
1086 divider = 9; in FalconInit()
1089 divider = 11; in FalconInit()
[all …]
/linux-4.4.14/sound/soc/spear/
Dspdif_out.c94 u32 divider, ctrl; in spdif_out_clock() local
97 divider = DIV_ROUND_CLOSEST(clk_get_rate(host->clk), (rate * 128)); in spdif_out_clock()
101 ctrl |= (divider << SPDIF_DIVIDER_SHIFT) & SPDIF_DIVIDER_MASK; in spdif_out_clock()
/linux-4.4.14/arch/m68k/coldfire/
Dm53xx.c579 int divider; in get_sys_clock() local
583 divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF); in get_sys_clock()
584 return (FREF/(2 << divider)); in get_sys_clock()
/linux-4.4.14/drivers/staging/clocking-wizard/
DTODO3 - support for fractional divider (output 0 only)
/linux-4.4.14/drivers/net/wan/
Ddscc4.c1261 u32 n = 0, m = 0, divider; in dscc4_set_clock() local
1269 divider = xtal / *bps; in dscc4_set_clock()
1270 if (divider > BRR_DIVIDER_MAX) { in dscc4_set_clock()
1271 divider >>= 4; in dscc4_set_clock()
1275 if (divider >> 22) { in dscc4_set_clock()
1278 } else if (divider) { in dscc4_set_clock()
1281 while (0xffffffc0 & divider) { in dscc4_set_clock()
1283 divider >>= 1; in dscc4_set_clock()
1285 n = divider; in dscc4_set_clock()
1288 divider = n << m; in dscc4_set_clock()
[all …]
/linux-4.4.14/drivers/mmc/host/
Dmxcmmc.c798 unsigned int divider; in mxcmci_set_clk_rate() local
803 for (divider = 1; divider <= 0xF; divider++) { in mxcmci_set_clk_rate()
806 x = (clk_in / (divider + 1)); in mxcmci_set_clk_rate()
814 if (divider < 0x10) in mxcmci_set_clk_rate()
823 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE); in mxcmci_set_clk_rate()
826 prescaler, divider, clk_in, clk_ios); in mxcmci_set_clk_rate()
/linux-4.4.14/Documentation/devicetree/bindings/clock/st/
Dst,clkgen-prediv.txt1 Binding for a ST pre-divider clock driver.
Dst,clkgen-divmux.txt1 Binding for a ST divider and multiplexer clock driver.
Dst,flexgen.txt6 - a pre and final dividers (represented by a divider and gate elements)
/linux-4.4.14/Documentation/ABI/testing/
Dsysfs-bus-intel_th-devices-pti20 Description: (RW) Configure PTI port clock divider:
/linux-4.4.14/Documentation/devicetree/bindings/display/armada/
Dmarvell,dove-lcd.txt14 "plldivider" - pll divider clock for pixel clock
/linux-4.4.14/include/linux/mfd/
Ddb8500-prcmu.h504 int prcmu_set_clock_divider(u8 clock, u8 divider);
622 static inline int prcmu_set_clock_divider(u8 clock, u8 divider) in prcmu_set_clock_divider() argument
/linux-4.4.14/Documentation/devicetree/bindings/usb/
Dci-hdrc-usb2.txt61 - external-vbus-divider: enables off-chip resistor divider for Vbus
/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_dsi_pll.c439 u32 divider; in bxt_dsi_program_clocks() local
457 divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1; in bxt_dsi_program_clocks()
458 tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider); in bxt_dsi_program_clocks()
Dintel_dsi.c747 static u16 txclkesc(u32 divider, unsigned int us) in txclkesc() argument
749 switch (divider) { in txclkesc()
Dintel_display.c154 int divider; in vlv_get_cck_clock_hpll() local
163 divider = val & CCK_FREQUENCY_VALUES; in vlv_get_cck_clock_hpll()
166 (divider << CCK_FREQUENCY_STATUS_SHIFT), in vlv_get_cck_clock_hpll()
169 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); in vlv_get_cck_clock_hpll()
5471 uint32_t divider; in broxton_set_cdclk() local
5479 divider = BXT_CDCLK_CD2X_DIV_SEL_4; in broxton_set_cdclk()
5483 divider = BXT_CDCLK_CD2X_DIV_SEL_2; in broxton_set_cdclk()
5487 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; in broxton_set_cdclk()
5491 divider = BXT_CDCLK_CD2X_DIV_SEL_1; in broxton_set_cdclk()
5495 divider = BXT_CDCLK_CD2X_DIV_SEL_1; in broxton_set_cdclk()
[all …]
Dintel_ddi.c1335 unsigned int divider) in skl_wrpll_try_divider() argument
1349 ctx->p = divider; in skl_wrpll_try_divider()
1357 ctx->p = divider; in skl_wrpll_try_divider()
/linux-4.4.14/Documentation/devicetree/bindings/sound/
Dadi,adau1701.txt17 configured clock divider on ASoC side before the
Dst,sta350.txt107 - st,powerdown-delay-divider:
109 value. If not specified, a divider of 1 will be used. Allowed values
Dsamsung-i2s.txt45 CLK_I2S_RCLK_PSR - the RCLK prescaler divider clock (corresponding to the
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgk20a.c140 u32 divider; in gk20a_pllg_calc_rate() local
143 divider = clk->m * pl_to_div[clk->pl]; in gk20a_pllg_calc_rate()
144 do_div(rate, divider); in gk20a_pllg_calc_rate()
/linux-4.4.14/Documentation/devicetree/bindings/i2c/
Di2c-mt6577.txt15 - clock-div: the fixed value for frequency divider of clock source in i2c
/linux-4.4.14/Documentation/video4linux/cx2341x/
Dfw-decoder-regs.txt170 correctly set the divider in Reg 2874.
212 Decoder horizontal Y output size divider
218 Decoder horizontal UV output size divider
524 correctly set the divider in Reg 296C
596 Decoder vertical Y output size divider
602 Decoder vertical UV output size divider
/linux-4.4.14/sound/oss/
Dsb_ess.c317 int divider; in ess_calc_div() local
322 divider = (clock + speed / 2) / speed; in ess_calc_div()
323 retval = revert - divider; in ess_calc_div()
326 divider = revert - retval; in ess_calc_div()
332 *speedp = clock / divider; in ess_calc_div()
Dad1848.c2703 unsigned long divider; in ad1848_tmr_start() local
2725 divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs; in ad1848_tmr_start()
2727 if (divider < 100) /* Don't allow shorter intervals than about 1ms */ in ad1848_tmr_start()
2728 divider = 100; in ad1848_tmr_start()
2730 if (divider > 65535) /* Overflow check */ in ad1848_tmr_start()
2731 divider = 65535; in ad1848_tmr_start()
2733 ad_write(devc, 21, (divider >> 8) & 0xff); /* Set upper bits */ in ad1848_tmr_start()
2734 ad_write(devc, 20, divider & 0xff); /* Set lower bits */ in ad1848_tmr_start()
2739 return current_interval = (divider * xtal_nsecs + 500) / 1000; in ad1848_tmr_start()
/linux-4.4.14/arch/arm/mach-lpc32xx/
Dclock.c861 u32 divider; in adc_onoff_enable() local
870 divider = clk->get_rate(clk) / 4500000 + 1; in adc_onoff_enable()
871 tmp |= divider; in adc_onoff_enable()
875 clk->rate = clk->get_rate(clk->parent) / divider; in adc_onoff_enable()
/linux-4.4.14/arch/mips/include/asm/sgi/
Dmc.h57 volatile u32 divider; /* Divider reg for RPSS */ member
/linux-4.4.14/drivers/video/fbdev/
Dau1200fb.c1243 unsigned int hi1, divider; in set_global() local
1256 divider = (lcd->pwmdiv & 0x3FFFF) + 1; in set_global()
1257 hi1 = (((pdata->brightness & 0xFF)+1) * divider >> 8); in set_global()
1272 unsigned int hi1, divider; in get_global() local
1283 divider = (lcd->pwmdiv & 0x3FFFF) + 1; in get_global()
1284 pdata->brightness = ((hi1 << 8) / divider) - 1; in get_global()
Dw100fb.c1420 unsigned long rot=0, divider, offset=0; in w100_set_dispregs() local
1429 divider = par->mode->pixclk_divider; in w100_set_dispregs()
1438 divider = par->mode->pixclk_divider_rotated; in w100_set_dispregs()
1497 w100_pwr_state.pclk_cntl.f.pclk_post_div = divider; in w100_set_dispregs()
/linux-4.4.14/arch/mips/sgi-ip22/
Dip22-mc.c169 sgimc->divider = 0x101; in sgimc_init()
/linux-4.4.14/Documentation/devicetree/bindings/leds/
Dleds-bcm6358.txt16 - brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8.
/linux-4.4.14/Documentation/arm/Samsung-S3C24XX/
DCPUfreq.txt17 newer version where there is a separate PLL and clock divider for the
/linux-4.4.14/drivers/clocksource/
Darm_arch_timer.c296 static void arch_timer_evtstrm_enable(int divider) in arch_timer_evtstrm_enable() argument
302 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) in arch_timer_evtstrm_enable()
/linux-4.4.14/sound/isa/es1688/
Des1688_lib.c316 unsigned int bits, divider; in snd_es1688_set_rate() local
323 divider = 256 - 7160000*20/(8*82*runtime->rate); in snd_es1688_set_rate()
326 snd_es1688_write(chip, 0xa2, divider); in snd_es1688_set_rate()
/linux-4.4.14/arch/arm/mach-w90x900/
Ddev.c211 .divider = 24,
/linux-4.4.14/Documentation/devicetree/bindings/display/imx/
Dldb.txt19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
/linux-4.4.14/Documentation/devicetree/bindings/phy/
Dti-phy.txt76 * "phy-div" - divider for apll
/linux-4.4.14/Documentation/networking/
Dz8530drv.txt254 # divider = use full duplex divider if
290 (1) this divider is usually mounted on the SCC-PBC (PA0HZP) or not
292 (digital pll) as transmit clock. Using this mode without a divider
/linux-4.4.14/arch/arm64/boot/dts/apm/
Dapm-storm.dtsi170 divider-offset = <0x238>;
171 divider-width = <0x9>;
172 divider-shift = <0x0>;
/linux-4.4.14/arch/sh/boards/mach-ecovec24/
Dsetup.c781 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
803 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
/linux-4.4.14/fs/gfs2/
Ddir.c970 u32 start, len, half_len, divider; in dir_split_leaf() local
1041 divider = (start + half_len) << (32 - dip->i_depth); in dir_split_leaf()
1052 be32_to_cpu(dent->de_hash) < divider) { in dir_split_leaf()
/linux-4.4.14/arch/m32r/
DKconfig190 int "Timer divider (integer)"
/linux-4.4.14/Documentation/virtual/kvm/
Dtimekeeping.txt202 programmed to a 32kHz divider if the RTC is to count seconds.
277 by the programmable divider register.