1* USB2 ChipIdea USB controller for ci13xxx 2 3Required properties: 4- compatible: should be one of: 5 "fsl,imx27-usb" 6 "lsi,zevio-usb" 7 "qcom,ci-hdrc" 8 "chipidea,usb2" 9 "xlnx,zynq-usb-2.20a" 10- reg: base address and length of the registers 11- interrupts: interrupt for the USB controller 12 13Recommended properies: 14- phy_type: the type of the phy connected to the core. Should be one 15 of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this 16 property the PORTSC register won't be touched. 17- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" 18 19Deprecated properties: 20- usb-phy: phandle for the PHY device. Use "phys" instead. 21- fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead. 22 23Optional properties: 24- clocks: reference to the USB clock 25- phys: reference to the USB PHY 26- phy-names: should be "usb-phy" 27- vbus-supply: reference to the VBUS regulator 28- maximum-speed: limit the maximum connection speed to "full-speed". 29- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts 30- itc-setting: interrupt threshold control register control, the setting 31 should be aligned with ITC bits at register USBCMD. 32- ahb-burst-config: it is vendor dependent, the required value should be 33 aligned with AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This 34 property is used to change AHB burst configuration, check the chipidea 35 spec for meaning of each value. If this property is not existed, it 36 will use the reset value. 37- tx-burst-size-dword: it is vendor dependent, the tx burst size in dword 38 (4 bytes), This register represents the maximum length of a the burst 39 in 32-bit words while moving data from system memory to the USB 40 bus, the value of this property will only take effect if property 41 "ahb-burst-config" is set to 0, if this property is missing the reset 42 default of the hardware implementation will be used. 43- rx-burst-size-dword: it is vendor dependent, the rx burst size in dword 44 (4 bytes), This register represents the maximum length of a the burst 45 in 32-bit words while moving data from the USB bus to system memory, 46 the value of this property will only take effect if property 47 "ahb-burst-config" is set to 0, if this property is missing the reset 48 default of the hardware implementation will be used. 49- extcon: phandles to external connector devices. First phandle should point to 50 external connector, which provide "USB" cable events, the second should point 51 to external connector device, which provide "USB-HOST" cable events. If one 52 of the external connector devices is not required, empty <0> phandle should 53 be specified. 54- phy-clkgate-delay-us: the delay time (us) between putting the PHY into 55 low power mode and gating the PHY clock. 56 57i.mx specific properties 58- fsl,usbmisc: phandler of non-core register device, with one 59 argument that indicate usb controller index 60- disable-over-current: disable over current detect 61- external-vbus-divider: enables off-chip resistor divider for Vbus 62 63Example: 64 65 usb@f7ed0000 { 66 compatible = "chipidea,usb2"; 67 reg = <0xf7ed0000 0x10000>; 68 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 69 clocks = <&chip CLKID_USB0>; 70 phys = <&usb_phy0>; 71 phy-names = "usb-phy"; 72 vbus-supply = <®_usb0_vbus>; 73 gadget-itc-setting = <0x4>; /* 4 micro-frames */ 74 /* Incremental burst of unspecified length */ 75 ahb-burst-config = <0x0>; 76 tx-burst-size-dword = <0x10>; /* 64 bytes */ 77 rx-burst-size-dword = <0x10>; 78 extcon = <0>, <&usb_id>; 79 phy-clkgate-delay-us = <400>; 80 }; 81