1/*
2 * DRA7 ATL (Audio Tracking Logic) clock driver
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Peter Ujfalusi <peter.ujfalusi@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/module.h>
19#include <linux/clk.h>
20#include <linux/clk-provider.h>
21#include <linux/slab.h>
22#include <linux/io.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/platform_device.h>
26#include <linux/pm_runtime.h>
27
28#define DRA7_ATL_INSTANCES	4
29
30#define DRA7_ATL_PPMR_REG(id)		(0x200 + (id * 0x80))
31#define DRA7_ATL_BBSR_REG(id)		(0x204 + (id * 0x80))
32#define DRA7_ATL_ATLCR_REG(id)		(0x208 + (id * 0x80))
33#define DRA7_ATL_SWEN_REG(id)		(0x210 + (id * 0x80))
34#define DRA7_ATL_BWSMUX_REG(id)		(0x214 + (id * 0x80))
35#define DRA7_ATL_AWSMUX_REG(id)		(0x218 + (id * 0x80))
36#define DRA7_ATL_PCLKMUX_REG(id)	(0x21c + (id * 0x80))
37
38#define DRA7_ATL_SWEN			BIT(0)
39#define DRA7_ATL_DIVIDER_MASK		(0x1f)
40#define DRA7_ATL_PCLKMUX		BIT(0)
41struct dra7_atl_clock_info;
42
43struct dra7_atl_desc {
44	struct clk *clk;
45	struct clk_hw hw;
46	struct dra7_atl_clock_info *cinfo;
47	int id;
48
49	bool probed;		/* the driver for the IP has been loaded */
50	bool valid;		/* configured */
51	bool enabled;
52	u32 bws;		/* Baseband Word Select Mux */
53	u32 aws;		/* Audio Word Select Mux */
54	u32 divider;		/* Cached divider value */
55};
56
57struct dra7_atl_clock_info {
58	struct device *dev;
59	void __iomem *iobase;
60
61	struct dra7_atl_desc *cdesc;
62};
63
64#define to_atl_desc(_hw)	container_of(_hw, struct dra7_atl_desc, hw)
65
66static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg,
67			     u32 val)
68{
69	__raw_writel(val, cinfo->iobase + reg);
70}
71
72static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg)
73{
74	return __raw_readl(cinfo->iobase + reg);
75}
76
77static int atl_clk_enable(struct clk_hw *hw)
78{
79	struct dra7_atl_desc *cdesc = to_atl_desc(hw);
80
81	if (!cdesc->probed)
82		goto out;
83
84	if (unlikely(!cdesc->valid))
85		dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n",
86			 cdesc->id);
87	pm_runtime_get_sync(cdesc->cinfo->dev);
88
89	atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id),
90		  cdesc->divider - 1);
91	atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN);
92
93out:
94	cdesc->enabled = true;
95
96	return 0;
97}
98
99static void atl_clk_disable(struct clk_hw *hw)
100{
101	struct dra7_atl_desc *cdesc = to_atl_desc(hw);
102
103	if (!cdesc->probed)
104		goto out;
105
106	atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0);
107	pm_runtime_put_sync(cdesc->cinfo->dev);
108
109out:
110	cdesc->enabled = false;
111}
112
113static int atl_clk_is_enabled(struct clk_hw *hw)
114{
115	struct dra7_atl_desc *cdesc = to_atl_desc(hw);
116
117	return cdesc->enabled;
118}
119
120static unsigned long atl_clk_recalc_rate(struct clk_hw *hw,
121					 unsigned long parent_rate)
122{
123	struct dra7_atl_desc *cdesc = to_atl_desc(hw);
124
125	return parent_rate / cdesc->divider;
126}
127
128static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
129			       unsigned long *parent_rate)
130{
131	unsigned divider;
132
133	divider = (*parent_rate + rate / 2) / rate;
134	if (divider > DRA7_ATL_DIVIDER_MASK + 1)
135		divider = DRA7_ATL_DIVIDER_MASK + 1;
136
137	return *parent_rate / divider;
138}
139
140static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
141			    unsigned long parent_rate)
142{
143	struct dra7_atl_desc *cdesc;
144	u32 divider;
145
146	if (!hw || !rate)
147		return -EINVAL;
148
149	cdesc = to_atl_desc(hw);
150	divider = ((parent_rate + rate / 2) / rate) - 1;
151	if (divider > DRA7_ATL_DIVIDER_MASK)
152		divider = DRA7_ATL_DIVIDER_MASK;
153
154	cdesc->divider = divider + 1;
155
156	return 0;
157}
158
159static const struct clk_ops atl_clk_ops = {
160	.enable		= atl_clk_enable,
161	.disable	= atl_clk_disable,
162	.is_enabled	= atl_clk_is_enabled,
163	.recalc_rate	= atl_clk_recalc_rate,
164	.round_rate	= atl_clk_round_rate,
165	.set_rate	= atl_clk_set_rate,
166};
167
168static void __init of_dra7_atl_clock_setup(struct device_node *node)
169{
170	struct dra7_atl_desc *clk_hw = NULL;
171	struct clk_init_data init = { NULL };
172	const char **parent_names = NULL;
173	struct clk *clk;
174
175	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
176	if (!clk_hw) {
177		pr_err("%s: could not allocate dra7_atl_desc\n", __func__);
178		return;
179	}
180
181	clk_hw->hw.init = &init;
182	clk_hw->divider = 1;
183	init.name = node->name;
184	init.ops = &atl_clk_ops;
185	init.flags = CLK_IGNORE_UNUSED;
186	init.num_parents = of_clk_get_parent_count(node);
187
188	if (init.num_parents != 1) {
189		pr_err("%s: atl clock %s must have 1 parent\n", __func__,
190		       node->name);
191		goto cleanup;
192	}
193
194	parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
195
196	if (!parent_names)
197		goto cleanup;
198
199	parent_names[0] = of_clk_get_parent_name(node, 0);
200
201	init.parent_names = parent_names;
202
203	clk = clk_register(NULL, &clk_hw->hw);
204
205	if (!IS_ERR(clk)) {
206		of_clk_add_provider(node, of_clk_src_simple_get, clk);
207		kfree(parent_names);
208		return;
209	}
210cleanup:
211	kfree(parent_names);
212	kfree(clk_hw);
213}
214CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup);
215
216static int of_dra7_atl_clk_probe(struct platform_device *pdev)
217{
218	struct device_node *node = pdev->dev.of_node;
219	struct dra7_atl_clock_info *cinfo;
220	int i;
221	int ret = 0;
222
223	if (!node)
224		return -ENODEV;
225
226	cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
227	if (!cinfo)
228		return -ENOMEM;
229
230	cinfo->iobase = of_iomap(node, 0);
231	cinfo->dev = &pdev->dev;
232	pm_runtime_enable(cinfo->dev);
233	pm_runtime_irq_safe(cinfo->dev);
234
235	pm_runtime_get_sync(cinfo->dev);
236	atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX);
237
238	for (i = 0; i < DRA7_ATL_INSTANCES; i++) {
239		struct device_node *cfg_node;
240		char prop[5];
241		struct dra7_atl_desc *cdesc;
242		struct of_phandle_args clkspec;
243		struct clk *clk;
244		int rc;
245
246		rc = of_parse_phandle_with_args(node, "ti,provided-clocks",
247						NULL, i, &clkspec);
248
249		if (rc) {
250			pr_err("%s: failed to lookup atl clock %d\n", __func__,
251			       i);
252			return -EINVAL;
253		}
254
255		clk = of_clk_get_from_provider(&clkspec);
256		if (IS_ERR(clk)) {
257			pr_err("%s: failed to get atl clock %d from provider\n",
258			       __func__, i);
259			return PTR_ERR(clk);
260		}
261
262		cdesc = to_atl_desc(__clk_get_hw(clk));
263		cdesc->cinfo = cinfo;
264		cdesc->id = i;
265
266		/* Get configuration for the ATL instances */
267		snprintf(prop, sizeof(prop), "atl%u", i);
268		cfg_node = of_find_node_by_name(node, prop);
269		if (cfg_node) {
270			ret = of_property_read_u32(cfg_node, "bws",
271						   &cdesc->bws);
272			ret |= of_property_read_u32(cfg_node, "aws",
273						    &cdesc->aws);
274			if (!ret) {
275				cdesc->valid = true;
276				atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i),
277					  cdesc->bws);
278				atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i),
279					  cdesc->aws);
280			}
281		}
282
283		cdesc->probed = true;
284		/*
285		 * Enable the clock if it has been asked prior to loading the
286		 * hw driver
287		 */
288		if (cdesc->enabled)
289			atl_clk_enable(__clk_get_hw(clk));
290	}
291	pm_runtime_put_sync(cinfo->dev);
292
293	return ret;
294}
295
296static int of_dra7_atl_clk_remove(struct platform_device *pdev)
297{
298	pm_runtime_disable(&pdev->dev);
299
300	return 0;
301}
302
303static const struct of_device_id of_dra7_atl_clk_match_tbl[] = {
304	{ .compatible = "ti,dra7-atl", },
305	{},
306};
307MODULE_DEVICE_TABLE(of, of_dra7_atl_clk_match_tbl);
308
309static struct platform_driver dra7_atl_clk_driver = {
310	.driver = {
311		.name = "dra7-atl",
312		.of_match_table = of_dra7_atl_clk_match_tbl,
313	},
314	.probe = of_dra7_atl_clk_probe,
315	.remove = of_dra7_atl_clk_remove,
316};
317
318module_platform_driver(dra7_atl_clk_driver);
319
320MODULE_DESCRIPTION("Clock driver for DRA7 Audio Tracking Logic");
321MODULE_ALIAS("platform:dra7-atl-clock");
322MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
323MODULE_LICENSE("GPL v2");
324