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Searched refs:clkr (Results 1 – 24 of 24) sorted by relevance

/linux-4.4.14/drivers/clk/qcom/
Dgcc-apq8084.c119 .clkr.hw.init = &(struct clk_init_data){
142 .clkr.hw.init = &(struct clk_init_data){
154 .clkr.hw.init = &(struct clk_init_data){
166 .clkr.hw.init = &(struct clk_init_data){
182 .clkr.hw.init = &(struct clk_init_data){
209 .clkr.hw.init = &(struct clk_init_data){
241 .clkr.hw.init = &(struct clk_init_data){
260 .clkr.hw.init = &(struct clk_init_data){
279 .clkr.hw.init = &(struct clk_init_data){
289 .clkr = {
[all …]
Dgcc-msm8974.c75 .clkr.hw.init = &(struct clk_init_data){
98 .clkr.hw.init = &(struct clk_init_data){
110 .clkr.hw.init = &(struct clk_init_data){
122 .clkr.hw.init = &(struct clk_init_data){
138 .clkr.hw.init = &(struct clk_init_data){
165 .clkr.hw.init = &(struct clk_init_data){
195 .clkr.hw.init = &(struct clk_init_data){
215 .clkr.hw.init = &(struct clk_init_data){
240 .clkr.hw.init = &(struct clk_init_data){
253 .clkr.hw.init = &(struct clk_init_data){
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Dmmcc-msm8960.c124 .clkr.hw.init = &(struct clk_init_data){
140 .clkr.hw.init = &(struct clk_init_data){
198 .clkr = {
213 .clkr = {
247 .clkr = {
262 .clkr = {
296 .clkr = {
311 .clkr = {
351 .clkr = {
366 .clkr = {
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Dgcc-msm8960.c43 .clkr.hw.init = &(struct clk_init_data){
70 .clkr.hw.init = &(struct clk_init_data){
97 .clkr.hw.init = &(struct clk_init_data){
195 .clkr = {
211 .clkr = {
246 .clkr = {
262 .clkr = {
297 .clkr = {
313 .clkr = {
348 .clkr = {
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Dmmcc-msm8974.c197 .clkr.hw.init = &(struct clk_init_data){
224 .clkr.hw.init = &(struct clk_init_data){
250 .clkr.hw.init = &(struct clk_init_data){
266 .clkr.hw.init = &(struct clk_init_data){
278 .clkr.hw.init = &(struct clk_init_data){
303 .clkr.hw.init = &(struct clk_init_data){
327 .clkr.hw.init = &(struct clk_init_data){
346 .clkr.hw.init = &(struct clk_init_data){
359 .clkr.hw.init = &(struct clk_init_data){
372 .clkr.hw.init = &(struct clk_init_data){
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Dmmcc-apq8084.c232 .clkr.hw.init = &(struct clk_init_data){
259 .clkr.hw.init = &(struct clk_init_data){
285 .clkr.hw.init = &(struct clk_init_data){
301 .clkr.hw.init = &(struct clk_init_data){
316 .clkr.hw.init = &(struct clk_init_data){
328 .clkr.hw.init = &(struct clk_init_data){
353 .clkr.hw.init = &(struct clk_init_data){
377 .clkr.hw.init = &(struct clk_init_data){
396 .clkr.hw.init = &(struct clk_init_data){
409 .clkr.hw.init = &(struct clk_init_data){
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Dgcc-msm8916.c277 .clkr.hw.init = &(struct clk_init_data){
304 .clkr.hw.init = &(struct clk_init_data){
331 .clkr.hw.init = &(struct clk_init_data){
358 .clkr.hw.init = &(struct clk_init_data){
381 .clkr.hw.init = &(struct clk_init_data){
393 .clkr.hw.init = &(struct clk_init_data){
413 .clkr.hw.init = &(struct clk_init_data){
434 .clkr.hw.init = &(struct clk_init_data){
453 .clkr.hw.init = &(struct clk_init_data){
466 .clkr.hw.init = &(struct clk_init_data){
[all …]
Dgcc-msm8660.c43 .clkr.hw.init = &(struct clk_init_data){
128 .clkr = {
144 .clkr = {
179 .clkr = {
195 .clkr = {
230 .clkr = {
246 .clkr = {
281 .clkr = {
297 .clkr = {
332 .clkr = {
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Dgcc-ipq806x.c43 .clkr.hw.init = &(struct clk_init_data){
70 .clkr.hw.init = &(struct clk_init_data){
97 .clkr.hw.init = &(struct clk_init_data){
124 .clkr.hw.init = &(struct clk_init_data){
168 .clkr.hw.init = &(struct clk_init_data){
289 .clkr = {
305 .clkr = {
340 .clkr = {
356 .clkr = {
391 .clkr = {
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Dlcc-msm8960.c42 .clkr.hw.init = &(struct clk_init_data){
117 .clkr = {
138 .clkr = {
155 .clkr = {
171 .clkr = {
188 .clkr = {
223 .clkr = { \
244 .clkr = { \
261 .clkr = { \
275 .clkr = { \
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Dlcc-ipq806x.c42 .clkr.hw.init = &(struct clk_init_data){
136 .clkr = {
157 .clkr = {
174 .clkr = {
188 .clkr = {
206 .clkr = {
250 .clkr = {
267 .clkr = {
284 .clkr = {
330 .clkr = {
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Dclk-pll.c44 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
53 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
65 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
74 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
84 regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_disable()
89 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); in clk_pll_disable()
100 regmap_read(pll->clkr.regmap, pll->l_reg, &l); in clk_pll_recalc_rate()
101 regmap_read(pll->clkr.regmap, pll->m_reg, &m); in clk_pll_recalc_rate()
102 regmap_read(pll->clkr.regmap, pll->n_reg, &n); in clk_pll_recalc_rate()
116 regmap_read(pll->clkr.regmap, pll->config_reg, &config); in clk_pll_recalc_rate()
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Dclk-rcg.c52 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_get_parent()
81 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_get_parent()
87 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); in clk_dyn_rcg_get_parent()
107 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_set_parent()
109 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns); in clk_rcg_set_parent()
217 struct clk_hw *hw = &rcg->clkr.hw; in configure_bank()
221 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in configure_bank()
228 ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns); in configure_bank()
237 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); in configure_bank()
241 ret = regmap_read(rcg->clkr.regmap, md_reg, &md); in configure_bank()
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Dclk-regmap-divider.c23 return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr); in to_clk_regmap_div()
39 struct clk_regmap *clkr = &divider->clkr; in div_set_rate() local
45 return regmap_update_bits(clkr->regmap, divider->reg, in div_set_rate()
54 struct clk_regmap *clkr = &divider->clkr; in div_recalc_rate() local
57 regmap_read(clkr->regmap, divider->reg, &div); in div_recalc_rate()
Dclk-regmap-mux.c23 return container_of(to_clk_regmap(hw), struct clk_regmap_mux, clkr); in to_clk_regmap_mux()
29 struct clk_regmap *clkr = to_clk_regmap(hw); in mux_get_parent() local
33 regmap_read(clkr->regmap, mux->reg, &val); in mux_get_parent()
44 struct clk_regmap *clkr = to_clk_regmap(hw); in mux_set_parent() local
51 return regmap_update_bits(clkr->regmap, mux->reg, mask, val); in mux_set_parent()
Dclk-rcg.h104 struct clk_regmap clkr; member
114 #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
143 struct clk_regmap clkr; member
149 container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr)
170 struct clk_regmap clkr; member
173 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
Dclk-rcg2.c56 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); in clk_rcg2_is_enabled()
70 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_rcg2_get_parent()
91 struct clk_hw *hw = &rcg->clkr.hw; in update_config()
94 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, in update_config()
101 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); in update_config()
119 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_rcg2_set_parent()
158 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_rcg2_recalc_rate()
162 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m); in clk_rcg2_recalc_rate()
164 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n); in clk_rcg2_recalc_rate()
230 struct clk_hw *hw = &rcg->clkr.hw; in clk_rcg2_configure()
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Dclk-branch.c31 regmap_read(br->clkr.regmap, br->hwcg_reg, &val); in clk_branch_in_hwcg_mode()
41 regmap_read(br->clkr.regmap, br->halt_reg, &val); in clk_branch_check_halt()
63 regmap_read(br->clkr.regmap, br->halt_reg, &val); in clk_branch2_check_halt()
78 const char *name = clk_hw_get_name(&br->clkr.hw); in clk_branch_wait()
Dclk-branch.h46 struct clk_regmap clkr; member
54 container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
Dclk-pll.h60 struct clk_regmap clkr; member
67 #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr)
Dclk-regmap-mux.h24 struct clk_regmap clkr; member
Dclk-regmap-divider.h24 struct clk_regmap clkr; member
/linux-4.4.14/arch/mips/include/asm/octeon/
Dcvmx-lmcx-defs.h2467 uint64_t clkr:6; member
2483 uint64_t clkr:6;
2499 uint64_t clkr:6; member
2515 uint64_t clkr:6;
2532 uint64_t clkr:6; member
2548 uint64_t clkr:6;
/linux-4.4.14/drivers/net/can/
Drcar_can.c61 u8 clkr; /* Clock Select Register */ member