| /linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/ |
| H A D | reg_rdwr.h | 12 #ifndef REG_WRITE
13 #define REG_WRITE(type, addr, val) \ macro
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| H A D | irq_nmi_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | strcop_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | config_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | rt_trace_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | ata_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | bif_slave_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | marb_bp_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | marb_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
284 REG_WRITE( reg_##scope##_##reg, \
297 REG_WRITE( reg_##scope##_##reg, \
309 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
320 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | bif_core_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | eth_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | extmem_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | ser_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | sser_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | bif_dma_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | dma_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| /linux-4.4.14/drivers/gpu/drm/gma500/ |
| H A D | mdfld_dsi_dpi.c | 134 REG_WRITE(pipeconf_reg, BIT(31)); dsi_set_pipe_plane_enable_state()
141 REG_WRITE(dspcntr_reg, dspcntr); dsi_set_pipe_plane_enable_state()
157 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); dsi_set_pipe_plane_enable_state()
243 REG_WRITE(gen_data_reg, 0x00008036); mdfld_dsi_tpo_ic_init()
245 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
249 REG_WRITE(gen_data_reg, 0x005a5af0); mdfld_dsi_tpo_ic_init()
251 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
255 REG_WRITE(gen_data_reg, 0x005a5af1); mdfld_dsi_tpo_ic_init()
257 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
261 REG_WRITE(gen_data_reg, 0x005a5afc); mdfld_dsi_tpo_ic_init()
263 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
267 REG_WRITE(gen_data_reg, 0x770000b7); mdfld_dsi_tpo_ic_init()
269 REG_WRITE(gen_data_reg, 0x00000044); mdfld_dsi_tpo_ic_init()
271 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x05 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
275 REG_WRITE(gen_data_reg, 0x000a0ab6); mdfld_dsi_tpo_ic_init()
277 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
281 REG_WRITE(gen_data_reg, 0x081010f2); mdfld_dsi_tpo_ic_init()
283 REG_WRITE(gen_data_reg, 0x4a070708); mdfld_dsi_tpo_ic_init()
285 REG_WRITE(gen_data_reg, 0x000000c5); mdfld_dsi_tpo_ic_init()
287 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
291 REG_WRITE(gen_data_reg, 0x024003f8); mdfld_dsi_tpo_ic_init()
293 REG_WRITE(gen_data_reg, 0x01030a04); mdfld_dsi_tpo_ic_init()
295 REG_WRITE(gen_data_reg, 0x0e020220); mdfld_dsi_tpo_ic_init()
297 REG_WRITE(gen_data_reg, 0x00000004); mdfld_dsi_tpo_ic_init()
299 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x0d << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
303 REG_WRITE(gen_data_reg, 0x398fc3e2); mdfld_dsi_tpo_ic_init()
305 REG_WRITE(gen_data_reg, 0x0000916f); mdfld_dsi_tpo_ic_init()
307 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x06 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
311 REG_WRITE(gen_data_reg, 0x000000b0); mdfld_dsi_tpo_ic_init()
313 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
317 REG_WRITE(gen_data_reg, 0x240242f4); mdfld_dsi_tpo_ic_init()
319 REG_WRITE(gen_data_reg, 0x78ee2002); mdfld_dsi_tpo_ic_init()
321 REG_WRITE(gen_data_reg, 0x2a071050); mdfld_dsi_tpo_ic_init()
323 REG_WRITE(gen_data_reg, 0x507fee10); mdfld_dsi_tpo_ic_init()
325 REG_WRITE(gen_data_reg, 0x10300710); mdfld_dsi_tpo_ic_init()
327 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x14 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
331 REG_WRITE(gen_data_reg, 0x19fe07ba); mdfld_dsi_tpo_ic_init()
333 REG_WRITE(gen_data_reg, 0x101c0a31); mdfld_dsi_tpo_ic_init()
335 REG_WRITE(gen_data_reg, 0x00000010); mdfld_dsi_tpo_ic_init()
337 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
341 REG_WRITE(gen_data_reg, 0x28ff07bb); mdfld_dsi_tpo_ic_init()
343 REG_WRITE(gen_data_reg, 0x24280a31); mdfld_dsi_tpo_ic_init()
345 REG_WRITE(gen_data_reg, 0x00000034); mdfld_dsi_tpo_ic_init()
347 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
351 REG_WRITE(gen_data_reg, 0x535d05fb); mdfld_dsi_tpo_ic_init()
353 REG_WRITE(gen_data_reg, 0x1b1a2130); mdfld_dsi_tpo_ic_init()
355 REG_WRITE(gen_data_reg, 0x221e180e); mdfld_dsi_tpo_ic_init()
357 REG_WRITE(gen_data_reg, 0x131d2120); mdfld_dsi_tpo_ic_init()
359 REG_WRITE(gen_data_reg, 0x535d0508); mdfld_dsi_tpo_ic_init()
361 REG_WRITE(gen_data_reg, 0x1c1a2131); mdfld_dsi_tpo_ic_init()
363 REG_WRITE(gen_data_reg, 0x231f160d); mdfld_dsi_tpo_ic_init()
365 REG_WRITE(gen_data_reg, 0x111b2220); mdfld_dsi_tpo_ic_init()
367 REG_WRITE(gen_data_reg, 0x535c2008); mdfld_dsi_tpo_ic_init()
369 REG_WRITE(gen_data_reg, 0x1f1d2433); mdfld_dsi_tpo_ic_init()
371 REG_WRITE(gen_data_reg, 0x2c251a10); mdfld_dsi_tpo_ic_init()
373 REG_WRITE(gen_data_reg, 0x2c34372d); mdfld_dsi_tpo_ic_init()
375 REG_WRITE(gen_data_reg, 0x00000023); mdfld_dsi_tpo_ic_init()
377 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x31 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
381 REG_WRITE(gen_data_reg, 0x525c0bfa); mdfld_dsi_tpo_ic_init()
383 REG_WRITE(gen_data_reg, 0x1c1c232f); mdfld_dsi_tpo_ic_init()
385 REG_WRITE(gen_data_reg, 0x2623190e); mdfld_dsi_tpo_ic_init()
387 REG_WRITE(gen_data_reg, 0x18212625); mdfld_dsi_tpo_ic_init()
389 REG_WRITE(gen_data_reg, 0x545d0d0e); mdfld_dsi_tpo_ic_init()
391 REG_WRITE(gen_data_reg, 0x1e1d2333); mdfld_dsi_tpo_ic_init()
393 REG_WRITE(gen_data_reg, 0x26231a10); mdfld_dsi_tpo_ic_init()
395 REG_WRITE(gen_data_reg, 0x1a222725); mdfld_dsi_tpo_ic_init()
397 REG_WRITE(gen_data_reg, 0x545d280f); mdfld_dsi_tpo_ic_init()
399 REG_WRITE(gen_data_reg, 0x21202635); mdfld_dsi_tpo_ic_init()
401 REG_WRITE(gen_data_reg, 0x31292013); mdfld_dsi_tpo_ic_init()
403 REG_WRITE(gen_data_reg, 0x31393d33); mdfld_dsi_tpo_ic_init()
405 REG_WRITE(gen_data_reg, 0x00000029); mdfld_dsi_tpo_ic_init()
407 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x31 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
411 REG_WRITE(gen_data_reg, 0x000100f7); mdfld_dsi_tpo_ic_init()
413 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); mdfld_dsi_tpo_ic_init()
479 REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018); mdfld_dsi_dpi_controller_init()
482 REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff); mdfld_dsi_dpi_controller_init()
502 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), val); mdfld_dsi_dpi_controller_init()
504 REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe), mdfld_dsi_dpi_controller_init()
507 REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe), mdfld_dsi_dpi_controller_init()
511 REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe), mdfld_dsi_dpi_controller_init()
515 REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe), mdfld_dsi_dpi_controller_init()
518 REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe), mdfld_dsi_dpi_controller_init()
525 REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe), mdfld_dsi_dpi_controller_init()
527 REG_WRITE(MIPI_HBP_COUNT_REG(pipe), mdfld_dsi_dpi_controller_init()
529 REG_WRITE(MIPI_HFP_COUNT_REG(pipe), mdfld_dsi_dpi_controller_init()
531 REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe), mdfld_dsi_dpi_controller_init()
533 REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe), mdfld_dsi_dpi_controller_init()
535 REG_WRITE(MIPI_VBP_COUNT_REG(pipe), mdfld_dsi_dpi_controller_init()
537 REG_WRITE(MIPI_VFP_COUNT_REG(pipe), mdfld_dsi_dpi_controller_init()
540 REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x46); mdfld_dsi_dpi_controller_init()
543 REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0x000007d0); mdfld_dsi_dpi_controller_init()
547 REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), val); mdfld_dsi_dpi_controller_init()
549 REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000); mdfld_dsi_dpi_controller_init()
551 REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004); mdfld_dsi_dpi_controller_init()
555 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008); mdfld_dsi_dpi_controller_init()
557 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150c3408); mdfld_dsi_dpi_controller_init()
559 REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14); mdfld_dsi_dpi_controller_init()
574 REG_WRITE(MIPI_INTR_STAT_REG(pipe), mdfld_dsi_dpi_turn_on()
578 REG_WRITE(MIPI_DPI_CONTROL_REG(pipe), DSI_DPI_CTRL_HS_TURN_ON); mdfld_dsi_dpi_turn_on()
584 REG_WRITE(MIPI_INTR_STAT_REG(pipe), mdfld_dsi_dpi_turn_on()
613 REG_WRITE(MIPI_INTR_STAT_REG(pipe), mdfld_dsi_dpi_shut_down()
619 REG_WRITE(MIPI_DPI_CONTROL_REG(pipe), DSI_DPI_CTRL_HS_SHUTDOWN); mdfld_dsi_dpi_shut_down()
655 REG_WRITE(MIPI_PORT_CONTROL(pipe), mdfld_dsi_dpi_set_power()
672 REG_WRITE(MIPI_PORT_CONTROL(pipe), mdfld_dsi_dpi_set_power()
727 REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018); mipi_set_properties()
728 REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff); mipi_set_properties()
729 REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe), 0xffffff); mipi_set_properties()
730 REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe), 0xffffff); mipi_set_properties()
731 REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe), 0x14); mipi_set_properties()
732 REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe), 0xff); mipi_set_properties()
733 REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x25); mipi_set_properties()
734 REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0xf0); mipi_set_properties()
735 REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000); mipi_set_properties()
736 REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004); mipi_set_properties()
737 REG_WRITE(MIPI_DBI_BW_CTRL_REG(pipe), 0x00000820); mipi_set_properties()
738 REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14); mipi_set_properties()
752 REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe), mdfld_mipi_set_video_timing()
754 REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe), mdfld_mipi_set_video_timing()
756 REG_WRITE(MIPI_HBP_COUNT_REG(pipe), mdfld_mipi_set_video_timing()
758 REG_WRITE(MIPI_HFP_COUNT_REG(pipe), mdfld_mipi_set_video_timing()
760 REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe), mdfld_mipi_set_video_timing()
762 REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe), mdfld_mipi_set_video_timing()
764 REG_WRITE(MIPI_VBP_COUNT_REG(pipe), mdfld_mipi_set_video_timing()
766 REG_WRITE(MIPI_VFP_COUNT_REG(pipe), mdfld_mipi_set_video_timing()
776 REG_WRITE(MIPI_PORT_CONTROL(0), 0x00000002); mdfld_mipi_config()
777 REG_WRITE(MIPI_PORT_CONTROL(2), 0x80000000); mdfld_mipi_config()
779 REG_WRITE(MIPI_PORT_CONTROL(0), 0x80010000); mdfld_mipi_config()
780 REG_WRITE(MIPI_PORT_CONTROL(2), 0x00); mdfld_mipi_config()
783 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150A600F); mdfld_mipi_config()
784 REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), 0x0000000F); mdfld_mipi_config()
787 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); mdfld_mipi_config()
797 REG_WRITE(HTOTAL_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1)); mdfld_set_pipe_timing()
798 REG_WRITE(HBLANK_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1)); mdfld_set_pipe_timing()
799 REG_WRITE(HSYNC_A, mdfld_set_pipe_timing()
802 REG_WRITE(VTOTAL_A, ((mode->vtotal - 1) << 16) | (mode->vdisplay - 1)); mdfld_set_pipe_timing()
803 REG_WRITE(VBLANK_A, ((mode->vtotal - 1) << 16) | (mode->vdisplay - 1)); mdfld_set_pipe_timing()
804 REG_WRITE(VSYNC_A, mdfld_set_pipe_timing()
807 REG_WRITE(PIPEASRC, mdfld_set_pipe_timing()
855 REG_WRITE(MRST_DPLL_A, 0x00); mdfld_dsi_dpi_mode_set()
856 REG_WRITE(MRST_FPA0, 0xC1); mdfld_dsi_dpi_mode_set()
857 REG_WRITE(MRST_DPLL_A, 0x00800000); mdfld_dsi_dpi_mode_set()
859 REG_WRITE(MRST_DPLL_A, 0x80800000); mdfld_dsi_dpi_mode_set()
865 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008); mdfld_dsi_dpi_mode_set()
871 REG_WRITE(DSPABASE, 0x00); mdfld_dsi_dpi_mode_set()
872 REG_WRITE(DSPASIZE, mdfld_dsi_dpi_mode_set()
875 REG_WRITE(DSPACNTR, 0x98000000); mdfld_dsi_dpi_mode_set()
876 REG_WRITE(DSPASURF, 0x00); mdfld_dsi_dpi_mode_set()
878 REG_WRITE(VGACNTRL, 0x80000000); mdfld_dsi_dpi_mode_set()
879 REG_WRITE(DEVICE_READY_REG, 0x00000001); mdfld_dsi_dpi_mode_set()
881 REG_WRITE(MIPI_PORT_CONTROL(pipe), 0x80810000); mdfld_dsi_dpi_mode_set()
884 REG_WRITE(MIPI_PORT_CONTROL(pipe), mipi); mdfld_dsi_dpi_mode_set()
903 REG_WRITE(pipeconf_reg, pipeconf); mdfld_dsi_dpi_mode_set()
907 REG_WRITE(dspcntr_reg, dspcntr); mdfld_dsi_dpi_mode_set()
|
| H A D | oaktrail_hdmi.c | 288 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); oaktrail_crtc_hdmi_mode_set()
293 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); oaktrail_crtc_hdmi_mode_set()
294 REG_WRITE(DPLL_DIV_CTRL, 0x00000000); oaktrail_crtc_hdmi_mode_set()
295 REG_WRITE(DPLL_STATUS, 0x1); oaktrail_crtc_hdmi_mode_set()
310 REG_WRITE(DPLL_CTRL, 0x00000008); oaktrail_crtc_hdmi_mode_set()
311 REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr)); oaktrail_crtc_hdmi_mode_set()
312 REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1)); oaktrail_crtc_hdmi_mode_set()
313 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); oaktrail_crtc_hdmi_mode_set()
314 REG_WRITE(DPLL_UPDATE, 0x80000000); oaktrail_crtc_hdmi_mode_set()
315 REG_WRITE(DPLL_CLK_ENABLE, 0x80050102); oaktrail_crtc_hdmi_mode_set()
326 REG_WRITE(htot_reg, temp); oaktrail_crtc_hdmi_mode_set()
327 REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); oaktrail_crtc_hdmi_mode_set()
328 REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); oaktrail_crtc_hdmi_mode_set()
329 REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16)); oaktrail_crtc_hdmi_mode_set()
330 REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16)); oaktrail_crtc_hdmi_mode_set()
331 REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); oaktrail_crtc_hdmi_mode_set()
332 REG_WRITE(pipesrc_reg, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1)); oaktrail_crtc_hdmi_mode_set()
334 REG_WRITE(PCH_HTOTAL_B, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); oaktrail_crtc_hdmi_mode_set()
335 REG_WRITE(PCH_HBLANK_B, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); oaktrail_crtc_hdmi_mode_set()
336 REG_WRITE(PCH_HSYNC_B, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); oaktrail_crtc_hdmi_mode_set()
337 REG_WRITE(PCH_VTOTAL_B, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16)); oaktrail_crtc_hdmi_mode_set()
338 REG_WRITE(PCH_VBLANK_B, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16)); oaktrail_crtc_hdmi_mode_set()
339 REG_WRITE(PCH_VSYNC_B, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); oaktrail_crtc_hdmi_mode_set()
340 REG_WRITE(PCH_PIPEBSRC, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1)); oaktrail_crtc_hdmi_mode_set()
345 REG_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); oaktrail_crtc_hdmi_mode_set()
346 REG_WRITE(dsppos_reg, 0); oaktrail_crtc_hdmi_mode_set()
364 REG_WRITE(pipeconf_reg, pipeconf); oaktrail_crtc_hdmi_mode_set()
367 REG_WRITE(PCH_PIPEBCONF, pipeconf); oaktrail_crtc_hdmi_mode_set()
371 REG_WRITE(dspcntr_reg, dspcntr); oaktrail_crtc_hdmi_mode_set()
388 REG_WRITE(VGACNTRL, 0x80000000); oaktrail_crtc_hdmi_dpms()
393 REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE); oaktrail_crtc_hdmi_dpms()
396 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); oaktrail_crtc_hdmi_dpms()
403 REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE); oaktrail_crtc_hdmi_dpms()
410 REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE); oaktrail_crtc_hdmi_dpms()
420 REG_WRITE(DPLL_CTRL, temp | (DPLL_PWRDN | DPLL_RESET)); oaktrail_crtc_hdmi_dpms()
421 REG_WRITE(DPLL_STATUS, 0x1); oaktrail_crtc_hdmi_dpms()
434 REG_WRITE(DPLL_CTRL, temp & ~(DPLL_PWRDN | DPLL_RESET)); oaktrail_crtc_hdmi_dpms()
436 REG_WRITE(DPLL_CLK_ENABLE, temp | DPLL_EN_DISP | DPLL_SEL_HDMI | DPLL_EN_HDMI); oaktrail_crtc_hdmi_dpms()
445 REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE); oaktrail_crtc_hdmi_dpms()
452 REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE); oaktrail_crtc_hdmi_dpms()
461 REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE); oaktrail_crtc_hdmi_dpms()
463 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); oaktrail_crtc_hdmi_dpms()
471 REG_WRITE(DSPARB, 0x00003fbf); oaktrail_crtc_hdmi_dpms()
474 REG_WRITE(0x70034, 0x3f880a0a); oaktrail_crtc_hdmi_dpms()
477 REG_WRITE(0x70038, 0x0b060808); oaktrail_crtc_hdmi_dpms()
480 REG_WRITE(0x70050, 0x08030404); oaktrail_crtc_hdmi_dpms()
483 REG_WRITE(0x70054, 0x04040404); oaktrail_crtc_hdmi_dpms()
486 REG_WRITE(0x70400, 0x4000); oaktrail_crtc_hdmi_dpms()
|
| H A D | cdv_device.c | 46 REG_WRITE(vga_reg, VGA_DISP_DISABLE); cdv_disable_vga()
146 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | cdv_set_brightness()
327 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); cdv_restore_display_registers()
328 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); cdv_restore_display_registers()
331 REG_WRITE(DPIO_CFG, 0); cdv_restore_display_registers()
332 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); cdv_restore_display_registers()
336 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); cdv_restore_display_registers()
342 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); cdv_restore_display_registers()
348 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); cdv_restore_display_registers()
349 REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]); cdv_restore_display_registers()
350 REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]); cdv_restore_display_registers()
351 REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]); cdv_restore_display_registers()
352 REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]); cdv_restore_display_registers()
353 REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]); cdv_restore_display_registers()
355 REG_WRITE(DSPARB, regs->cdv.saveDSPARB); cdv_restore_display_registers()
356 REG_WRITE(ADPA, regs->cdv.saveADPA); cdv_restore_display_registers()
358 REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2); cdv_restore_display_registers()
359 REG_WRITE(LVDS, regs->cdv.saveLVDS); cdv_restore_display_registers()
360 REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL); cdv_restore_display_registers()
361 REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS); cdv_restore_display_registers()
362 REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL); cdv_restore_display_registers()
363 REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS); cdv_restore_display_registers()
364 REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS); cdv_restore_display_registers()
365 REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE); cdv_restore_display_registers()
366 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); cdv_restore_display_registers()
368 REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL); cdv_restore_display_registers()
370 REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER); cdv_restore_display_registers()
371 REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR); cdv_restore_display_registers()
447 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); cdv_hotplug_event()
457 REG_WRITE(PORT_HOTPLUG_EN, hotplug); cdv_hotplug_enable()
459 REG_WRITE(PORT_HOTPLUG_EN, 0); cdv_hotplug_enable()
460 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); cdv_hotplug_enable()
|
| H A D | gma_display.c | 86 REG_WRITE(map->stride, crtc->primary->fb->pitches[0]); gma_pipe_set_base()
110 REG_WRITE(map->cntr, dspcntr); gma_pipe_set_base()
119 REG_WRITE(map->base, offset + start); gma_pipe_set_base()
122 REG_WRITE(map->base, offset); gma_pipe_set_base()
124 REG_WRITE(map->surf, start); gma_pipe_set_base()
154 REG_WRITE(palreg + 4 * i, gma_crtc_load_lut()
228 REG_WRITE(map->dpll, temp); gma_crtc_dpms()
232 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); gma_crtc_dpms()
236 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); gma_crtc_dpms()
245 REG_WRITE(map->cntr, gma_crtc_dpms()
248 REG_WRITE(map->base, REG_READ(map->base)); gma_crtc_dpms()
256 REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); gma_crtc_dpms()
261 REG_WRITE(map->status, temp); gma_crtc_dpms()
281 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); gma_crtc_dpms()
292 REG_WRITE(map->cntr, gma_crtc_dpms()
295 REG_WRITE(map->base, REG_READ(map->base)); gma_crtc_dpms()
302 REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); gma_crtc_dpms()
314 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); gma_crtc_dpms()
327 REG_WRITE(DSPARB, 0x3F3E); gma_crtc_dpms()
355 REG_WRITE(control, temp); gma_crtc_cursor_set()
356 REG_WRITE(base, 0); gma_crtc_cursor_set()
435 REG_WRITE(control, temp); gma_crtc_cursor_set()
436 REG_WRITE(base, addr); gma_crtc_cursor_set()
481 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); gma_crtc_cursor_move()
482 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr); gma_crtc_cursor_move()
614 REG_WRITE(map->dpll, gma_crtc_restore()
620 REG_WRITE(map->fp0, crtc_state->saveFP0); gma_crtc_restore()
623 REG_WRITE(map->fp1, crtc_state->saveFP1); gma_crtc_restore()
626 REG_WRITE(map->dpll, crtc_state->saveDPLL); gma_crtc_restore()
630 REG_WRITE(map->htotal, crtc_state->saveHTOTAL); gma_crtc_restore()
631 REG_WRITE(map->hblank, crtc_state->saveHBLANK); gma_crtc_restore()
632 REG_WRITE(map->hsync, crtc_state->saveHSYNC); gma_crtc_restore()
633 REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); gma_crtc_restore()
634 REG_WRITE(map->vblank, crtc_state->saveVBLANK); gma_crtc_restore()
635 REG_WRITE(map->vsync, crtc_state->saveVSYNC); gma_crtc_restore()
636 REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); gma_crtc_restore()
638 REG_WRITE(map->size, crtc_state->saveDSPSIZE); gma_crtc_restore()
639 REG_WRITE(map->pos, crtc_state->saveDSPPOS); gma_crtc_restore()
641 REG_WRITE(map->src, crtc_state->savePIPESRC); gma_crtc_restore()
642 REG_WRITE(map->base, crtc_state->saveDSPBASE); gma_crtc_restore()
643 REG_WRITE(map->conf, crtc_state->savePIPECONF); gma_crtc_restore()
647 REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); gma_crtc_restore()
648 REG_WRITE(map->base, crtc_state->saveDSPBASE); gma_crtc_restore()
654 REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]); gma_crtc_restore()
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| H A D | mdfld_intel_display.c | 143 REG_WRITE(dspcntr_reg, dspcntr); mdfld__intel_plane_set_alpha()
201 REG_WRITE(map->stride, crtc->primary->fb->pitches[0]); mdfld__intel_pipe_set_base()
220 REG_WRITE(map->cntr, dspcntr); mdfld__intel_pipe_set_base()
224 REG_WRITE(map->linoff, offset); mdfld__intel_pipe_set_base()
226 REG_WRITE(map->surf, start); mdfld__intel_pipe_set_base()
254 REG_WRITE(map->cntr, mdfld_disable_crtc()
257 REG_WRITE(map->base, REG_READ(map->base)); mdfld_disable_crtc()
268 REG_WRITE(map->conf, temp); mdfld_disable_crtc()
281 REG_WRITE(map->dpll, temp); mdfld_disable_crtc()
289 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); mdfld_disable_crtc()
338 REG_WRITE(map->dpll, temp); mdfld_crtc_dpms()
343 REG_WRITE(map->dpll, temp); mdfld_crtc_dpms()
348 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); mdfld_crtc_dpms()
366 REG_WRITE(map->cntr, mdfld_crtc_dpms()
369 REG_WRITE(map->base, REG_READ(map->base)); mdfld_crtc_dpms()
375 REG_WRITE(map->conf, pipeconf); mdfld_crtc_dpms()
384 REG_WRITE(map->status, REG_READ(map->status)); mdfld_crtc_dpms()
392 REG_WRITE(map->cntr, mdfld_crtc_dpms()
394 REG_WRITE(map->base, REG_READ(map->base)); mdfld_crtc_dpms()
396 REG_WRITE(0xb048, 1); mdfld_crtc_dpms()
400 REG_WRITE(map->conf, temp); mdfld_crtc_dpms()
402 REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 0); mdfld_crtc_dpms()
404 REG_WRITE(0xb004, REG_READ(0xb004)); mdfld_crtc_dpms()
406 REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 1); mdfld_crtc_dpms()
408 REG_WRITE(map->cntr, mdfld_crtc_dpms()
410 REG_WRITE(map->base, REG_READ(map->base)); mdfld_crtc_dpms()
412 REG_WRITE(0xb048, 2); mdfld_crtc_dpms()
416 REG_WRITE(map->conf, temp); mdfld_crtc_dpms()
437 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); mdfld_crtc_dpms()
442 REG_WRITE(map->cntr, mdfld_crtc_dpms()
445 REG_WRITE(map->base, REG_READ(map->base)); mdfld_crtc_dpms()
454 REG_WRITE(map->conf, temp); mdfld_crtc_dpms()
467 REG_WRITE(map->dpll, temp); mdfld_crtc_dpms()
766 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); mdfld_crtc_mode_set()
770 REG_WRITE(PFIT_CONTROL, 0); mdfld_crtc_mode_set()
787 REG_WRITE(map->size, ((min(mode->crtc_vdisplay, adjusted_mode->crtc_vdisplay) - 1) << 16) mdfld_crtc_mode_set()
790 REG_WRITE(map->src, ((mode->crtc_hdisplay - 1) << 16) mdfld_crtc_mode_set()
793 REG_WRITE(map->size, mdfld_crtc_mode_set()
796 REG_WRITE(map->src, mdfld_crtc_mode_set()
801 REG_WRITE(map->pos, 0); mdfld_crtc_mode_set()
819 REG_WRITE(map->htotal, (mode->crtc_hdisplay - 1) | mdfld_crtc_mode_set()
821 REG_WRITE(map->vtotal, (mode->crtc_vdisplay - 1) | mdfld_crtc_mode_set()
823 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - mdfld_crtc_mode_set()
826 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - mdfld_crtc_mode_set()
829 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - mdfld_crtc_mode_set()
832 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - mdfld_crtc_mode_set()
836 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | mdfld_crtc_mode_set()
838 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | mdfld_crtc_mode_set()
840 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | mdfld_crtc_mode_set()
842 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | mdfld_crtc_mode_set()
844 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | mdfld_crtc_mode_set()
846 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | mdfld_crtc_mode_set()
932 REG_WRITE(map->dpll, dpll); mdfld_crtc_mode_set()
940 REG_WRITE(map->fp0, 0); mdfld_crtc_mode_set()
942 REG_WRITE(map->dpll, dpll); mdfld_crtc_mode_set()
951 REG_WRITE(map->dpll, dpll); mdfld_crtc_mode_set()
992 REG_WRITE(map->fp0, fp); mdfld_crtc_mode_set()
993 REG_WRITE(map->dpll, dpll); mdfld_crtc_mode_set()
998 REG_WRITE(map->dpll, dpll); mdfld_crtc_mode_set()
1013 REG_WRITE(map->conf, dev_priv->pipeconf[pipe]); mdfld_crtc_mode_set()
1017 REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]); mdfld_crtc_mode_set()
|
| H A D | psb_intel_display.c | 219 REG_WRITE(PFIT_CONTROL, 0); psb_intel_crtc_mode_set()
224 REG_WRITE(map->fp0, fp); psb_intel_crtc_mode_set()
225 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); psb_intel_crtc_mode_set()
255 REG_WRITE(LVDS, lvds); psb_intel_crtc_mode_set()
259 REG_WRITE(map->fp0, fp); psb_intel_crtc_mode_set()
260 REG_WRITE(map->dpll, dpll); psb_intel_crtc_mode_set()
266 REG_WRITE(map->dpll, dpll); psb_intel_crtc_mode_set()
272 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | psb_intel_crtc_mode_set()
274 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | psb_intel_crtc_mode_set()
276 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | psb_intel_crtc_mode_set()
278 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | psb_intel_crtc_mode_set()
280 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | psb_intel_crtc_mode_set()
282 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | psb_intel_crtc_mode_set()
287 REG_WRITE(map->size, psb_intel_crtc_mode_set()
289 REG_WRITE(map->pos, 0); psb_intel_crtc_mode_set()
290 REG_WRITE(map->src, psb_intel_crtc_mode_set()
292 REG_WRITE(map->conf, pipeconf); psb_intel_crtc_mode_set()
297 REG_WRITE(map->cntr, dspcntr); psb_intel_crtc_mode_set()
487 REG_WRITE(control[gma_crtc->pipe], 0); psb_intel_cursor_init()
488 REG_WRITE(base[gma_crtc->pipe], 0); psb_intel_cursor_init()
|
| H A D | cdv_intel_display.c | 149 REG_WRITE(SB_ADDR, reg); cdv_sb_read()
150 REG_WRITE(SB_PCKT, cdv_sb_read()
184 REG_WRITE(SB_ADDR, reg); cdv_sb_write()
185 REG_WRITE(SB_DATA, val); cdv_sb_write()
186 REG_WRITE(SB_PCKT, cdv_sb_write()
211 REG_WRITE(DPIO_CFG, 0); cdv_sb_reset()
213 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); cdv_sb_reset()
236 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); cdv_dpll_set_clock_cdv()
482 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); cdv_disable_sr()
490 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); cdv_disable_sr()
512 REG_WRITE(DSPFW1, fw); cdv_update_wm()
519 REG_WRITE(DSPFW2, fw); cdv_update_wm()
521 REG_WRITE(DSPFW3, 0x36000000); cdv_update_wm()
528 REG_WRITE(DSPFW5, 0x00040330); cdv_update_wm()
534 REG_WRITE(DSPFW5, fw); cdv_update_wm()
537 REG_WRITE(DSPFW6, 0x10); cdv_update_wm()
542 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); cdv_update_wm()
549 REG_WRITE(DSPFW1, 0x3f880808); cdv_update_wm()
550 REG_WRITE(DSPFW2, 0x0b020202); cdv_update_wm()
551 REG_WRITE(DSPFW3, 0x24000000); cdv_update_wm()
552 REG_WRITE(DSPFW4, 0x08030202); cdv_update_wm()
553 REG_WRITE(DSPFW5, 0x01010101); cdv_update_wm()
554 REG_WRITE(DSPFW6, 0x1d0); cdv_update_wm()
684 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0); cdv_intel_crtc_mode_set()
685 REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0); cdv_intel_crtc_mode_set()
686 REG_WRITE(PIPE_DP_LINK_M(pipe), 0); cdv_intel_crtc_mode_set()
687 REG_WRITE(PIPE_DP_LINK_N(pipe), 0); cdv_intel_crtc_mode_set()
736 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); cdv_intel_crtc_mode_set()
768 REG_WRITE(LVDS, lvds); cdv_intel_crtc_mode_set()
776 REG_WRITE(PFIT_CONTROL, 0); cdv_intel_crtc_mode_set()
781 REG_WRITE(map->dpll, cdv_intel_crtc_mode_set()
794 REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); cdv_intel_crtc_mode_set()
797 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | cdv_intel_crtc_mode_set()
799 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | cdv_intel_crtc_mode_set()
801 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | cdv_intel_crtc_mode_set()
803 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | cdv_intel_crtc_mode_set()
805 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | cdv_intel_crtc_mode_set()
807 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | cdv_intel_crtc_mode_set()
812 REG_WRITE(map->size, cdv_intel_crtc_mode_set()
814 REG_WRITE(map->pos, 0); cdv_intel_crtc_mode_set()
815 REG_WRITE(map->src, cdv_intel_crtc_mode_set()
817 REG_WRITE(map->conf, pipeconf); cdv_intel_crtc_mode_set()
822 REG_WRITE(map->cntr, dspcntr); cdv_intel_crtc_mode_set()
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| H A D | oaktrail_crtc.c | 336 REG_WRITE(DSPARB, 0x3f80); oaktrail_crtc_dpms()
337 REG_WRITE(DSPFW1, 0x3f8f0404); oaktrail_crtc_dpms()
338 REG_WRITE(DSPFW2, 0x04040f04); oaktrail_crtc_dpms()
339 REG_WRITE(DSPFW3, 0x0); oaktrail_crtc_dpms()
340 REG_WRITE(DSPFW4, 0x04040404); oaktrail_crtc_dpms()
341 REG_WRITE(DSPFW5, 0x04040404); oaktrail_crtc_dpms()
342 REG_WRITE(DSPFW6, 0x78); oaktrail_crtc_dpms()
343 REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040); oaktrail_crtc_dpms()
427 REG_WRITE(PFIT_CONTROL, 0); oaktrail_crtc_mode_set()
622 REG_WRITE(map->stride, crtc->primary->fb->pitches[0]); oaktrail_pipe_set_base()
646 REG_WRITE(map->cntr, dspcntr); oaktrail_pipe_set_base()
648 REG_WRITE(map->base, offset); oaktrail_pipe_set_base()
650 REG_WRITE(map->surf, start); oaktrail_pipe_set_base()
|
| H A D | oaktrail_lvds.c | 56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | oaktrail_lvds_set_power()
67 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & oaktrail_lvds_set_power()
122 REG_WRITE(LVDS, lvds_port); oaktrail_lvds_mode_set()
141 REG_WRITE(PFIT_CONTROL, 0); oaktrail_lvds_mode_set()
147 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); oaktrail_lvds_mode_set()
151 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | oaktrail_lvds_mode_set()
154 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | oaktrail_lvds_mode_set()
157 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); oaktrail_lvds_mode_set()
159 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); oaktrail_lvds_mode_set()
|
| H A D | psb_intel_lvds.c | 159 REG_WRITE(BLC_PWM_CTL, psb_lvds_pwm_set_brightness()
203 REG_WRITE(BLC_PWM_CTL, psb_intel_lvds_set_backlight()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | psb_intel_lvds_set_power()
243 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & psb_intel_lvds_set_power()
321 REG_WRITE(BLC_PWM_CTL, lvds_priv->saveBLC_PWM_CTL); psb_intel_lvds_restore()
322 REG_WRITE(PFIT_CONTROL, lvds_priv->savePFIT_CONTROL); psb_intel_lvds_restore()
323 REG_WRITE(PFIT_PGM_RATIOS, lvds_priv->savePFIT_PGM_RATIOS); psb_intel_lvds_restore()
324 REG_WRITE(LVDSPP_ON, lvds_priv->savePP_ON); psb_intel_lvds_restore()
325 REG_WRITE(LVDSPP_OFF, lvds_priv->savePP_OFF); psb_intel_lvds_restore()
326 /*REG_WRITE(PP_DIVISOR, lvds_priv->savePP_DIVISOR);*/ psb_intel_lvds_restore()
327 REG_WRITE(PP_CYCLE, lvds_priv->savePP_CYCLE); psb_intel_lvds_restore()
328 REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL); psb_intel_lvds_restore()
329 REG_WRITE(LVDS, lvds_priv->saveLVDS); psb_intel_lvds_restore()
332 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | psb_intel_lvds_restore()
338 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & psb_intel_lvds_restore()
499 REG_WRITE(PFIT_CONTROL, pfit_control); psb_intel_lvds_mode_set()
|
| H A D | psb_lid.c | 40 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); psb_lid_timer_func()
56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); psb_lid_timer_func()
|
| H A D | cdv_intel_crt.c | 64 REG_WRITE(reg, temp); cdv_intel_crt_dpms()
109 REG_WRITE(dpll_md_reg, cdv_intel_crt_mode_set()
124 REG_WRITE(adpa_reg, adpa); cdv_intel_crt_mode_set()
158 REG_WRITE(PORT_HOTPLUG_EN, hotplug_en); cdv_intel_crt_detect_hotplug()
174 REG_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); cdv_intel_crt_detect_hotplug()
177 REG_WRITE(PORT_HOTPLUG_EN, orig); cdv_intel_crt_detect_hotplug()
|
| H A D | mdfld_dsi_pkg_sender.c | 171 REG_WRITE(intr_stat_reg, mask); handle_dsi_error()
176 REG_WRITE(intr_stat_reg, mask); handle_dsi_error()
236 REG_WRITE(ctrl_reg, val); send_short_pkg()
272 REG_WRITE(data_reg, b4 << 24 | b3 << 16 | b2 << 8 | b1); send_long_pkg()
294 REG_WRITE(data_reg, b3 << 16 | b2 << 8 | b1); send_long_pkg()
300 REG_WRITE(ctrl_reg, val); send_long_pkg()
541 REG_WRITE(sender->mipi_intr_stat_reg, BIT(29)); __read_panel_data()
560 REG_WRITE(sender->mipi_intr_stat_reg, BIT(29)); __read_panel_data()
656 REG_WRITE(MIPI_PORT_CONTROL(pipe), mipi_val); mdfld_dsi_pkg_sender_init()
|
| H A D | cdv_intel_dp.c | 393 REG_WRITE(PP_CONTROL, pp); cdv_intel_edp_panel_vdd_on()
407 REG_WRITE(PP_CONTROL, pp); cdv_intel_edp_panel_vdd_off()
427 REG_WRITE(PP_CONTROL, pp); cdv_intel_edp_panel_on()
460 REG_WRITE(PP_CONTROL, pp); cdv_intel_edp_panel_off()
488 REG_WRITE(PP_CONTROL, pp); cdv_intel_edp_backlight_on()
504 REG_WRITE(PP_CONTROL, pp); cdv_intel_edp_backlight_off()
605 REG_WRITE(ch_data + i, cdv_intel_dp_aux_ch()
609 REG_WRITE(ch_ctl, cdv_intel_dp_aux_ch()
626 REG_WRITE(ch_ctl, cdv_intel_dp_aux_ch()
1028 REG_WRITE(PIPE_GMCH_DATA_M(pipe), cdv_intel_dp_set_m_n()
1031 REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); cdv_intel_dp_set_m_n()
1032 REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); cdv_intel_dp_set_m_n()
1033 REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); cdv_intel_dp_set_m_n()
1088 REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN)); cdv_intel_dp_mode_set()
1102 REG_WRITE(PFIT_CONTROL, pfit_control); cdv_intel_dp_mode_set()
1393 REG_WRITE(intel_dp->output_reg, dp_reg_value); cdv_intel_dp_set_link_train()
1515 REG_WRITE(intel_dp->output_reg, reg); cdv_intel_dp_start_link_train()
1671 REG_WRITE(intel_dp->output_reg, reg); cdv_intel_dp_complete_link_train()
1692 REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); cdv_intel_dp_link_down()
1698 REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); cdv_intel_dp_link_down()
1990 REG_WRITE(DSPCLK_GATE_D, reg_value); cdv_disable_intel_clock_gating()
2074 REG_WRITE(PP_CONTROL, pp_on); cdv_intel_dp_init()
2078 REG_WRITE(BLC_PWM_CTL2, pwm_ctrl); cdv_intel_dp_init()
|
| H A D | cdv_intel_hdmi.c | 88 REG_WRITE(hdmi_priv->hdmi_reg, hdmib); cdv_hdmi_mode_set()
102 REG_WRITE(hdmi_priv->hdmi_reg, hdmib & ~HDMIB_PORT_EN); cdv_hdmi_dpms()
104 REG_WRITE(hdmi_priv->hdmi_reg, hdmib | HDMIB_PORT_EN); cdv_hdmi_dpms()
123 REG_WRITE(hdmi_priv->hdmi_reg, hdmi_priv->save_HDMIB); cdv_hdmi_restore()
|
| H A D | intel_i2c.c | 69 REG_WRITE(chan->reg, reserved | clock_bits); set_clock()
91 REG_WRITE(chan->reg, reserved | data_bits); set_data()
|
| H A D | cdv_intel_lvds.c | 145 REG_WRITE(BLC_PWM_CTL,
184 REG_WRITE(BLC_PWM_CTL, cdv_intel_lvds_set_backlight()
209 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | cdv_intel_lvds_set_power()
220 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & cdv_intel_lvds_set_power()
386 REG_WRITE(PFIT_CONTROL, pfit_control); cdv_intel_lvds_mode_set()
772 REG_WRITE(BLC_PWM_CTL2, pwm); cdv_intel_lvds_init()
|
| H A D | mdfld_device.c | 385 REG_WRITE(mipi_reg, temp); mdfld_restore_display_registers()
394 REG_WRITE(device_ready_reg, temp); mdfld_restore_display_registers()
400 REG_WRITE(device_ready_reg, temp); mdfld_restore_display_registers()
|
| H A D | oaktrail_device.c | 94 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); oaktrail_set_brightness()
95 REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl); oaktrail_set_brightness()
135 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); device_backlight_init()
136 REG_WRITE(BLC_PWM_CTL, value | (value << 16)); device_backlight_init()
|
| H A D | psb_device.c | 98 REG_WRITE(BLC_PWM_CTL, psb_backlight_setup()
|
| H A D | psb_drv.h | 868 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) macro
877 REG_WRITE(reg, val); REGISTER_WRITE_WITH_AUX()
|
| H A D | intel_gmbus.c | 96 REG_WRITE(DSPCLK_GATE_D, val); intel_i2c_quirk_set()
|
| H A D | mdfld_dsi_output.h | 51 REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end))
|
| H A D | psb_irq.c | 299 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); psb_irq_handler()
|
| H A D | psb_intel_sdvo.c | 1821 REG_WRITE(sdvo->sdvo_reg, sdvo->saveSDVO); psb_intel_sdvo_restore()
|
| /linux-4.4.14/drivers/net/wireless/ath/ |
| H A D | key.c | 26 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
57 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); ath_hw_keyreset()
58 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); ath_hw_keyreset()
59 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); ath_hw_keyreset()
60 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); ath_hw_keyreset()
61 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); ath_hw_keyreset()
62 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); ath_hw_keyreset()
63 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); ath_hw_keyreset()
64 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); ath_hw_keyreset()
69 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); ath_hw_keyreset()
70 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); ath_hw_keyreset()
71 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); ath_hw_keyreset()
72 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); ath_hw_keyreset()
74 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); ath_hw_keyreset()
75 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), ath_hw_keyreset()
121 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); ath_hw_keysetmac()
122 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag); ath_hw_keysetmac()
208 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); ath_hw_set_keycache_entry()
209 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); ath_hw_set_keycache_entry()
212 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); ath_hw_set_keycache_entry()
213 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); ath_hw_set_keycache_entry()
216 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); ath_hw_set_keycache_entry()
217 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); ath_hw_set_keycache_entry()
246 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); ath_hw_set_keycache_entry()
247 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); ath_hw_set_keycache_entry()
250 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); ath_hw_set_keycache_entry()
251 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); ath_hw_set_keycache_entry()
254 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); ath_hw_set_keycache_entry()
255 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), ath_hw_set_keycache_entry()
285 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); ath_hw_set_keycache_entry()
286 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); ath_hw_set_keycache_entry()
289 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); ath_hw_set_keycache_entry()
290 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); ath_hw_set_keycache_entry()
293 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); ath_hw_set_keycache_entry()
294 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), ath_hw_set_keycache_entry()
303 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); ath_hw_set_keycache_entry()
304 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); ath_hw_set_keycache_entry()
311 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); ath_hw_set_keycache_entry()
312 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); ath_hw_set_keycache_entry()
319 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); ath_hw_set_keycache_entry()
320 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); ath_hw_set_keycache_entry()
323 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); ath_hw_set_keycache_entry()
324 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); ath_hw_set_keycache_entry()
327 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); ath_hw_set_keycache_entry()
328 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); ath_hw_set_keycache_entry()
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| H A D | hw.c | 24 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
123 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); ath_hw_setbssidmask()
126 REG_WRITE(ah, AR_STA_ID1, id1); ath_hw_setbssidmask()
128 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(common->bssidmask)); ath_hw_setbssidmask()
129 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(common->bssidmask + 4)); ath_hw_setbssidmask()
148 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); ath_hw_cycle_counters_update()
157 REG_WRITE(ah, AR_CCCNT, 0); ath_hw_cycle_counters_update()
158 REG_WRITE(ah, AR_RFCNT, 0); ath_hw_cycle_counters_update()
159 REG_WRITE(ah, AR_RCCNT, 0); ath_hw_cycle_counters_update()
160 REG_WRITE(ah, AR_TFCNT, 0); ath_hw_cycle_counters_update()
163 REG_WRITE(ah, AR_MIBC, 0); ath_hw_cycle_counters_update()
|
| /linux-4.4.14/drivers/net/wireless/ath/ath9k/ |
| H A D | ar9003_wow.c | 44 REG_WRITE(ah, AR_CR, AR_CR_RXD); ath9k_hw_set_powermode_wow_sleep()
62 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); ath9k_hw_set_powermode_wow_sleep()
64 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT); ath9k_hw_set_powermode_wow_sleep()
92 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); ath9k_wow_create_keep_alive_pattern()
111 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0); ath9k_wow_create_keep_alive_pattern()
118 REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]); ath9k_wow_create_keep_alive_pattern()
139 REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i), ath9k_hw_wow_apply_pattern()
146 REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val); ath9k_hw_wow_apply_pattern()
235 REG_WRITE(ah, AR_WOW_PATTERN, ath9k_hw_wow_wakeup()
237 REG_WRITE(ah, AR_MAC_PCU_WOW4, ath9k_hw_wow_wakeup()
243 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); ath9k_hw_wow_wakeup()
286 REG_WRITE(ah, AR_WA, wa_reg); ath9k_hw_wow_set_arwr_reg()
339 REG_WRITE(ah, AR_WOW_BCN_TIMO, AR_WOW_BEACON_TIMO); ath9k_hw_wow_enable()
341 REG_WRITE(ah, AR_WOW_BCN_TIMO, AR_WOW_BEACON_TIMO_MAX); ath9k_hw_wow_enable()
347 REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, AR_WOW_KEEP_ALIVE_NEVER); ath9k_hw_wow_enable()
349 REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, KAL_TIMEOUT * 32); ath9k_hw_wow_enable()
354 REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, KAL_DELAY * 1000); ath9k_hw_wow_enable()
376 REG_WRITE(ah, AR_WOW_KEEP_ALIVE, keep_alive); ath9k_hw_wow_enable()
405 REG_WRITE(ah, AR_WOW_PATTERN, magic_pattern); ath9k_hw_wow_enable()
411 REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B, ath9k_hw_wow_enable()
433 REG_WRITE(ah, AR_PCIE_PM_CTRL, host_pm_ctrl); ath9k_hw_wow_enable()
446 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); ath9k_hw_wow_enable()
|
| H A D | ar9003_aic.c | 111 REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00); ar9003_aic_gain_table()
112 REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438); ar9003_aic_gain_table()
155 REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000), ar9003_aic_gain_table()
160 REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), ar9003_aic_gain_table()
171 REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000), ar9003_aic_cal_start()
176 REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), 0); ar9003_aic_cal_start()
180 REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B0, ar9003_aic_cal_start()
190 REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B1, ar9003_aic_cal_start()
197 REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B0, ar9003_aic_cal_start()
206 REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B1, ar9003_aic_cal_start()
210 REG_WRITE(ah, AR_PHY_AIC_CTRL_2_B0, ar9003_aic_cal_start()
220 REG_WRITE(ah, AR_PHY_AIC_CTRL_3_B0, ar9003_aic_cal_start()
230 REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B0, ar9003_aic_cal_start()
237 REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B1, ar9003_aic_cal_start()
247 REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL, ar9003_aic_cal_start()
441 REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL, ar9003_aic_cal_done()
485 REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1, ar9003_aic_cal_continue()
550 REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1, ATH_AIC_SRAM_AUTO_INCREMENT); ar9003_aic_start_normal()
553 REG_WRITE(ah, AR_PHY_AIC_SRAM_DATA_B1, aic->aic_sram[i]); ar9003_aic_start_normal()
557 REG_WRITE(ah, 0xa6b0, 0x80); ar9003_aic_start_normal()
558 REG_WRITE(ah, 0xa6b4, 0x5b2df0); ar9003_aic_start_normal()
559 REG_WRITE(ah, 0xa6b8, 0x10762cc8); ar9003_aic_start_normal()
560 REG_WRITE(ah, 0xa6bc, 0x1219a4b); ar9003_aic_start_normal()
561 REG_WRITE(ah, 0xa6c0, 0x1e01); ar9003_aic_start_normal()
562 REG_WRITE(ah, 0xb6b4, 0xf0); ar9003_aic_start_normal()
563 REG_WRITE(ah, 0xb6c0, 0x1e01); ar9003_aic_start_normal()
564 REG_WRITE(ah, 0xb6b0, 0x81); ar9003_aic_start_normal()
565 REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX4, 0x40000000); ar9003_aic_start_normal()
|
| H A D | ar9002_hw.c | 219 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), ar9002_hw_configpcipowersave()
225 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); ar9002_hw_configpcipowersave()
226 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); ar9002_hw_configpcipowersave()
229 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); ar9002_hw_configpcipowersave()
230 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); ar9002_hw_configpcipowersave()
231 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); ar9002_hw_configpcipowersave()
237 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); ar9002_hw_configpcipowersave()
239 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); ar9002_hw_configpcipowersave()
240 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); ar9002_hw_configpcipowersave()
241 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); ar9002_hw_configpcipowersave()
244 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); ar9002_hw_configpcipowersave()
291 REG_WRITE(ah, AR_WA, val); ar9002_hw_configpcipowersave()
319 REG_WRITE(ah, AR_WA, val); ar9002_hw_configpcipowersave()
333 REG_WRITE(ah, AR_PHY(0x36), 0x00007058); ar9002_hw_get_radiorev()
335 REG_WRITE(ah, AR_PHY(0x20), 0x00010000); ar9002_hw_get_radiorev()
349 REG_WRITE(ah, AR_PHY(0), 0x00000007); ar9002_hw_rf_claim()
450 REG_WRITE(ah, reg, val|val_orig); ar9002_hw_load_ani_reg()
452 REG_WRITE(ah, reg, val); ar9002_hw_load_ani_reg()
|
| H A D | mac.c | 32 REG_WRITE(ah, AR_IMR_S0, ath9k_hw_set_txq_interrupts()
35 REG_WRITE(ah, AR_IMR_S1, ath9k_hw_set_txq_interrupts()
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); ath9k_hw_set_txq_interrupts()
54 REG_WRITE(ah, AR_QTXDP(q), txdp); ath9k_hw_puttxbuf()
61 REG_WRITE(ah, AR_Q_TXE, 1 << q); ath9k_hw_txstart()
123 REG_WRITE(ah, AR_TXCFG, ath9k_hw_updatetxtriglevel()
146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); ath9k_hw_abort_tx_dma()
166 REG_WRITE(ah, AR_Q_TXD, 0); ath9k_hw_abort_tx_dma()
177 REG_WRITE(ah, AR_Q_TXD, 1 << q); ath9k_hw_stop_dma_queue()
187 REG_WRITE(ah, AR_Q_TXD, 0); ath9k_hw_stop_dma_queue()
390 REG_WRITE(ah, AR_DLCL_IFS(q), ath9k_hw_resettxqueue()
395 REG_WRITE(ah, AR_DRETRY_LIMIT(q), ath9k_hw_resettxqueue()
400 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ); ath9k_hw_resettxqueue()
403 REG_WRITE(ah, AR_DMISC(q), ath9k_hw_resettxqueue()
406 REG_WRITE(ah, AR_DMISC(q), ath9k_hw_resettxqueue()
410 REG_WRITE(ah, AR_QCBRCFG(q), ath9k_hw_resettxqueue()
418 REG_WRITE(ah, AR_QRDYTIMECFG(q), ath9k_hw_resettxqueue()
423 REG_WRITE(ah, AR_DCHNTIME(q), ath9k_hw_resettxqueue()
463 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN) ath9k_hw_resettxqueue()
478 REG_WRITE(ah, AR_QRDYTIMECFG(q), ath9k_hw_resettxqueue()
505 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); ath9k_hw_resettxqueue()
670 REG_WRITE(ah, AR_RXDP, rxdp); ath9k_hw_putrxbuf()
700 REG_WRITE(ah, AR_MACMISC, ath9k_hw_stopdmarecv()
705 REG_WRITE(ah, AR_CR, AR_CR_RXD); ath9k_hw_stopdmarecv()
785 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); ath9k_hw_kill_interrupts()
788 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); ath9k_hw_kill_interrupts()
791 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); ath9k_hw_kill_interrupts()
833 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); ath9k_hw_enable_interrupts()
835 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask); ath9k_hw_enable_interrupts()
836 REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask); ath9k_hw_enable_interrupts()
838 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); ath9k_hw_enable_interrupts()
839 REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default); ath9k_hw_enable_interrupts()
927 REG_WRITE(ah, AR_IMR, mask); ath9k_hw_set_interrupts()
943 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); ath9k_hw_set_interrupts()
973 REG_WRITE(ah, AR_D_TXBLK_BASE, filter); ath9k_hw_set_tx_filter()
|
| H A D | ar9003_mci.c | 48 REG_WRITE(ah, address, bit_position); ar9003_mci_wait_for_interrupt()
58 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, ar9003_mci_wait_for_interrupt()
61 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_RX_MSG); ar9003_mci_wait_for_interrupt()
234 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); ar9003_mci_prep_interface()
235 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, ar9003_mci_prep_interface()
237 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, ar9003_mci_prep_interface()
272 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF); ar9003_mci_prep_interface()
273 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF); ar9003_mci_prep_interface()
274 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF); ar9003_mci_prep_interface()
275 REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF); ar9003_mci_prep_interface()
276 REG_WRITE(ah, AR_MCI_BT_PRI, 0X000000FF); ar9003_mci_prep_interface()
284 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, ar9003_mci_prep_interface()
286 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_BT_PRI); ar9003_mci_prep_interface()
312 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, ar9003_mci_prep_interface()
314 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, ar9003_mci_prep_interface()
318 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en); ar9003_mci_prep_interface()
336 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); ar9003_mci_disable_interrupt()
337 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); ar9003_mci_disable_interrupt()
342 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, AR_MCI_INTERRUPT_DEFAULT); ar9003_mci_enable_interrupt()
343 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, ar9003_mci_enable_interrupt()
389 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr); ar9003_mci_get_isr()
390 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr); ar9003_mci_get_isr()
456 REG_WRITE(ah, AR_OBS, 0x4b); ar9003_mci_observation_set_up()
740 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, ar9003_mci_end_reset()
778 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000); ar9003_mci_mute_bt()
779 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff); ar9003_mci_mute_bt()
780 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xffffffff); ar9003_mci_mute_bt()
781 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xffffffff); ar9003_mci_mute_bt()
782 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xffffffff); ar9003_mci_mute_bt()
867 REG_WRITE(ah, AR_BTCOEX_CTRL, regval); ar9003_mci_set_btcoex_ctrl_9565_1ANT()
886 REG_WRITE(ah, AR_BTCOEX_CTRL, regval); ar9003_mci_set_btcoex_ctrl_9565_2ANT()
903 REG_WRITE(ah, AR_BTCOEX_CTRL, regval); ar9003_mci_set_btcoex_ctrl_9462()
922 REG_WRITE(ah, AR_MCI_GPM_0, mci->gpm_addr); ar9003_mci_reset()
923 REG_WRITE(ah, AR_MCI_GPM_1, mci->gpm_len); ar9003_mci_reset()
924 REG_WRITE(ah, AR_MCI_SCHD_TABLE_0, mci->sched_addr); ar9003_mci_reset()
966 REG_WRITE(ah, AR_BTCOEX_MAX_TXPWR(i), 0x7f7f7f7f); ar9003_mci_reset()
976 REG_WRITE(ah, AR_MCI_COMMAND2, regval); ar9003_mci_reset()
981 REG_WRITE(ah, AR_MCI_COMMAND2, regval); ar9003_mci_reset()
992 REG_WRITE(ah, AR_MCI_COMMAND2, regval); ar9003_mci_reset()
995 REG_WRITE(ah, AR_MCI_COMMAND2, regval); ar9003_mci_reset()
1000 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, ar9003_mci_reset()
1035 REG_WRITE(ah, AR_BTCOEX_CTRL, 0); ar9003_mci_stop_bt()
1140 REG_WRITE(ah, AR_SELFGEN_MASK, 0x02); ar9003_mci_2g5g_switch()
1184 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); ar9003_mci_send_message()
1188 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, ar9003_mci_send_message()
1194 REG_WRITE(ah, (AR_MCI_TX_PAYLOAD0 + i * 4), ar9003_mci_send_message()
1198 REG_WRITE(ah, AR_MCI_COMMAND0, ar9003_mci_send_message()
1214 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en); ar9003_mci_send_message()
1274 REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00); ar9003_mci_cleanup()
1424 REG_WRITE(ah, AR_BTCOEX_CTRL2, (btcoex_ctrl2 | BIT(23))); ar9003_mci_set_power_awake()
1432 REG_WRITE(ah, AR_DIAG_SW, (diag_sw | BIT(27) | BIT(19) | BIT(18))); ar9003_mci_set_power_awake()
1436 REG_WRITE(ah, AR_BTCOEX_CTRL2, btcoex_ctrl2); ar9003_mci_set_power_awake()
1437 REG_WRITE(ah, AR_DIAG_SW, diag_sw); ar9003_mci_set_power_awake()
1479 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, ar9003_mci_get_next_gpm_offset()
|
| H A D | ar5008_phy.c | 73 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); ar5008_write_bank6()
218 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, ar5008_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, ar5008_hw_set_channel()
250 REG_WRITE(ah, AR_PHY(0x37), reg32); ar5008_hw_set_channel()
297 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); ar5008_hw_cmn_spur_mitigate()
298 REG_WRITE(ah, chan_mask_reg[i], chan_mask); ar5008_hw_cmn_spur_mitigate()
330 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); ar5008_hw_cmn_spur_mitigate()
331 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); ar5008_hw_cmn_spur_mitigate()
341 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); ar5008_hw_cmn_spur_mitigate()
342 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); ar5008_hw_cmn_spur_mitigate()
352 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); ar5008_hw_cmn_spur_mitigate()
353 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); ar5008_hw_cmn_spur_mitigate()
363 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); ar5008_hw_cmn_spur_mitigate()
364 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); ar5008_hw_cmn_spur_mitigate()
374 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); ar5008_hw_cmn_spur_mitigate()
375 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); ar5008_hw_cmn_spur_mitigate()
385 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); ar5008_hw_cmn_spur_mitigate()
386 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); ar5008_hw_cmn_spur_mitigate()
396 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); ar5008_hw_cmn_spur_mitigate()
397 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); ar5008_hw_cmn_spur_mitigate()
407 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); ar5008_hw_cmn_spur_mitigate()
408 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); ar5008_hw_cmn_spur_mitigate()
455 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); ar5008_hw_spur_mitigate()
462 REG_WRITE(ah, AR_PHY_SPUR_REG, new); ar5008_hw_spur_mitigate()
473 REG_WRITE(ah, AR_PHY_TIMING11, new); ar5008_hw_spur_mitigate()
572 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); ar5008_hw_init_bb()
591 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); ar5008_hw_init_chain_masks()
592 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); ar5008_hw_init_chain_masks()
599 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); ar5008_hw_init_chain_masks()
600 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); ar5008_hw_init_chain_masks()
607 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); ar5008_hw_init_chain_masks()
616 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, ar5008_hw_init_chain_masks()
651 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); ar5008_hw_override_ini()
660 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); ar5008_hw_override_ini()
669 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); ar5008_hw_override_ini()
694 REG_WRITE(ah, AR_PHY_TURBO, phymode); ar5008_hw_set_channel_regs()
696 /* This function do only REG_WRITE, so ar5008_hw_set_channel_regs()
700 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); ar5008_hw_set_channel_regs()
701 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); ar5008_hw_set_channel_regs()
726 REG_WRITE(ah, AR_PHY(0), 0x00000007); ar5008_hw_process_ini()
729 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); ar5008_hw_process_ini()
734 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); ar5008_hw_process_ini()
745 REG_WRITE(ah, reg, val); ar5008_hw_process_ini()
777 REG_WRITE(ah, reg, val); ar5008_hw_process_ini()
830 REG_WRITE(ah, AR_PHY_MODE, rfMode); ar5008_hw_set_rfmode()
835 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); ar5008_hw_mark_phy_inactive()
874 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); ar5008_hw_rfbus_req()
885 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); ar5008_hw_rfbus_done()
893 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); ar5008_restore_chainmask()
894 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); ar5008_restore_chainmask()
1241 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); ar5008_hw_set_radar_params()
1242 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); ar5008_hw_set_radar_params()
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| H A D | ar9003_rtt.c | 40 REG_WRITE(ah, AR_PHY_RTT_CTRL, 1); ar9003_hw_rtt_enable()
45 REG_WRITE(ah, AR_PHY_RTT_CTRL, 0); ar9003_hw_rtt_disable()
78 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val); ar9003_hw_rtt_load_hist_entry()
83 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); ar9003_hw_rtt_load_hist_entry()
87 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); ar9003_hw_rtt_load_hist_entry()
96 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); ar9003_hw_rtt_load_hist_entry()
150 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); ar9003_hw_rtt_fill_hist_entry()
154 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); ar9003_hw_rtt_fill_hist_entry()
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| H A D | ar9002_phy.c | 101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, ar9002_hw_set_channel()
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, ar9002_hw_set_channel()
152 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); ar9002_hw_set_channel()
232 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); ar9002_hw_spur_mitigate()
239 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); ar9002_hw_spur_mitigate()
269 REG_WRITE(ah, AR_PHY_TIMING11, newVal); ar9002_hw_spur_mitigate()
272 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); ar9002_hw_spur_mitigate()
410 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); ar9002_hw_antdiv_comb_conf_set()
429 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); ar9002_hw_set_bt_ant_diversity()
431 REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM); ar9002_hw_set_bt_ant_diversity()
444 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); ar9002_hw_set_bt_ant_diversity()
450 REG_WRITE(ah, AR_PHY_SWITCH_COM, 0); ar9002_hw_set_bt_ant_diversity()
466 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); ar9002_hw_set_bt_ant_diversity()
471 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); ar9002_hw_set_bt_ant_diversity()
545 REG_WRITE(ah, AR_CR, AR_CR_RXD); ar9002_hw_tx99_start()
546 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); ar9002_hw_tx99_start()
547 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); ar9002_hw_tx99_start()
548 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); ar9002_hw_tx99_start()
549 REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum); ar9002_hw_tx99_start()
550 REG_WRITE(ah, AR_TIME_OUT, 0x00000400); ar9002_hw_tx99_start()
551 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); ar9002_hw_tx99_start()
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| H A D | btcoex.c | 271 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode); ath9k_hw_btcoex_enable_3wire()
272 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); ath9k_hw_btcoex_enable_3wire()
276 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, btcoex->wlan_weight[0]); ath9k_hw_btcoex_enable_3wire()
277 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, btcoex->wlan_weight[1]); ath9k_hw_btcoex_enable_3wire()
279 REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), ath9k_hw_btcoex_enable_3wire()
282 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex->bt_coex_weights); ath9k_hw_btcoex_enable_3wire()
289 REG_WRITE(ah, 0x50040, val); ath9k_hw_btcoex_enable_3wire()
305 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i), ath9k_hw_btcoex_enable_mci()
320 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i), ath9k_hw_btcoex_disable_mci()
371 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); ath9k_hw_btcoex_disable()
372 REG_WRITE(ah, AR_BT_COEX_MODE2, 0); ath9k_hw_btcoex_disable()
375 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0); ath9k_hw_btcoex_disable()
376 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0); ath9k_hw_btcoex_disable()
378 REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), 0); ath9k_hw_btcoex_disable()
380 REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0); ath9k_hw_btcoex_disable()
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| H A D | hw.c | 118 REG_WRITE(ah, INI_RA(array, r, 0), ath9k_hw_write_array()
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); ath9k_hw_disablepcie()
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); ath9k_hw_disablepcie()
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); ath9k_hw_disablepcie()
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); ath9k_hw_disablepcie()
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); ath9k_hw_disablepcie()
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); ath9k_hw_disablepcie()
324 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); ath9k_hw_disablepcie()
325 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); ath9k_hw_disablepcie()
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); ath9k_hw_disablepcie()
328 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); ath9k_hw_disablepcie()
355 REG_WRITE(ah, addr, wrData); ath9k_hw_chip_test()
366 REG_WRITE(ah, addr, wrData); ath9k_hw_chip_test()
375 REG_WRITE(ah, regAddr[i], regHold[i]); ath9k_hw_chip_test()
605 REG_WRITE(ah, AR_WA, ah->WARegVal); __ath9k_hw_init()
707 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); ath9k_hw_init_qos()
708 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); ath9k_hw_init_qos()
710 REG_WRITE(ah, AR_QOS_NO_ACK, ath9k_hw_init_qos()
715 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); ath9k_hw_init_qos()
716 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); ath9k_hw_init_qos()
717 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); ath9k_hw_init_qos()
718 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); ath9k_hw_init_qos()
719 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); ath9k_hw_init_qos()
800 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); ath9k_hw_init_pll()
806 REG_WRITE(ah, AR_RTC_PLL_CONTROL, ath9k_hw_init_pll()
811 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); ath9k_hw_init_pll()
824 REG_WRITE(ah, AR_RTC_PLL_CONTROL, ath9k_hw_init_pll()
860 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); ath9k_hw_init_pll()
863 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | ath9k_hw_init_pll()
889 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); ath9k_hw_init_pll()
892 REG_WRITE(ah, AR_PHY_PLL_MODE, ath9k_hw_init_pll()
895 REG_WRITE(ah, AR_PHY_PLL_MODE, ath9k_hw_init_pll()
903 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); ath9k_hw_init_pll()
912 REG_WRITE(ah, 0x50040, 0x304); ath9k_hw_init_pll()
917 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); ath9k_hw_init_pll()
955 REG_WRITE(ah, AR_IMR, imr_reg); ath9k_hw_init_interrupt_masks()
957 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); ath9k_hw_init_interrupt_masks()
960 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); ath9k_hw_init_interrupt_masks()
961 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); ath9k_hw_init_interrupt_masks()
962 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); ath9k_hw_init_interrupt_masks()
968 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); ath9k_hw_init_interrupt_masks()
969 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); ath9k_hw_init_interrupt_masks()
970 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); ath9k_hw_init_interrupt_masks()
971 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); ath9k_hw_init_interrupt_masks()
979 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); ath9k_hw_set_sifs_time()
986 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); ath9k_hw_setslottime()
1115 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); ath9k_hw_init_global_settings()
1194 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); ath9k_hw_set_dma()
1222 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); ath9k_hw_set_dma()
1308 REG_WRITE(ah, AR_RTC_RESET, 1); ath9k_hw_ar9330_reset_war()
1328 REG_WRITE(ah, AR_WA, ah->WARegVal); ath9k_hw_set_reset()
1332 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | ath9k_hw_set_reset()
1348 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); ath9k_hw_set_reset()
1353 REG_WRITE(ah, AR_RC, val); ath9k_hw_set_reset()
1356 REG_WRITE(ah, AR_RC, AR_RC_AHB); ath9k_hw_set_reset()
1371 REG_WRITE(ah, AR_RTC_RC, rst_flags); ath9k_hw_set_reset()
1382 REG_WRITE(ah, AR_RTC_RC, 0); ath9k_hw_set_reset()
1389 REG_WRITE(ah, AR_RC, 0); ath9k_hw_set_reset()
1402 REG_WRITE(ah, AR_WA, ah->WARegVal); ath9k_hw_set_reset_power_on()
1406 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | ath9k_hw_set_reset_power_on()
1410 REG_WRITE(ah, AR_RC, AR_RC_AHB); ath9k_hw_set_reset_power_on()
1412 REG_WRITE(ah, AR_RTC_RESET, 0); ath9k_hw_set_reset_power_on()
1419 REG_WRITE(ah, AR_RC, 0); ath9k_hw_set_reset_power_on()
1421 REG_WRITE(ah, AR_RTC_RESET, 1); ath9k_hw_set_reset_power_on()
1440 REG_WRITE(ah, AR_WA, ah->WARegVal); ath9k_hw_set_reset_reg()
1444 REG_WRITE(ah, AR_RTC_FORCE_WAKE, ath9k_hw_set_reset_reg()
1588 REG_WRITE(ah, AR_NAV, 0); ath9k_hw_check_nav()
1668 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); ath9k_hw_reset_opmode()
1670 REG_WRITE(ah, AR_ISR, ~0); ath9k_hw_reset_opmode()
1671 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); ath9k_hw_reset_opmode()
1685 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); ath9k_hw_init_queues()
1709 REG_WRITE(ah, AR_CFG, mask); ath9k_hw_init_desc()
1717 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); ath9k_hw_init_desc()
1719 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); ath9k_hw_init_desc()
1727 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); ath9k_hw_init_desc()
1881 REG_WRITE(ah, ath9k_hw_reset()
1895 REG_WRITE(ah, ath9k_hw_reset()
1969 REG_WRITE(ah, AR_OBS, 8); ath9k_hw_reset()
1998 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); ath9k_hw_reset()
2055 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); ath9k_set_power_sleep()
2069 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); ath9k_set_power_sleep()
2079 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); ath9k_set_power_sleep()
2095 REG_WRITE(ah, AR_RTC_FORCE_WAKE, ath9k_set_power_network_sleep()
2123 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); ath9k_set_power_network_sleep()
2133 REG_WRITE(ah, AR_WA, ah->WARegVal); ath9k_hw_set_power_awake()
2245 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); ath9k_hw_beaconinit()
2246 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - ath9k_hw_beaconinit()
2248 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - ath9k_hw_beaconinit()
2260 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); ath9k_hw_beaconinit()
2261 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); ath9k_hw_beaconinit()
2262 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); ath9k_hw_beaconinit()
2279 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); ath9k_hw_set_sta_beacon_timers()
2280 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); ath9k_hw_set_sta_beacon_timers()
2281 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); ath9k_hw_set_sta_beacon_timers()
2309 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); ath9k_hw_set_sta_beacon_timers()
2310 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); ath9k_hw_set_sta_beacon_timers()
2312 REG_WRITE(ah, AR_SLEEP1, ath9k_hw_set_sta_beacon_timers()
2321 REG_WRITE(ah, AR_SLEEP2, ath9k_hw_set_sta_beacon_timers()
2324 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); ath9k_hw_set_sta_beacon_timers()
2325 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); ath9k_hw_set_sta_beacon_timers()
2334 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); ath9k_hw_set_sta_beacon_timers()
2629 REG_WRITE(ah, addr, tmp); ath9k_hw_gpio_cfg_output_mux()
2736 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); ath9k_hw_setantenna()
2767 REG_WRITE(ah, AR_RX_FILTER, bits); ath9k_hw_setrxfilter()
2774 REG_WRITE(ah, AR_PHY_ERR, phybits); ath9k_hw_setrxfilter()
2874 REG_WRITE(ah, AR_MCAST_FIL0, filter0); ath9k_hw_setmcastfilter()
2875 REG_WRITE(ah, AR_MCAST_FIL1, filter1); ath9k_hw_setmcastfilter()
2883 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); ath9k_hw_write_associd()
2884 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | ath9k_hw_write_associd()
2913 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); ath9k_hw_settsf64()
2914 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); ath9k_hw_settsf64()
2925 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); ath9k_hw_reset_tsf()
2947 REG_WRITE(ah, AR_2040_MODE, macmode); ath9k_hw_set11nmac2040()
3047 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, ath9k_hw_gen_timer_start()
3049 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, ath9k_hw_gen_timer_start()
|
| H A D | ar9003_phy.c | 223 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); ar9003_hw_set_channel()
232 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); ar9003_hw_set_channel()
238 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); ar9003_hw_set_channel()
665 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); ar9003_hw_set_channel_regs()
671 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); ar9003_hw_set_channel_regs()
673 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); ar9003_hw_set_channel_regs()
689 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); ar9003_hw_init_bb()
699 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); ar9003_hw_set_chain_masks()
700 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); ar9003_hw_set_chain_masks()
705 REG_WRITE(ah, AR_SELFGEN_MASK, tx); ar9003_hw_set_chain_masks()
733 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); ar9003_hw_override_ini()
736 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, ar9003_hw_override_ini()
755 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); ar9003_hw_override_ini()
756 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); ar9003_hw_override_ini()
757 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); ar9003_hw_override_ini()
759 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); ar9003_hw_override_ini()
760 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); ar9003_hw_override_ini()
761 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); ar9003_hw_override_ini()
789 REG_WRITE(ah, reg, val); ar9003_hw_prog_ini()
1011 REG_WRITE(ah, AR_PHY_MODE, rfMode); ar9003_hw_set_rfmode()
1016 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); ar9003_hw_mark_phy_inactive()
1068 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); ar9003_hw_rfbus_req()
1083 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); ar9003_hw_rfbus_done()
1492 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); ar9003_hw_set_radar_params()
1493 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); ar9003_hw_set_radar_params()
1573 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_antdiv_comb_conf_set()
1607 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_set_bt_ant_diversity()
1619 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_set_bt_ant_diversity()
1630 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); ar9003_hw_set_bt_ant_diversity()
1646 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_set_bt_ant_diversity()
1681 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_set_bt_ant_diversity()
1821 REG_WRITE(ah, AR_CR, AR_CR_RXD); ar9003_hw_tx99_start()
1822 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); ar9003_hw_tx99_start()
1823 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ ar9003_hw_tx99_start()
1824 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); ar9003_hw_tx99_start()
1825 REG_WRITE(ah, AR_TIME_OUT, 0x00000400); ar9003_hw_tx99_start()
1826 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); ar9003_hw_tx99_start()
1849 REG_WRITE(ah, 0xa458, 0); ar9003_hw_tx99_set_txpower()
1851 REG_WRITE(ah, 0xa3c0, ar9003_hw_tx99_set_txpower()
1856 REG_WRITE(ah, 0xa3c4, ar9003_hw_tx99_set_txpower()
1861 REG_WRITE(ah, 0xa3c8, ar9003_hw_tx99_set_txpower()
1865 REG_WRITE(ah, 0xa3cc, ar9003_hw_tx99_set_txpower()
1870 REG_WRITE(ah, 0xa3d0, ar9003_hw_tx99_set_txpower()
1875 REG_WRITE(ah, 0xa3d4, ar9003_hw_tx99_set_txpower()
1880 REG_WRITE(ah, 0xa3e4, ar9003_hw_tx99_set_txpower()
1885 REG_WRITE(ah, 0xa3e8, ar9003_hw_tx99_set_txpower()
1890 REG_WRITE(ah, 0xa3d8, ar9003_hw_tx99_set_txpower()
1895 REG_WRITE(ah, 0xa3dc, ar9003_hw_tx99_set_txpower()
1900 REG_WRITE(ah, 0xa3ec, ar9003_hw_tx99_set_txpower()
2089 REG_WRITE(ah, AR_PHY_RADAR_0, val); ar9003_hw_bb_watchdog_check()
2094 REG_WRITE(ah, AR_PHY_RADAR_0, val); ar9003_hw_bb_watchdog_check()
2125 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, ar9003_hw_bb_watchdog_config()
2131 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, ar9003_hw_bb_watchdog_config()
2142 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, ar9003_hw_bb_watchdog_config()
2167 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, ar9003_hw_bb_watchdog_config()
2188 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, ar9003_hw_bb_watchdog_read()
2247 REG_WRITE(ah, AR_PHY_RESTART, val); ar9003_hw_disable_phy_restart()
|
| H A D | ar9002_calib.c | 60 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); ar9002_hw_setup_calibration()
65 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); ar9002_hw_setup_calibration()
69 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); ar9002_hw_setup_calibration()
302 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); ar9002_hw_adc_gaincal_calibrate()
309 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), ar9002_hw_adc_gaincal_calibrate()
357 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); ar9002_hw_adc_dccal_calibrate()
363 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), ar9002_hw_adc_dccal_calibrate()
485 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); ar9271_hw_pa_cal()
493 REG_WRITE(ah, AR9285_AN_RF2G6, regVal); ar9271_hw_pa_cal()
500 REG_WRITE(ah, AR9285_AN_RF2G6, regVal); ar9271_hw_pa_cal()
527 REG_WRITE(ah, regList[i][0], regList[i][1]); ar9271_hw_pa_cal()
560 REG_WRITE(ah, 0x7834, regVal); ar9285_hw_pa_cal()
563 REG_WRITE(ah, 0x9808, regVal); ar9285_hw_pa_cal()
580 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); ar9285_hw_pa_cal()
588 REG_WRITE(ah, 0x7834, regVal); ar9285_hw_pa_cal()
594 REG_WRITE(ah, 0x7834, regVal); ar9285_hw_pa_cal()
625 REG_WRITE(ah, 0x7834, regVal); ar9285_hw_pa_cal()
628 REG_WRITE(ah, 0x9808, regVal); ar9285_hw_pa_cal()
631 REG_WRITE(ah, regList[i][0], regList[i][1]); ar9285_hw_pa_cal()
799 REG_WRITE(ah, AR9285_RF2G5, ar9285_hw_clc()
803 REG_WRITE(ah, AR9285_RF2G5, ar9285_hw_clc()
808 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org); ar9285_hw_clc()
833 REG_WRITE(ah, AR_PHY_AGC_CONTROL, ar9002_hw_init_cal()
|
| H A D | eeprom_9287.c | 378 REG_WRITE(ah, 0xa270, tmpVal); ar9287_eeprom_olpc_set_pdadcs()
385 REG_WRITE(ah, 0xb270, tmpVal); ar9287_eeprom_olpc_set_pdadcs()
394 REG_WRITE(ah, 0xa398, tmpVal); ar9287_eeprom_olpc_set_pdadcs()
404 REG_WRITE(ah, 0xb398, tmpVal); ar9287_eeprom_olpc_set_pdadcs()
510 REG_WRITE(ah, ath9k_hw_set_ar9287_power_cal_table()
538 REG_WRITE(ah, regOffset, reg32); ath9k_hw_set_ar9287_power_cal_table()
807 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, ath9k_hw_ar9287_set_txpower()
813 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, ath9k_hw_ar9287_set_txpower()
821 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, ath9k_hw_ar9287_set_txpower()
826 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, ath9k_hw_ar9287_set_txpower()
834 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, ath9k_hw_ar9287_set_txpower()
840 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, ath9k_hw_ar9287_set_txpower()
849 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, ath9k_hw_ar9287_set_txpower()
855 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, ath9k_hw_ar9287_set_txpower()
861 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, ath9k_hw_ar9287_set_txpower()
871 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, ath9k_hw_ar9287_set_txpower()
883 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, ath9k_hw_ar9287_set_txpower()
897 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, ath9k_hw_ar9287_set_txpower()
901 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER); ath9k_hw_ar9287_set_txpower()
918 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); ath9k_hw_ar9287_set_board_values()
923 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, ath9k_hw_ar9287_set_board_values()
926 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, ath9k_hw_ar9287_set_board_values()
962 REG_WRITE(ah, AR_PHY_RF_CTL4, ath9k_hw_ar9287_set_board_values()
|
| H A D | ar9003_mac.c | 23 REG_WRITE(hw, AR_CR, 0); ar9003_hw_rx_enable()
234 REG_WRITE(ah, AR_ISR_S2, isr2); ar9003_hw_get_isr()
269 REG_WRITE(ah, AR_ISR_S0, s0); ar9003_hw_get_isr()
271 REG_WRITE(ah, AR_ISR_S1, s1); ar9003_hw_get_isr()
296 REG_WRITE(ah, AR_ISR_S5, s5); ar9003_hw_get_isr()
305 REG_WRITE(ah, AR_ISR, isr); ar9003_hw_get_isr()
338 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); ar9003_hw_get_isr()
339 REG_WRITE(ah, AR_RC, 0); ar9003_hw_get_isr()
347 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); ar9003_hw_get_isr()
466 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK); ath9k_hw_set_rx_bufsize()
474 REG_WRITE(ah, AR_HP_RXDP, rxdp); ath9k_hw_addrxbuf_edma()
476 REG_WRITE(ah, AR_LP_RXDP, rxdp); ath9k_hw_addrxbuf_edma()
600 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start); ath9k_hw_reset_txstatus_ring()
601 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end); ath9k_hw_reset_txstatus_ring()
|
| H A D | ani.c | 139 REG_WRITE(ah, AR_PHY_ERR_1, 0); ath9k_ani_restart()
140 REG_WRITE(ah, AR_PHY_ERR_2, 0); ath9k_ani_restart()
141 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); ath9k_ani_restart()
142 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); ath9k_ani_restart()
469 REG_WRITE(ah, AR_FILT_OFDM, 0); ath9k_enable_mib_counters()
470 REG_WRITE(ah, AR_FILT_CCK, 0); ath9k_enable_mib_counters()
471 REG_WRITE(ah, AR_MIBC, ath9k_enable_mib_counters()
474 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); ath9k_enable_mib_counters()
475 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); ath9k_enable_mib_counters()
487 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); ath9k_hw_disable_mib_counters()
489 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); ath9k_hw_disable_mib_counters()
490 REG_WRITE(ah, AR_FILT_OFDM, 0); ath9k_hw_disable_mib_counters()
491 REG_WRITE(ah, AR_FILT_CCK, 0); ath9k_hw_disable_mib_counters()
|
| H A D | ar9002_mac.c | 24 REG_WRITE(ah, AR_CR, AR_CR_RXE); ar9002_hw_rx_enable()
82 REG_WRITE(ah, AR_ISR_S2, isr2); ar9002_hw_get_isr()
113 REG_WRITE(ah, AR_ISR_S0, s0_s); ar9002_hw_get_isr()
115 REG_WRITE(ah, AR_ISR_S1, s1_s); ar9002_hw_get_isr()
160 REG_WRITE(ah, AR_ISR_S5, s5_s); ar9002_hw_get_isr()
166 REG_WRITE(ah, AR_ISR, isr); ar9002_hw_get_isr()
195 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); ar9002_hw_get_isr()
196 REG_WRITE(ah, AR_RC, 0); ar9002_hw_get_isr()
204 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); ar9002_hw_get_isr()
|
| H A D | ar9003_calib.c | 53 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); ar9003_hw_setup_calibration()
354 REG_WRITE(ah, AR_PHY_AGC_CONTROL, ar9003_hw_dynamic_osdac_selection()
391 REG_WRITE(ah, AR_PHY_AGC_CONTROL, ar9003_hw_dynamic_osdac_selection()
408 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, ar9003_hw_dynamic_osdac_selection()
410 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3, ar9003_hw_dynamic_osdac_selection()
412 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3, ar9003_hw_dynamic_osdac_selection()
430 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, ar9003_hw_dynamic_osdac_selection()
432 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3, ar9003_hw_dynamic_osdac_selection()
434 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3, ar9003_hw_dynamic_osdac_selection()
452 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, ar9003_hw_dynamic_osdac_selection()
454 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3, ar9003_hw_dynamic_osdac_selection()
456 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3, ar9003_hw_dynamic_osdac_selection()
484 REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, val); ar9003_hw_dynamic_osdac_selection()
505 REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, val); ar9003_hw_dynamic_osdac_selection()
526 REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, val); ar9003_hw_dynamic_osdac_selection()
1368 REG_WRITE(ah, CL_TAB_ENTRY(cl_idx[i]), ar9003_hw_cl_cal_post_proc()
1423 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl); ar9003_hw_init_cal_pcoem()
1471 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); ar9003_hw_init_cal_pcoem()
1473 REG_WRITE(ah, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY); ar9003_hw_init_cal_pcoem()
1474 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); ar9003_hw_init_cal_pcoem()
1479 REG_WRITE(ah, AR_PHY_AGC_CONTROL, ar9003_hw_init_cal_pcoem()
1492 REG_WRITE(ah, AR_PHY_RX_DELAY, rx_delay); ar9003_hw_init_cal_pcoem()
1501 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl); ar9003_hw_init_cal_pcoem()
1566 REG_WRITE(ah, AR_PHY_AGC_CONTROL, do_ar9003_agc_cal()
1632 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); ar9003_hw_init_cal_soc()
1634 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); ar9003_hw_init_cal_soc()
|
| H A D | eeprom_def.c | 525 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff); ath9k_hw_def_set_board_values()
538 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, ath9k_hw_def_set_board_values()
541 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, ath9k_hw_def_set_board_values()
613 REG_WRITE(ah, AR_PHY_RF_CTL4, ath9k_hw_def_set_board_values()
919 REG_WRITE(ah, ath9k_hw_set_def_power_cal_table()
926 REG_WRITE(ah, ath9k_hw_set_def_power_cal_table()
942 REG_WRITE(ah, regOffset, reg32); ath9k_hw_set_def_power_cal_table()
1242 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, ath9k_hw_def_set_txpower()
1247 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, ath9k_hw_def_set_txpower()
1256 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, ath9k_hw_def_set_txpower()
1261 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, ath9k_hw_def_set_txpower()
1267 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, ath9k_hw_def_set_txpower()
1272 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, ath9k_hw_def_set_txpower()
1280 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, ath9k_hw_def_set_txpower()
1285 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, ath9k_hw_def_set_txpower()
1292 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, ath9k_hw_def_set_txpower()
1301 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, ath9k_hw_def_set_txpower()
1311 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, ath9k_hw_def_set_txpower()
1317 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, ath9k_hw_def_set_txpower()
1325 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, ath9k_hw_def_set_txpower()
1336 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, ath9k_hw_def_set_txpower()
1340 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER); ath9k_hw_def_set_txpower()
|
| H A D | eeprom_4k.c | 416 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, ath9k_hw_set_4k_power_cal_table()
431 REG_WRITE(ah, regOffset, reg32); ath9k_hw_set_4k_power_cal_table()
691 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, ath9k_hw_4k_set_txpower()
696 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, ath9k_hw_4k_set_txpower()
703 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, ath9k_hw_4k_set_txpower()
708 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, ath9k_hw_4k_set_txpower()
715 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, ath9k_hw_4k_set_txpower()
720 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, ath9k_hw_4k_set_txpower()
728 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, ath9k_hw_4k_set_txpower()
737 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, ath9k_hw_4k_set_txpower()
746 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, ath9k_hw_4k_set_txpower()
760 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, ath9k_hw_4k_set_txpower()
764 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER); ath9k_hw_4k_set_txpower()
844 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); ath9k_hw_4k_set_board_values()
869 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); ath9k_hw_4k_set_board_values()
876 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); ath9k_hw_4k_set_board_values()
894 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); ath9k_hw_4k_set_board_values()
|
| H A D | ar9003_eeprom.c | 3693 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_ant_ctrl_apply()
3704 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); ar9003_hw_ant_ctrl_apply()
3721 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); ar9003_hw_ant_ctrl_apply()
3745 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg); ar9003_hw_drive_strength_apply()
3758 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg); ar9003_hw_drive_strength_apply()
3765 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg); ar9003_hw_drive_strength_apply()
3876 REG_WRITE(ah, pmu_reg, pmu_set); is_pmu_set()
3894 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); ar9003_hw_internal_regulator_apply()
3917 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set); ar9003_hw_internal_regulator_apply()
3923 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); ar9003_hw_internal_regulator_apply()
3929 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); ar9003_hw_internal_regulator_apply()
3935 REG_WRITE(ah, AR_PHY_PMU1, reg_val); ar9003_hw_internal_regulator_apply()
3938 REG_WRITE(ah, AR_PHY_PMU2, 0x10200000); ar9003_hw_internal_regulator_apply()
3942 REG_WRITE(ah, AR_RTC_REG_CONTROL1, ar9003_hw_internal_regulator_apply()
3945 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val); ar9003_hw_internal_regulator_apply()
3947 REG_WRITE(ah, AR_RTC_REG_CONTROL1, ar9003_hw_internal_regulator_apply()
3972 REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val); ar9003_hw_internal_regulator_apply()
4401 REG_WRITE(ah, AR_TPC, val); ar9003_hw_selfgen_tpc_txpower()
4409 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0); ar9003_hw_tx_power_regwrite()
4414 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0), ar9003_hw_tx_power_regwrite()
4421 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1), ar9003_hw_tx_power_regwrite()
4430 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2), ar9003_hw_tx_power_regwrite()
4437 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3), ar9003_hw_tx_power_regwrite()
4447 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8), ar9003_hw_tx_power_regwrite()
4457 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4), ar9003_hw_tx_power_regwrite()
4465 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5), ar9003_hw_tx_power_regwrite()
4473 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9), ar9003_hw_tx_power_regwrite()
4483 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10), ar9003_hw_tx_power_regwrite()
4495 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6), ar9003_hw_tx_power_regwrite()
4503 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7), ar9003_hw_tx_power_regwrite()
4511 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11), ar9003_hw_tx_power_regwrite()
5437 REG_WRITE(ah, AR_PHY_PWRTX_MAX, ath9k_hw_ar9300_set_txpower()
5442 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, ath9k_hw_ar9300_set_txpower()
5445 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, ath9k_hw_ar9300_set_txpower()
5449 REG_WRITE(ah, AR_PHY_PWRTX_MAX, 0); ath9k_hw_ar9300_set_txpower()
|
| H A D | eeprom.c | 21 REG_WRITE(ah, reg, val); ath9k_hw_analog_shift_regwrite()
|
| H A D | ar9003_hw.c | 1025 REG_WRITE(ah, 0x570c, val); ar9003_hw_configpcipowersave()
1033 REG_WRITE(ah, AR_WA, ah->WARegVal); ar9003_hw_configpcipowersave()
1044 REG_WRITE(ah, ar9003_hw_configpcipowersave()
|
| H A D | ar9003_paprd.c | 769 REG_WRITE(ah, reg, paprd_table_val[i]); ar9003_paprd_populate_single_table()
|
| H A D | htc_drv_init.c | 503 REG_WRITE(ah, reg_offset, val); ath9k_reg_rmw()
|
| H A D | hw.h | 79 #define REG_WRITE(_ah, _reg, _val) \ macro
|
| /linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/ |
| H A D | iop_version_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_sap_in_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_sap_out_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_sw_spu_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_sw_cfg_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_sw_cpu_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_sw_mpu_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| /linux-4.4.14/drivers/net/dsa/ |
| H A D | mv88e6131.c | 49 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, mv88e6131_setup_global()
53 REG_WRITE(REG_GLOBAL, GLOBAL_CORE_TAG_TYPE, 0x8100); mv88e6131_setup_global()
62 REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg); mv88e6131_setup_global()
69 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, mv88e6131_setup_global()
73 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, mv88e6131_setup_global()
80 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, mv88e6131_setup_global()
|
| H A D | mv88e6060.c | 51 #define REG_WRITE(addr, reg, val) \ macro
91 REG_WRITE(REG_PORT(i), PORT_CONTROL, mv88e6060_switch_reset()
99 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, mv88e6060_switch_reset()
125 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536); mv88e6060_setup_global()
131 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, mv88e6060_setup_global()
147 REG_WRITE(addr, PORT_CONTROL, mv88e6060_setup_port()
159 REG_WRITE(addr, PORT_VLAN_MAP, mv88e6060_setup_port()
170 REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p)); mv88e6060_setup_port()
202 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]); mv88e6060_set_addr()
203 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); mv88e6060_set_addr()
204 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); mv88e6060_set_addr()
|
| H A D | mv88e6123_61_65.c | 52 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, 0x0000); mv88e6123_61_65_setup_global()
61 REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg); mv88e6123_61_65_setup_global()
66 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, ds->index & 0x1f); mv88e6123_61_65_setup_global()
|
| H A D | mv88e6171.c | 46 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, mv88e6171_setup_global()
57 REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg); mv88e6171_setup_global()
62 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, ds->index & 0x1f); mv88e6171_setup_global()
|
| H A D | mv88e6xxx.c | 188 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); mv88e6xxx_set_addr_direct()
189 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); mv88e6xxx_set_addr_direct()
190 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); mv88e6xxx_set_addr_direct()
204 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC, mv88e6xxx_set_addr_indirect()
242 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, mv88e6xxx_ppu_disable()
263 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE); mv88e6xxx_ppu_enable()
2212 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, mv88e6xxx_setup_global()
2216 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); mv88e6xxx_setup_global()
2217 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); mv88e6xxx_setup_global()
2218 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); mv88e6xxx_setup_global()
2219 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); mv88e6xxx_setup_global()
2220 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); mv88e6xxx_setup_global()
2221 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); mv88e6xxx_setup_global()
2222 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); mv88e6xxx_setup_global()
2223 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); mv88e6xxx_setup_global()
2226 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); mv88e6xxx_setup_global()
2231 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff); mv88e6xxx_setup_global()
2238 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, mv88e6xxx_setup_global()
2250 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, mv88e6xxx_setup_global()
2258 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK, mv88e6xxx_setup_global()
2264 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, mv88e6xxx_setup_global()
2274 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff); mv88e6xxx_setup_global()
2279 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000); mv88e6xxx_setup_global()
2283 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, mv88e6xxx_setup_global()
2296 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP, mv88e6xxx_setup_global()
2301 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL); mv88e6xxx_setup_global()
2333 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc); mv88e6xxx_switch_reset()
2344 REG_WRITE(REG_GLOBAL, 0x04, 0xc000); mv88e6xxx_switch_reset()
2346 REG_WRITE(REG_GLOBAL, 0x04, 0xc400); mv88e6xxx_switch_reset()
|
| H A D | mv88e6352.c | 58 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, mv88e6352_setup_global()
68 REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg); mv88e6352_setup_global()
73 REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); mv88e6352_setup_global()
|
| H A D | mv88e6xxx.h | 515 #define REG_WRITE(addr, reg, val) \ macro
|
| /linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/iop/ |
| H A D | iop_version_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_fifo_in_extra_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_fifo_out_extra_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_scrc_in_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_scrc_out_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_trigger_grp_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_crc_par_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_fifo_in_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_mpu_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_sap_in_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_timer_grp_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_dmc_in_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_dmc_out_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_fifo_out_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_sap_out_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_spu_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_sw_spu_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_sw_cfg_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_sw_cpu_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | iop_sw_mpu_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| /linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ |
| H A D | strmux_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | clkgen_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | l2cache_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | marb_bar_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
306 REG_WRITE( reg_##scope##_##reg, \
319 REG_WRITE( reg_##scope##_##reg, \
331 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
342 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | marb_foo_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
432 REG_WRITE( reg_##scope##_##reg, \
445 REG_WRITE( reg_##scope##_##reg, \
457 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
468 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | ddr2_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | intr_vect_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | pinmux_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | pio_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | timer_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | gio_defs.h | 22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| /linux-4.4.14/arch/cris/include/arch-v32/mach-fs/mach/hwregs/ |
| H A D | config_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | strmux_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | bif_slave_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | intr_vect_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | marb_bp_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | marb_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
284 REG_WRITE( reg_##scope##_##reg, \
297 REG_WRITE( reg_##scope##_##reg, \
309 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
320 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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| H A D | bif_core_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | gio_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | pinmux_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | timer_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| H A D | bif_dma_defs.h | 25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
|
| /linux-4.4.14/drivers/net/wireless/cw1200/ |
| H A D | fwio.c | 83 #define REG_WRITE(reg, val) \ cw1200_load_firmware_cw1200() macro
135 REG_WRITE(ST90TDS_SRAM_BASE_ADDR_REG_ID, 0xFFF20000); cw1200_load_firmware_cw1200()
136 REG_WRITE(ST90TDS_AHB_DPORT_REG_ID, 0xEAFFFFFE); cw1200_load_firmware_cw1200()
141 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32); cw1200_load_firmware_cw1200()
145 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32); cw1200_load_firmware_cw1200()
263 #undef REG_WRITE cw1200_load_firmware_cw1200() macro
|
| /linux-4.4.14/drivers/media/usb/dvb-usb-v2/ |
| H A D | ce6230.h | 47 REG_WRITE = 0xcf, /* wr f */ enumerator in enum:ce6230_cmd
|
| H A D | ce6230.c | 48 case REG_WRITE: ce6230_ctrl_msg()
|
| /linux-4.4.14/arch/x86/mm/ |
| H A D | pf_in.h | 29 REG_WRITE, /* write from reg to addr */ enumerator in enum:reason_type
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| H A D | mmio-mod.c | 185 case REG_WRITE: pre()
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| H A D | pf_in.c | 156 CHECK_OP_TYPE(opcode, reg_wop, REG_WRITE); get_ins_type()
|
| /linux-4.4.14/drivers/leds/ |
| H A D | leds-dac124s085.c | 36 #define REG_WRITE (0 << 12) macro
|
| /linux-4.4.14/arch/cris/arch-v32/mach-a3/ |
| H A D | pinmux.c | 228 REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_gio_pa + 4 * port, crisv32_pinmux_set()
230 REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_iop_pa + 4 * port, crisv32_pinmux_set()
|
| /linux-4.4.14/arch/cris/arch-v32/mach-fs/ |
| H A D | pinmux.c | 191 REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_gio + 8 * port, crisv32_pinmux_set()
193 REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_iop + 8 * port, crisv32_pinmux_set()
|