86 	REG_WRITE(map->stride, crtc->primary->fb->pitches[0]);  in gma_pipe_set_base()
110 	REG_WRITE(map->cntr, dspcntr);  in gma_pipe_set_base()
119 		REG_WRITE(map->base, offset + start);  in gma_pipe_set_base()
122 		REG_WRITE(map->base, offset);  in gma_pipe_set_base()
124 		REG_WRITE(map->surf, start);  in gma_pipe_set_base()
154 			REG_WRITE(palreg + 4 * i,  in gma_crtc_load_lut()
228 			REG_WRITE(map->dpll, temp);  in gma_crtc_dpms()
232 			REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);  in gma_crtc_dpms()
236 			REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);  in gma_crtc_dpms()
245 			REG_WRITE(map->cntr,  in gma_crtc_dpms()
248 			REG_WRITE(map->base, REG_READ(map->base));  in gma_crtc_dpms()
256 			REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);  in gma_crtc_dpms()
261 		REG_WRITE(map->status, temp);  in gma_crtc_dpms()
281 		REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);  in gma_crtc_dpms()
292 			REG_WRITE(map->cntr,  in gma_crtc_dpms()
295 			REG_WRITE(map->base, REG_READ(map->base));  in gma_crtc_dpms()
302 			REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);  in gma_crtc_dpms()
314 			REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);  in gma_crtc_dpms()
327 	REG_WRITE(DSPARB, 0x3F3E);  in gma_crtc_dpms()
355 			REG_WRITE(control, temp);  in gma_crtc_cursor_set()
356 			REG_WRITE(base, 0);  in gma_crtc_cursor_set()
435 		REG_WRITE(control, temp);  in gma_crtc_cursor_set()
436 		REG_WRITE(base, addr);  in gma_crtc_cursor_set()
481 		REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);  in gma_crtc_cursor_move()
482 		REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);  in gma_crtc_cursor_move()
614 		REG_WRITE(map->dpll,  in gma_crtc_restore()
620 	REG_WRITE(map->fp0, crtc_state->saveFP0);  in gma_crtc_restore()
623 	REG_WRITE(map->fp1, crtc_state->saveFP1);  in gma_crtc_restore()
626 	REG_WRITE(map->dpll, crtc_state->saveDPLL);  in gma_crtc_restore()
630 	REG_WRITE(map->htotal, crtc_state->saveHTOTAL);  in gma_crtc_restore()
631 	REG_WRITE(map->hblank, crtc_state->saveHBLANK);  in gma_crtc_restore()
632 	REG_WRITE(map->hsync, crtc_state->saveHSYNC);  in gma_crtc_restore()
633 	REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);  in gma_crtc_restore()
634 	REG_WRITE(map->vblank, crtc_state->saveVBLANK);  in gma_crtc_restore()
635 	REG_WRITE(map->vsync, crtc_state->saveVSYNC);  in gma_crtc_restore()
636 	REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);  in gma_crtc_restore()
638 	REG_WRITE(map->size, crtc_state->saveDSPSIZE);  in gma_crtc_restore()
639 	REG_WRITE(map->pos, crtc_state->saveDSPPOS);  in gma_crtc_restore()
641 	REG_WRITE(map->src, crtc_state->savePIPESRC);  in gma_crtc_restore()
642 	REG_WRITE(map->base, crtc_state->saveDSPBASE);  in gma_crtc_restore()
643 	REG_WRITE(map->conf, crtc_state->savePIPECONF);  in gma_crtc_restore()
647 	REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);  in gma_crtc_restore()
648 	REG_WRITE(map->base, crtc_state->saveDSPBASE);  in gma_crtc_restore()
654 		REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]);  in gma_crtc_restore()