223 	REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);  in ar9003_hw_set_channel()
232 	REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);  in ar9003_hw_set_channel()
238 	REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);  in ar9003_hw_set_channel()
665 	REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);  in ar9003_hw_set_channel_regs()
671 	REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);  in ar9003_hw_set_channel_regs()
673 	REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);  in ar9003_hw_set_channel_regs()
689 	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);  in ar9003_hw_init_bb()
699 	REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);  in ar9003_hw_set_chain_masks()
700 	REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);  in ar9003_hw_set_chain_masks()
705 	REG_WRITE(ah, AR_SELFGEN_MASK, tx);  in ar9003_hw_set_chain_masks()
733 	REG_WRITE(ah, AR_PCU_MISC_MODE2, val);  in ar9003_hw_override_ini()
736 		REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,  in ar9003_hw_override_ini()
755 			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);  in ar9003_hw_override_ini()
756 			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);  in ar9003_hw_override_ini()
757 			REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);  in ar9003_hw_override_ini()
759 			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);  in ar9003_hw_override_ini()
760 			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);  in ar9003_hw_override_ini()
761 			REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);  in ar9003_hw_override_ini()
789 		REG_WRITE(ah, reg, val);  in ar9003_hw_prog_ini()
1011 	REG_WRITE(ah, AR_PHY_MODE, rfMode);  in ar9003_hw_set_rfmode()
1016 	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);  in ar9003_hw_mark_phy_inactive()
1068 	REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);  in ar9003_hw_rfbus_req()
1083 	REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);  in ar9003_hw_rfbus_done()
1492 	REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);  in ar9003_hw_set_radar_params()
1493 	REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);  in ar9003_hw_set_radar_params()
1573 	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_antdiv_comb_conf_set()
1607 	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_set_bt_ant_diversity()
1619 		REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_set_bt_ant_diversity()
1630 		REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);  in ar9003_hw_set_bt_ant_diversity()
1646 			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_set_bt_ant_diversity()
1681 			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_set_bt_ant_diversity()
1821 	REG_WRITE(ah, AR_CR, AR_CR_RXD);  in ar9003_hw_tx99_start()
1822 	REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);  in ar9003_hw_tx99_start()
1823 	REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */  in ar9003_hw_tx99_start()
1824 	REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);  in ar9003_hw_tx99_start()
1825 	REG_WRITE(ah, AR_TIME_OUT, 0x00000400);  in ar9003_hw_tx99_start()
1826 	REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);  in ar9003_hw_tx99_start()
1849 	REG_WRITE(ah, 0xa458, 0);  in ar9003_hw_tx99_set_txpower()
1851 	REG_WRITE(ah, 0xa3c0,  in ar9003_hw_tx99_set_txpower()
1856 	REG_WRITE(ah, 0xa3c4,  in ar9003_hw_tx99_set_txpower()
1861 	REG_WRITE(ah, 0xa3c8,  in ar9003_hw_tx99_set_txpower()
1865 	REG_WRITE(ah, 0xa3cc,  in ar9003_hw_tx99_set_txpower()
1870 	REG_WRITE(ah, 0xa3d0,  in ar9003_hw_tx99_set_txpower()
1875 	REG_WRITE(ah, 0xa3d4,  in ar9003_hw_tx99_set_txpower()
1880 	REG_WRITE(ah, 0xa3e4,  in ar9003_hw_tx99_set_txpower()
1885 	REG_WRITE(ah, 0xa3e8,  in ar9003_hw_tx99_set_txpower()
1890 	REG_WRITE(ah, 0xa3d8,  in ar9003_hw_tx99_set_txpower()
1895 	REG_WRITE(ah, 0xa3dc,  in ar9003_hw_tx99_set_txpower()
1900 	REG_WRITE(ah, 0xa3ec,  in ar9003_hw_tx99_set_txpower()
2089 		REG_WRITE(ah, AR_PHY_RADAR_0, val);  in ar9003_hw_bb_watchdog_check()
2094 		REG_WRITE(ah, AR_PHY_RADAR_0, val);  in ar9003_hw_bb_watchdog_check()
2125 		REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,  in ar9003_hw_bb_watchdog_config()
2131 		REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,  in ar9003_hw_bb_watchdog_config()
2142 	REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,  in ar9003_hw_bb_watchdog_config()
2167 	REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,  in ar9003_hw_bb_watchdog_config()
2188 	REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,  in ar9003_hw_bb_watchdog_read()
2247 		REG_WRITE(ah, AR_PHY_RESTART, val);  in ar9003_hw_disable_phy_restart()