101 				REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,  in ar9002_hw_set_channel()
104 				REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,  in ar9002_hw_set_channel()
152 	REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);  in ar9002_hw_set_channel()
232 	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);  in ar9002_hw_spur_mitigate()
239 	REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);  in ar9002_hw_spur_mitigate()
269 	REG_WRITE(ah, AR_PHY_TIMING11, newVal);  in ar9002_hw_spur_mitigate()
272 	REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);  in ar9002_hw_spur_mitigate()
410 	REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);  in ar9002_hw_antdiv_comb_conf_set()
429 		REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);  in ar9002_hw_set_bt_ant_diversity()
431 		REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM);  in ar9002_hw_set_bt_ant_diversity()
444 		REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);  in ar9002_hw_set_bt_ant_diversity()
450 		REG_WRITE(ah, AR_PHY_SWITCH_COM, 0);  in ar9002_hw_set_bt_ant_diversity()
466 	REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);  in ar9002_hw_set_bt_ant_diversity()
471 	REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);  in ar9002_hw_set_bt_ant_diversity()
545 	REG_WRITE(ah, AR_CR, AR_CR_RXD);  in ar9002_hw_tx99_start()
546 	REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);  in ar9002_hw_tx99_start()
547 	REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20);  in ar9002_hw_tx99_start()
548 	REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);  in ar9002_hw_tx99_start()
549 	REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum);  in ar9002_hw_tx99_start()
550 	REG_WRITE(ah, AR_TIME_OUT, 0x00000400);  in ar9002_hw_tx99_start()
551 	REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);  in ar9002_hw_tx99_start()