525 	REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);  in ath9k_hw_def_set_board_values()
538 		REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,  in ath9k_hw_def_set_board_values()
541 		REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,  in ath9k_hw_def_set_board_values()
613 	REG_WRITE(ah, AR_PHY_RF_CTL4,  in ath9k_hw_def_set_board_values()
919 				REG_WRITE(ah,  in ath9k_hw_set_def_power_cal_table()
926 				REG_WRITE(ah,  in ath9k_hw_set_def_power_cal_table()
942 				REG_WRITE(ah, regOffset, reg32);  in ath9k_hw_set_def_power_cal_table()
1242 	REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,  in ath9k_hw_def_set_txpower()
1247 	REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,  in ath9k_hw_def_set_txpower()
1256 			REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,  in ath9k_hw_def_set_txpower()
1261 			REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,  in ath9k_hw_def_set_txpower()
1267 			REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,  in ath9k_hw_def_set_txpower()
1272 			REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,  in ath9k_hw_def_set_txpower()
1280 	REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,  in ath9k_hw_def_set_txpower()
1285 	REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,  in ath9k_hw_def_set_txpower()
1292 		REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,  in ath9k_hw_def_set_txpower()
1301 		REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,  in ath9k_hw_def_set_txpower()
1311 			REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,  in ath9k_hw_def_set_txpower()
1317 			REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,  in ath9k_hw_def_set_txpower()
1325 	REG_WRITE(ah, AR_PHY_POWER_TX_SUB,  in ath9k_hw_def_set_txpower()
1336 		REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX,  in ath9k_hw_def_set_txpower()
1340 		REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER);  in ath9k_hw_def_set_txpower()