393 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_panel_vdd_on()
407 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_panel_vdd_off()
427 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_panel_on()
460 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_panel_off()
488 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_backlight_on()
504 	REG_WRITE(PP_CONTROL, pp);  in cdv_intel_edp_backlight_off()
605 			REG_WRITE(ch_data + i,  in cdv_intel_dp_aux_ch()
609 		REG_WRITE(ch_ctl,  in cdv_intel_dp_aux_ch()
626 		REG_WRITE(ch_ctl,  in cdv_intel_dp_aux_ch()
1028 		REG_WRITE(PIPE_GMCH_DATA_M(pipe),  in cdv_intel_dp_set_m_n()
1031 		REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);  in cdv_intel_dp_set_m_n()
1032 		REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);  in cdv_intel_dp_set_m_n()
1033 		REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);  in cdv_intel_dp_set_m_n()
1088 	REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));  in cdv_intel_dp_mode_set()
1102 		REG_WRITE(PFIT_CONTROL, pfit_control);  in cdv_intel_dp_mode_set()
1393 	REG_WRITE(intel_dp->output_reg, dp_reg_value);  in cdv_intel_dp_set_link_train()
1515 	REG_WRITE(intel_dp->output_reg, reg);  in cdv_intel_dp_start_link_train()
1671 	REG_WRITE(intel_dp->output_reg, reg);  in cdv_intel_dp_complete_link_train()
1692 		REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);  in cdv_intel_dp_link_down()
1698 	REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);  in cdv_intel_dp_link_down()
1990 	REG_WRITE(DSPCLK_GATE_D, reg_value);  in cdv_disable_intel_clock_gating()
2074 		REG_WRITE(PP_CONTROL, pp_on);  in cdv_intel_dp_init()
2078 		REG_WRITE(BLC_PWM_CTL2, pwm_ctrl);  in cdv_intel_dp_init()